| blob | 2c321bbcb65455b10b223316acbad03e27a0b1b3 |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2018 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
33 /* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35 #define RELOC_SECTION(HTAB, NAME) \
38 /* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40 #define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
45 /* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47 #define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
52 /* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54 #define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
59 #define elf_info_to_howto NULL
60 #define elf_info_to_howto_rel elf32_arm_info_to_howto
62 #define ARM_ELF_ABI_VERSION 0
63 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65 /* The Adjusted Place, as defined by AAELF. */
66 #define Pa(X) ((X) & 0xfffffffc)
73 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
78 {
79 /* No relocation. */
108 /* 32 bit absolute */
123 /* standard 32bit pc-relative reloc */
138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
153 /* 16 bit absolute */
168 /* 12 bit absolute */
197 /* 8 bit absolute */
296 /* BLX instruction for the ARM. */
311 /* BLX instruction for the Thumb. */
326 /* Dynamic TLS relocations. */
370 /* Relocs used in ARM Linux */
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
893 /* Group relocations. */
1273 /* End of group relocations. */
1487 /* GNU extension to record C++ vtable member usage */
1502 /* GNU extension to record C++ vtable hierarchy */
1545 /* TLS relocations */
1658 /* 112-127 private relocations. */
1676 /* R_ARM_ME_TOO, obsolete. */
1746 };
1748 /* 160 onwards: */
1750 {
1855 };
1857 /* 249-255 extended, currently unused, relocations: */
1859 {
1915 };
1919 {
1932 }
1934 static bfd_boolean
1937 {
1942 {
1943 /* xgettext:c-format */
1948 }
1950 }
1952 struct elf32_arm_reloc_map
1953 {
1954 bfd_reloc_code_real_type bfd_reloc_val;
1956 };
1958 /* All entries in this list must also be present in elf32_arm_howto_table. */
1960 {
2058 };
2062 bfd_reloc_code_real_type code)
2063 {
2071 }
2076 {
2095 }
2097 /* Support for core dump NOTE sections. */
2099 static bfd_boolean
2101 {
2106 {
2111 /* pr_cursig */
2114 /* pr_pid */
2117 /* pr_reg */
2122 }
2124 /* Make a ".reg/999" section. */
2127 }
2129 static bfd_boolean
2131 {
2133 {
2144 }
2146 /* Note that for some reason, a spurious space is tacked
2147 onto the end of the args in some (at least one anyway)
2148 implementations, so strip it off if it exists. */
2149 {
2155 }
2158 }
2163 {
2165 {
2170 {
2177 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2178 DIAGNOSTIC_PUSH;
2179 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2180 -Wstringop-truncation:
2181 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2182 */
2183 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2184 #endif
2186 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2187 DIAGNOSTIC_POP;
2188 #endif
2193 }
2196 {
2215 }
2216 }
2217 }
2219 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2221 #define TARGET_BIG_SYM arm_elf32_be_vec
2224 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2225 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2226 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2231 /* In lieu of proper flags, assume all EABIv4 or later objects are
2232 interworkable. */
2233 #define INTERWORK_FLAG(abfd) \
2234 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2235 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2236 || ((abfd)->flags & BFD_LINKER_CREATED))
2238 /* The linker script knows the section names for placement.
2239 The entry_names are used to do simple name mangling on the stubs.
2240 Given a function name, and its type, the stub can be found. The
2241 name can be changed. The only requirement is the %s be present. */
2261 /* The name of the dynamic interpreter. This is put in the .interp
2262 section. */
2265 /* FDPIC default stack size. */
2266 #define DEFAULT_STACK_SIZE 0x8000
2269 {
2273 };
2276 {
2284 + dl_tlsdesc_lazy_resolver(GOT) */
2286 };
2288 /* ARM FDPIC PLT entry. */
2289 /* The last 5 words contain PLT lazy fragment code and data. */
2291 {
2302 };
2304 /* Thumb FDPIC PLT entry. */
2305 /* The last 5 words contain PLT lazy fragment code and data. */
2307 {
2318 };
2320 #ifdef FOUR_WORD_PLT
2322 /* The first entry in a procedure linkage table looks like
2323 this. It is set up so that any shared library function that is
2324 called before the relocation has been set up calls the dynamic
2325 linker first. */
2327 {
2332 };
2334 /* Subsequent entries in a procedure linkage table look like
2335 this. */
2337 {
2342 };
2346 /* The first entry in a procedure linkage table looks like
2347 this. It is set up so that any shared library function that is
2348 called before the relocation has been set up calls the dynamic
2349 linker first. */
2351 {
2357 };
2359 /* By default subsequent entries in a procedure linkage table look like
2360 this. Offsets that don't fit into 28 bits will cause link error. */
2362 {
2366 };
2368 /* When explicitly asked, we'll use this "long" entry format
2369 which can cope with arbitrary displacements. */
2371 {
2376 };
2382 /* The first entry in a procedure linkage table looks like this.
2383 It is set up so that any shared library function that is called before the
2384 relocation has been set up calls the dynamic linker first. */
2386 {
2387 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2388 an instruction maybe encoded to one or two array elements. */
2391 /* add lr, pc */
2394 };
2396 /* Subsequent entries in a procedure linkage table for thumb only target
2397 look like this. */
2399 {
2400 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2401 an instruction maybe encoded to one or two array elements. */
2406 /* nop */
2407 };
2409 /* The format of the first entry in the procedure linkage table
2410 for a VxWorks executable. */
2412 {
2417 };
2419 /* The format of subsequent entries in a VxWorks executable. */
2421 {
2428 };
2430 /* The format of entries in a VxWorks shared library. */
2432 {
2439 };
2441 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2442 #define PLT_THUMB_STUB_SIZE 4
2444 {
2447 };
2449 /* The entries in a PLT when using a DLL-based target with multiple
2450 address spaces. */
2452 {
2455 };
2457 /* The first entry in a procedure linkage table looks like
2458 this. It is set up so that any shared library function that is
2459 called before the relocation has been set up calls the dynamic
2460 linker first. */
2462 {
2463 /* First bundle: */
2468 /* Second bundle: */
2473 /* Third bundle: */
2477 /* .Lplt_tail: */
2479 /* Fourth bundle: */
2484 };
2485 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2487 /* Subsequent entries in a procedure linkage table look like this. */
2489 {
2494 };
2496 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2497 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2498 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2499 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2500 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2501 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2502 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2503 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2505 enum stub_insn_type
2506 {
2508 THUMB32_TYPE,
2509 ARM_TYPE,
2510 DATA_TYPE
2511 };
2513 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2514 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2515 is inserted in arm_build_one_stub(). */
2516 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2517 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2518 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2519 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2520 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2521 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2522 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2523 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2526 {
2527 bfd_vma data;
2533 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2534 to reach the stub if necessary. */
2536 {
2539 };
2541 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2542 available. */
2544 {
2548 };
2550 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2552 {
2560 };
2562 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2564 {
2567 };
2569 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2570 M-profile architectures. */
2572 {
2576 };
2578 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2579 allowed. */
2581 {
2587 };
2589 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2590 available. */
2592 {
2597 };
2599 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2600 one, when the destination is close enough. */
2602 {
2606 };
2608 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2609 blx to reach the stub if necessary. */
2611 {
2615 };
2617 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2618 blx to reach the stub if necessary. We can not add into pc;
2619 it is not guaranteed to mode switch (different in ARMv6 and
2620 ARMv7). */
2622 {
2627 };
2629 /* V4T ARM -> ARM long branch stub, PIC. */
2631 {
2636 };
2638 /* V4T Thumb -> ARM long branch stub, PIC. */
2640 {
2646 };
2648 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2649 architectures. */
2651 {
2659 };
2661 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2662 allowed. */
2664 {
2671 };
2673 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2674 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2676 {
2680 };
2682 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2683 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2685 {
2691 };
2693 /* NaCl ARM -> ARM long branch stub. */
2695 {
2704 };
2706 /* NaCl ARM -> ARM long branch stub, PIC. */
2708 {
2717 };
2719 /* Stub used for transition to secure state (aka SG veneer). */
2721 {
2724 };
2727 /* Cortex-A8 erratum-workaround stubs. */
2729 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2730 can't use a conditional branch to reach this stub). */
2733 {
2737 };
2739 /* Stub used for b.w and bl.w instructions. */
2742 {
2744 };
2747 {
2749 };
2751 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2752 instruction (which switches to ARM mode) to point to this stub. Jump to the
2753 real destination using an ARM-mode branch. */
2756 {
2758 };
2760 /* For each section group there can be a specially created linker section
2761 to hold the stubs for that group. The name of the stub section is based
2762 upon the name of another section within that group with the suffix below
2763 applied.
2765 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2766 create what appeared to be a linker stub section when it actually
2767 contained user code/data. For example, consider this fragment:
2769 const char * stubborn_problems[] = { "np" };
2771 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2772 section called:
2774 .data.rel.local.stubborn_problems
2776 This then causes problems in arm32_arm_build_stubs() as it triggers:
2778 // Ignore non-stub sections.
2779 if (!strstr (stub_sec->name, STUB_SUFFIX))
2780 continue;
2782 And so the section would be ignored instead of being processed. Hence
2783 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2784 C identifier. */
2787 /* One entry per long/short branch stub defined above. */
2788 #define DEF_STUBS \
2789 DEF_STUB(long_branch_any_any) \
2790 DEF_STUB(long_branch_v4t_arm_thumb) \
2791 DEF_STUB(long_branch_thumb_only) \
2792 DEF_STUB(long_branch_v4t_thumb_thumb) \
2793 DEF_STUB(long_branch_v4t_thumb_arm) \
2794 DEF_STUB(short_branch_v4t_thumb_arm) \
2795 DEF_STUB(long_branch_any_arm_pic) \
2796 DEF_STUB(long_branch_any_thumb_pic) \
2797 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2798 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2799 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2800 DEF_STUB(long_branch_thumb_only_pic) \
2801 DEF_STUB(long_branch_any_tls_pic) \
2802 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2803 DEF_STUB(long_branch_arm_nacl) \
2804 DEF_STUB(long_branch_arm_nacl_pic) \
2805 DEF_STUB(cmse_branch_thumb_only) \
2806 DEF_STUB(a8_veneer_b_cond) \
2807 DEF_STUB(a8_veneer_b) \
2808 DEF_STUB(a8_veneer_bl) \
2809 DEF_STUB(a8_veneer_blx) \
2810 DEF_STUB(long_branch_thumb2_only) \
2811 DEF_STUB(long_branch_thumb2_only_pure)
2813 #define DEF_STUB(x) arm_stub_##x,
2814 enum elf32_arm_stub_type
2815 {
2816 arm_stub_none,
2817 DEF_STUBS
2818 max_stub_type
2819 };
2820 #undef DEF_STUB
2822 /* Note the first a8_veneer type. */
2826 {
2831 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2833 {
2835 DEF_STUBS
2836 };
2838 struct elf32_arm_stub_hash_entry
2839 {
2840 /* Base hash table entry structure. */
2843 /* The stub section. */
2846 /* Offset within stub_sec of the beginning of this stub. */
2847 bfd_vma stub_offset;
2849 /* Given the symbol's value and its section we can determine its final
2850 value when building the stubs (so the stub knows where to jump). */
2851 bfd_vma target_value;
2854 /* Same as above but for the source of the branch to the stub. Used for
2855 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2856 such, source section does not need to be recorded since Cortex-A8 erratum
2857 workaround stubs are only generated when both source and target are in the
2858 same section. */
2859 bfd_vma source_value;
2861 /* The instruction which caused this stub to be generated (only valid for
2862 Cortex-A8 erratum workaround stubs at present). */
2865 /* The stub type. */
2867 /* Its encoding size in bytes. */
2869 /* Its template. */
2871 /* The size of the template (number of entries). */
2874 /* The symbol table entry, if any, that this was derived from. */
2877 /* Type of branch. */
2880 /* Where this stub is being called from, or, in the case of combined
2881 stub sections, the first input section in the group. */
2884 /* The name for the local symbol at the start of this stub. The
2885 stub name in the hash table has to be unique; this does not, so
2886 it can be friendlier. */
2888 };
2890 /* Used to build a map of a section. This is required for mixed-endian
2891 code/data. */
2894 {
2895 bfd_vma vma;
2897 }
2898 elf32_arm_section_map;
2900 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2903 {
2904 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2905 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2906 VFP11_ERRATUM_ARM_VENEER,
2907 VFP11_ERRATUM_THUMB_VENEER
2908 }
2909 elf32_vfp11_erratum_type;
2912 {
2914 bfd_vma vma;
2915 union
2916 {
2917 struct
2918 {
2922 struct
2923 {
2928 elf32_vfp11_erratum_type type;
2929 }
2930 elf32_vfp11_erratum_list;
2932 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2933 veneer. */
2935 {
2936 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2937 STM32L4XX_ERRATUM_VENEER
2938 }
2939 elf32_stm32l4xx_erratum_type;
2942 {
2944 bfd_vma vma;
2945 union
2946 {
2947 struct
2948 {
2952 struct
2953 {
2958 elf32_stm32l4xx_erratum_type type;
2959 }
2960 elf32_stm32l4xx_erratum_list;
2963 {
2964 DELETE_EXIDX_ENTRY,
2965 INSERT_EXIDX_CANTUNWIND_AT_END
2966 }
2967 arm_unwind_edit_type;
2969 /* A (sorted) list of edits to apply to an unwind table. */
2971 {
2972 arm_unwind_edit_type type;
2973 /* Note: we sometimes want to insert an unwind entry corresponding to a
2974 section different from the one we're currently writing out, so record the
2975 (text) section this edit relates to here. */
2979 }
2980 arm_unwind_table_edit;
2983 {
2984 /* Information about mapping symbols. */
2989 /* Information about CPU errata. */
2995 /* Information about unwind tables. */
2996 union
2997 {
2998 /* Unwind info attached to a text section. */
2999 struct
3000 {
3004 /* Unwind info attached to an .ARM.exidx section. */
3005 struct
3006 {
3011 }
3012 _arm_elf_section_data;
3014 #define elf32_arm_section_data(sec) \
3015 ((_arm_elf_section_data *) elf_section_data (sec))
3017 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3018 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3019 so may be created multiple times: we use an array of these entries whilst
3020 relaxing which we can refresh easily, then create stubs for each potentially
3021 erratum-triggering instruction once we've settled on a solution. */
3023 struct a8_erratum_fix
3024 {
3027 bfd_vma offset;
3028 bfd_vma target_offset;
3033 };
3035 /* A table of relocs applied to branches which might trigger Cortex-A8
3036 erratum. */
3038 struct a8_erratum_reloc
3039 {
3040 bfd_vma from;
3041 bfd_vma destination;
3046 bfd_boolean non_a8_stub;
3047 };
3049 /* The size of the thread control block. */
3050 #define TCB_SIZE 8
3052 /* ARM-specific information about a PLT entry, over and above the usual
3053 gotplt_union. */
3054 struct arm_plt_info
3055 {
3056 /* We reference count Thumb references to a PLT entry separately,
3057 so that we can emit the Thumb trampoline only if needed. */
3058 bfd_signed_vma thumb_refcount;
3060 /* Some references from Thumb code may be eliminated by BL->BLX
3061 conversion, so record them separately. */
3062 bfd_signed_vma maybe_thumb_refcount;
3064 /* How many of the recorded PLT accesses were from non-call relocations.
3065 This information is useful when deciding whether anything takes the
3066 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3067 non-call references to the function should resolve directly to the
3068 real runtime target. */
3071 /* Since PLT entries have variable size if the Thumb prologue is
3072 used, we need to record the index into .got.plt instead of
3073 recomputing it from the PLT offset. */
3074 bfd_signed_vma got_offset;
3075 };
3077 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3078 struct arm_local_iplt_info
3079 {
3080 /* The information that is usually found in the generic ELF part of
3081 the hash table entry. */
3084 /* The information that is usually found in the ARM-specific part of
3085 the hash table entry. */
3088 /* A list of all potential dynamic relocations against this symbol. */
3090 };
3092 /* Structure to handle FDPIC support for local functions. */
3097 };
3099 struct elf_arm_obj_tdata
3100 {
3103 /* tls_type for each local got entry. */
3106 /* GOTPLT entries for TLS descriptors. */
3109 /* Information for local symbols that need entries in .iplt. */
3112 /* Zero to warn when linking objects with incompatible enum sizes. */
3115 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3118 /* Maintains FDPIC counters and funcdesc info. */
3120 };
3122 #define elf_arm_tdata(bfd) \
3123 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3125 #define elf32_arm_local_got_tls_type(bfd) \
3126 (elf_arm_tdata (bfd)->local_got_tls_type)
3128 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3129 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3131 #define elf32_arm_local_iplt(bfd) \
3132 (elf_arm_tdata (bfd)->local_iplt)
3134 #define elf32_arm_local_fdpic_cnts(bfd) \
3135 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3137 #define is_arm_elf(bfd) \
3138 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3139 && elf_tdata (bfd) != NULL \
3140 && elf_object_id (bfd) == ARM_ELF_DATA)
3142 static bfd_boolean
3144 {
3146 ARM_ELF_DATA);
3147 }
3149 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3151 /* Structure to handle FDPIC support for extern functions. */
3158 };
3160 /* Arm ELF linker hash entry. */
3161 struct elf32_arm_link_hash_entry
3162 {
3165 /* Track dynamic relocs copied for this symbol. */
3168 /* ARM-specific PLT information. */
3171 #define GOT_UNKNOWN 0
3172 #define GOT_NORMAL 1
3173 #define GOT_TLS_GD 2
3174 #define GOT_TLS_IE 4
3175 #define GOT_TLS_GDESC 8
3176 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3179 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3184 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3185 starting at the end of the jump table. */
3186 bfd_vma tlsdesc_got;
3188 /* The symbol marking the real symbol location for exported thumb
3189 symbols with Arm stubs. */
3192 /* A pointer to the most recently used stub hash entry against this
3193 symbol. */
3196 /* Counter for FDPIC relocations against this symbol. */
3198 };
3200 /* Traverse an arm ELF linker hash table. */
3201 #define elf32_arm_link_hash_traverse(table, func, info) \
3202 (elf_link_hash_traverse \
3203 (&(table)->root, \
3204 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
3205 (info)))
3207 /* Get the ARM elf linker hash table from a link_info structure. */
3208 #define elf32_arm_hash_table(info) \
3209 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3210 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
3212 #define arm_stub_hash_lookup(table, string, create, copy) \
3213 ((struct elf32_arm_stub_hash_entry *) \
3214 bfd_hash_lookup ((table), (string), (create), (copy)))
3216 /* Array to keep track of which stub sections have been created, and
3217 information on stub grouping. */
3218 struct map_stub
3219 {
3220 /* This is the section to which stubs in the group will be
3221 attached. */
3223 /* The stub section. */
3225 };
3227 #define elf32_arm_compute_jump_table_size(htab) \
3228 ((htab)->next_tls_desc_index * 4)
3230 /* ARM ELF linker hash table. */
3231 struct elf32_arm_link_hash_table
3232 {
3233 /* The main hash table. */
3236 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3237 bfd_size_type thumb_glue_size;
3239 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3240 bfd_size_type arm_glue_size;
3242 /* The size in bytes of section containing the ARMv4 BX veneers. */
3243 bfd_size_type bx_glue_size;
3245 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3246 veneer has been populated. */
3249 /* The size in bytes of the section containing glue for VFP11 erratum
3250 veneers. */
3251 bfd_size_type vfp11_erratum_glue_size;
3253 /* The size in bytes of the section containing glue for STM32L4XX erratum
3254 veneers. */
3255 bfd_size_type stm32l4xx_erratum_glue_size;
3257 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3258 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3259 elf32_arm_write_section(). */
3263 /* An arbitrary input BFD chosen to hold the glue sections. */
3266 /* Nonzero to output a BE8 image. */
3269 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3270 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3273 /* The relocation to use for R_ARM_TARGET2 relocations. */
3276 /* 0 = Ignore R_ARM_V4BX.
3277 1 = Convert BX to MOV PC.
3278 2 = Generate v4 interworing stubs. */
3281 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3284 /* Whether we should fix the ARM1176 BLX immediate issue. */
3287 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3290 /* What sort of code sequences we should look for which may trigger the
3291 VFP11 denorm erratum. */
3292 bfd_arm_vfp11_fix vfp11_fix;
3294 /* Global counter for the number of fixes we have emitted. */
3297 /* What sort of code sequences we should look for which may trigger the
3298 STM32L4XX erratum. */
3299 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3301 /* Global counter for the number of fixes we have emitted. */
3304 /* Nonzero to force PIC branch veneers. */
3307 /* The number of bytes in the initial entry in the PLT. */
3308 bfd_size_type plt_header_size;
3310 /* The number of bytes in the subsequent PLT etries. */
3311 bfd_size_type plt_entry_size;
3313 /* True if the target system is VxWorks. */
3316 /* True if the target system is Symbian OS. */
3319 /* True if the target system is Native Client. */
3322 /* True if the target uses REL relocations. */
3323 bfd_boolean use_rel;
3325 /* Nonzero if import library must be a secure gateway import library
3326 as per ARMv8-M Security Extensions. */
3329 /* The import library whose symbols' address must remain stable in
3330 the import library generated. */
3333 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3334 bfd_vma next_tls_desc_index;
3336 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3337 bfd_vma num_tls_desc;
3339 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3342 /* The offset into splt of the PLT entry for the TLS descriptor
3343 resolver. Special values are 0, if not necessary (or not found
3344 to be necessary yet), and -1 if needed but not determined
3345 yet. */
3346 bfd_vma dt_tlsdesc_plt;
3348 /* The offset into sgot of the GOT entry used by the PLT entry
3349 above. */
3350 bfd_vma dt_tlsdesc_got;
3352 /* Offset in .plt section of tls_arm_trampoline. */
3353 bfd_vma tls_trampoline;
3355 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3356 union
3357 {
3358 bfd_signed_vma refcount;
3359 bfd_vma offset;
3362 /* Small local sym cache. */
3365 /* For convenience in allocate_dynrelocs. */
3368 /* The amount of space used by the reserved portion of the sgotplt
3369 section, plus whatever space is used by the jump slots. */
3370 bfd_vma sgotplt_jump_table_size;
3372 /* The stub hash table. */
3375 /* Linker stub bfd. */
3378 /* Linker call-backs. */
3383 /* Array to keep track of which stub sections have been created, and
3384 information on stub grouping. */
3387 /* Input stub section holding secure gateway veneers. */
3390 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3391 start to be allocated. */
3392 bfd_vma new_cmse_stub_offset;
3394 /* Number of elements in stub_group. */
3397 /* Assorted information used by elf32_arm_size_stubs. */
3402 /* True if the target system uses FDPIC. */
3405 /* Fixup section. Used for FDPIC. */
3407 };
3409 /* Add an FDPIC read-only fixup. */
3410 static void
3412 {
3413 bfd_vma fixup_offset;
3418 }
3422 {
3423 #if GCC_VERSION >= 3004
3425 #else
3429 {
3433 }
3435 #endif
3436 }
3440 {
3441 #if GCC_VERSION >= 3004
3443 #else
3448 {
3450 sum++;
3452 }
3454 #endif
3455 }
3460 static void
3466 bfd_vma addr,
3467 bfd_vma dynreloc_value,
3468 bfd_vma seg)
3469 {
3471 {
3476 {
3478 Elf_Internal_Rela outrel;
3487 }
3488 else
3489 {
3503 }
3505 }
3506 }
3508 /* Create an entry in an ARM ELF linker hash table. */
3514 {
3518 /* Allocate the structure if it has not already been allocated by a
3519 subclass. */
3526 /* Call the allocation method of the superclass. */
3531 {
3549 }
3552 }
3554 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3555 symbols. */
3557 static bfd_boolean
3559 {
3561 {
3562 bfd_size_type num_syms;
3563 bfd_size_type size;
3589 }
3591 }
3593 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3594 to input bfd ABFD. Create the information if it doesn't already exist.
3595 Return null if an allocation fails. */
3599 {
3610 }
3612 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3613 in ABFD's symbol table. If the symbol is global, H points to its
3614 hash table entry, otherwise H is null.
3616 Return true if the symbol does have PLT information. When returning
3617 true, point *ROOT_PLT at the target-independent reference count/offset
3618 union and *ARM_PLT at the ARM-specific information. */
3620 static bfd_boolean
3625 {
3632 {
3636 }
3648 }
3652 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3653 before it. */
3655 static bfd_boolean
3658 {
3665 }
3667 /* Return a pointer to the head of the dynamic reloc list that should
3668 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3669 ABFD's symbol table. Return null if an error occurs. */
3674 {
3676 {
3683 }
3684 else
3685 {
3686 /* Track dynamic relocs needed for local syms too.
3687 We really need local syms available to do this
3688 easily. Oh well. */
3698 }
3699 }
3701 /* Initialize an entry in the stub hash table. */
3707 {
3708 /* Allocate the structure if it has not already been allocated by a
3709 subclass. */
3711 {
3716 }
3718 /* Call the allocation method of the superclass. */
3721 {
3724 /* Initialize the local fields. */
3739 }
3742 }
3744 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3745 shortcuts to them in our hash table. */
3747 static bfd_boolean
3749 {
3756 /* BPABI objects never have a GOT, or associated sections. */
3763 /* Also create .rofixup. */
3765 {
3771 }
3774 }
3776 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3778 static bfd_boolean
3780 {
3785 flagword flags;
3793 {
3800 }
3803 {
3811 }
3814 {
3820 }
3822 }
3824 /* Determine if we're dealing with a Thumb only architecture. */
3826 static bfd_boolean
3828 {
3831 Tag_CPU_arch_profile);
3838 /* Force return logic to be reviewed for each new architecture. */
3849 }
3851 /* Determine if we're dealing with a Thumb-2 object. */
3853 static bfd_boolean
3855 {
3858 Tag_THUMB_ISA_use);
3865 /* Force return logic to be reviewed for each new architecture. */
3874 }
3876 /* Determine whether Thumb-2 BL instruction is available. */
3878 static bfd_boolean
3880 {
3884 /* Force return logic to be reviewed for each new architecture. */
3887 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3890 }
3892 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3893 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3894 hash table. */
3896 static bfd_boolean
3898 {
3912 {
3917 {
3919 htab->plt_entry_size
3921 }
3922 else
3923 {
3924 htab->plt_header_size
3926 htab->plt_entry_size
3928 }
3932 }
3933 else
3934 {
3935 /* PR ld/16017
3936 Test for thumb only architectures. Note - we cannot just call
3937 using_thumb_only() as the attributes in the output bfd have not been
3938 initialised at this point, so instead we use the input bfd. */
3943 {
3946 }
3948 }
3954 else
3956 }
3965 }
3967 /* Copy the extra info we tack onto an elf_link_hash_entry. */
3969 static void
3973 {
3980 {
3982 {
3986 /* Add reloc counts against the indirect sym to the direct sym
3987 list. Merge any entries against the same section. */
3989 {
3994 {
3999 }
4002 }
4004 }
4008 }
4011 {
4012 /* Copy over PLT info. */
4020 /* Copy FDPIC counters. */
4025 /* We should only allocate a function to .iplt once the final
4026 symbol information is known. */
4030 {
4033 }
4034 }
4037 }
4039 /* Destroy an ARM elf linker hash table. */
4041 static void
4043 {
4049 }
4051 /* Create an ARM elf linker hash table. */
4055 {
4064 elf32_arm_link_hash_newfunc,
4066 ARM_ELF_DATA))
4067 {
4070 }
4074 #ifdef FOUR_WORD_PLT
4077 #else
4080 #endif
4087 {
4090 }
4094 }
4096 /* Determine what kind of NOPs are available. */
4098 static bfd_boolean
4100 {
4102 Tag_CPU_arch);
4104 /* Force return logic to be reviewed for each new architecture. */
4112 }
4114 static bfd_boolean
4116 {
4118 {
4135 }
4136 }
4138 /* Determine the type of stub needed, if any, for a call. */
4140 static enum elf32_arm_stub_type
4147 bfd_vma destination,
4151 {
4152 bfd_vma location;
4153 bfd_signed_vma branch_offset;
4178 /* True for architectures that implement the thumb2 movw instruction. */
4181 /* Determine where the call point is. */
4188 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4189 are considering a function call relocation. */
4195 /* For TLS call relocs, it is the caller's responsibility to provide
4196 the address of the appropriate trampoline. */
4203 {
4208 else
4211 {
4214 /* Note when dealing with PLT entries: the main PLT stub is in
4215 ARM mode, so if the branch is in Thumb mode, another
4216 Thumb->ARM stub will be inserted later just before the ARM
4217 PLT stub. If a long branch stub is needed, we'll add a
4218 Thumb->Arm one and branch directly to the ARM PLT entry.
4219 Here, we have to check if a pre-PLT Thumb->ARM stub
4220 is needed and if it will be close enough. */
4227 /* Thumb branch/call to PLT: it can become a branch to ARM
4228 or to Thumb. We must perform the same checks and
4229 corrections as in elf32_arm_final_link_relocate. */
4232 {
4236 {
4237 /* If the Thumb BLX instruction is available, convert
4238 the BL to a BLX instruction to call the ARM-mode
4239 PLT entry. */
4241 }
4242 else
4243 {
4245 /* Target the Thumb stub before the ARM PLT entry. */
4248 }
4249 }
4250 else
4251 {
4253 }
4254 }
4255 }
4256 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4263 {
4264 /* Handle cases where:
4265 - this call goes too far (different Thumb/Thumb2 max
4266 distance)
4267 - it's a Thumb->Arm call and blx is not available, or it's a
4268 Thumb->Arm branch (not bl). A stub is needed in this case,
4269 but only if this call is not through a PLT entry. Indeed,
4270 PLT stubs handle mode switching already. */
4274 || (thumb2_bl
4277 || (thumb2
4287 {
4288 /* If we need to insert a Thumb-Thumb long branch stub to a
4289 PLT, use one that branches directly to the ARM PLT
4290 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4291 stub, undo this now. */
4293 {
4296 }
4299 {
4300 /* Thumb to thumb. */
4302 {
4304 _bfd_error_handler
4306 " section with SHF_ARM_PURECODE section"
4307 " attribute is only supported for M-profile"
4312 /* PIC stubs. */
4315 /* V5T and above. Stub starts with ARM code, so
4316 we must be able to switch mode before
4317 reaching it, which is only possible for 'bl'
4318 (ie R_ARM_THM_CALL relocation). */
4319 ? arm_stub_long_branch_any_thumb_pic
4320 /* On V4T, use Thumb code only. */
4323 /* non-PIC stubs. */
4326 /* V5T and above. */
4327 ? arm_stub_long_branch_any_any
4328 /* V4T. */
4330 }
4331 else
4332 {
4335 else
4336 {
4338 _bfd_error_handler
4340 " section with SHF_ARM_PURECODE section"
4341 " attribute is only supported for M-profile"
4346 /* PIC stub. */
4347 ? arm_stub_long_branch_thumb_only_pic
4348 /* non-PIC stub. */
4351 }
4352 }
4353 }
4354 else
4355 {
4357 _bfd_error_handler
4359 " section with SHF_ARM_PURECODE section"
4364 /* Thumb to arm. */
4368 {
4369 _bfd_error_handler
4373 }
4375 stub_type =
4377 /* PIC stubs. */
4379 /* TLS PIC stubs. */
4383 /* V5T PIC and above. */
4384 ? arm_stub_long_branch_any_arm_pic
4385 /* V4T PIC stub. */
4388 /* non-PIC stubs. */
4390 /* V5T and above. */
4391 ? arm_stub_long_branch_any_any
4392 /* V4T. */
4395 /* Handle v4t short branches. */
4400 }
4401 }
4402 }
4407 {
4409 _bfd_error_handler
4411 " section with SHF_ARM_PURECODE section"
4412 " attribute is only supported for M-profile"
4416 {
4417 /* Arm to thumb. */
4422 {
4423 _bfd_error_handler
4427 }
4429 /* We have an extra 2-bytes reach because of
4430 the mode change (bit 24 (H) of BLX encoding). */
4436 {
4438 /* PIC stubs. */
4440 /* V5T and above. */
4441 ? arm_stub_long_branch_any_thumb_pic
4442 /* V4T stub. */
4445 /* non-PIC stubs. */
4447 /* V5T and above. */
4448 ? arm_stub_long_branch_any_any
4449 /* V4T. */
4451 }
4452 }
4453 else
4454 {
4455 /* Arm to arm. */
4458 {
4459 stub_type =
4461 /* PIC stubs. */
4463 /* TLS PIC Stub. */
4464 ? arm_stub_long_branch_any_tls_pic
4466 ? arm_stub_long_branch_arm_nacl_pic
4468 /* non-PIC stubs. */
4470 ? arm_stub_long_branch_arm_nacl
4472 }
4473 }
4474 }
4476 /* If a stub is needed, record the actual destination type. */
4481 }
4483 /* Build a name for an entry in the stub hash table. */
4491 {
4493 bfd_size_type len;
4496 {
4505 }
4506 else
4507 {
4519 }
4522 }
4524 /* Look up an entry in the stub hash. Stub entries are cached because
4525 creating the stub name takes a bit of time. */
4534 {
4542 /* If this input section is part of a group of sections sharing one
4543 stub section, then use the id of the first section in the group.
4544 Stub names need to include a section id, as there may well be
4545 more than one stub used to reach say, printf, and we need to
4546 distinguish between them. */
4554 {
4556 }
4557 else
4558 {
4571 }
4574 }
4576 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4577 section. */
4579 static bfd_boolean
4581 {
4586 {
4592 }
4595 }
4597 /* Required alignment (as a power of 2) for the dedicated section holding
4598 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4599 with input sections. */
4601 static int
4602 arm_dedicated_stub_output_section_required_alignment
4604 {
4609 {
4610 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4611 boundary. */
4618 }
4621 }
4623 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4624 NULL if veneers of this type are interspersed with input sections. */
4628 {
4633 {
4640 }
4643 }
4645 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4646 returns the address of the hash table field in HTAB holding a pointer to the
4647 corresponding input section. Otherwise, returns NULL. */
4652 {
4657 {
4664 }
4667 }
4669 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4670 is the section that branch into veneer and can be NULL if stub should go in
4671 a dedicated output section. Returns a pointer to the stub section, and the
4672 section to which the stub section will be attached (in *LINK_SEC_P).
4673 LINK_SEC_P may be NULL. */
4679 {
4682 bfd_boolean dedicated_output_section =
4687 {
4697 {
4701 }
4702 }
4703 else
4704 {
4714 }
4717 {
4719 bfd_size_type len;
4731 align);
4738 }
4747 }
4749 /* Add a new stub entry to the stub hash. Not all fields of the new
4750 stub entry are initialised. */
4756 {
4762 stub_type);
4766 /* Enter this entry into the linker stub hash table. */
4770 {
4776 }
4783 }
4785 /* Store an Arm insn into an output section not processed by
4786 elf32_arm_write_section. */
4788 static void
4791 {
4794 else
4796 }
4798 /* Store a 16-bit Thumb insn into an output section not processed by
4799 elf32_arm_write_section. */
4801 static void
4804 {
4807 else
4809 }
4811 /* Store a Thumb2 insn into an output section not processed by
4812 elf32_arm_write_section. */
4814 static void
4817 {
4818 /* T2 instructions are 16-bit streamed. */
4820 {
4823 }
4824 else
4825 {
4828 }
4829 }
4831 /* If it's possible to change R_TYPE to a more efficient access
4832 model, return the new reloc type. */
4834 static unsigned
4837 {
4844 /* We do not support relaxations for Old TLS models. */
4846 {
4853 }
4856 }
4858 static bfd_reloc_status_type elf32_arm_final_link_relocate
4864 static unsigned int
4866 {
4868 {
4900 }
4901 }
4903 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4904 veneering (TRUE) or have their own symbol (FALSE). */
4906 static bfd_boolean
4908 {
4913 {
4919 }
4922 }
4924 /* Returns the padding needed for the dedicated section used stubs of type
4925 STUB_TYPE. */
4927 static int
4929 {
4934 {
4940 }
4943 }
4945 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4946 returns the address of the hash table field in HTAB holding the offset at
4947 which new veneers should be layed out in the stub section. */
4952 {
4954 {
4961 }
4962 }
4964 static bfd_boolean
4967 {
4968 #define MAXRELOCS 3
4969 bfd_boolean removed_sg_veneer;
4976 bfd_vma sym_value;
4986 /* Massage our args to the form they really have. */
4998 /* We have to do less-strictly-aligned fixes last. */
5001 /* Assign a slot at the end of section if none assigned yet. */
5003 {
5006 }
5011 /* This is the address of the stub destination. */
5021 {
5023 {
5025 {
5028 {
5029 /* We've borrowed the reloc_addend field to mean we should
5030 insert a condition code into this (Thumb-1 branch)
5031 instruction. See THUMB16_BCOND_INSN. */
5034 }
5037 }
5047 {
5050 }
5057 /* Handle cases where the target is encoded within the
5058 instruction. */
5060 {
5063 }
5077 }
5078 }
5083 /* Stub size has already been computed in arm_size_one_stub. Check
5084 consistency. */
5087 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5091 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5092 to relocate in each stub. */
5093 removed_sg_veneer =
5098 {
5099 Elf_Internal_Rela rel;
5100 bfd_boolean unresolved_reloc;
5102 bfd_vma points_to =
5111 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5112 template should refer back to the instruction after the original
5113 branch. We use target_section as Cortex-A8 erratum workaround stubs
5114 are only generated when both source and target are in the same
5115 section. */
5127 }
5130 #undef MAXRELOCS
5131 }
5133 /* Calculate the template, template size and instruction size for a stub.
5134 Return value is the instruction size. */
5136 static unsigned int
5140 {
5155 {
5157 {
5171 }
5172 }
5175 }
5177 /* As above, but don't actually build the stub. Just bump offset so
5178 we know stub section sizes. */
5180 static bfd_boolean
5183 {
5188 /* Massage our args to the form they really have. */
5197 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5199 {
5203 }
5205 /* Already accounted for. */
5213 }
5215 /* External entry points for sizing and building linker stubs. */
5217 /* Set up various things so that we can make a list of input sections
5218 for each output section included in the link. Returns -1 on error,
5219 0 when no stubs will be needed, and 1 on success. */
5221 int
5224 {
5230 bfd_size_type amt;
5238 /* Count the number of input BFDs and find the top input section id. */
5242 {
5247 {
5250 }
5251 }
5260 /* We can't use output_bfd->section_count here to find the top output
5261 section index as some sections may have been removed, and
5262 _bfd_strip_section_from_output doesn't renumber the indices. */
5266 {
5269 }
5278 /* For sections we aren't interested in, mark their entries with a
5279 value we can check later. */
5281 do
5288 {
5291 }
5294 }
5296 /* The linker repeatedly calls this function for each input section,
5297 in the order that input sections are linked into output sections.
5298 Build lists of input sections to determine groupings between which
5299 we may insert linker stubs. */
5301 void
5304 {
5311 {
5315 {
5316 /* Steal the link_sec pointer for our list. */
5317 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5318 /* This happens to make the list in reverse order,
5319 which we reverse later. */
5322 }
5323 }
5324 }
5326 /* See whether we can group stub sections together. Grouping stub
5327 sections may result in fewer stubs. More importantly, we need to
5328 put all .init* and .fini* stubs at the end of the .init or
5329 .fini output sections respectively, because glibc splits the
5330 _init and _fini functions into multiple parts. Putting a stub in
5331 the middle of a function is not a good idea. */
5333 static void
5335 bfd_size_type stub_group_size,
5336 bfd_boolean stubs_always_after_branch)
5337 {
5340 do
5341 {
5348 /* Reverse the list: we must avoid placing stubs at the
5349 beginning of the section because the beginning of the text
5350 section may be required for an interrupt vector in bare metal
5351 code. */
5352 #define NEXT_SEC PREV_SEC
5355 {
5356 /* Pop from tail. */
5360 /* Push on head. */
5363 }
5366 {
5370 bfd_vma end_of_next;
5374 {
5378 /* End of NEXT is too far from start, so stop. */
5380 /* Add NEXT to the group. */
5382 }
5384 /* OK, the size from the start to the start of CURR is less
5385 than stub_group_size and thus can be handled by one stub
5386 section. (Or the head section is itself larger than
5387 stub_group_size, in which case we may be toast.)
5388 We should really be keeping track of the total size of
5389 stubs added here, as stubs contribute to the final output
5390 section size. */
5391 do
5392 {
5394 /* Set up this stub group. */
5396 }
5399 /* But wait, there's more! Input sections up to stub_group_size
5400 bytes after the stub section can be handled by it too. */
5402 {
5406 {
5409 /* End of NEXT is too far from stubs, so stop. */
5411 /* Add NEXT to the stub group. */
5415 }
5416 }
5418 }
5419 }
5423 #undef PREV_SEC
5424 #undef NEXT_SEC
5425 }
5427 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5428 erratum fix. */
5430 static int
5432 {
5440 else
5442 }
5447 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5448 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5449 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5450 otherwise. */
5452 static bfd_boolean
5462 {
5475 {
5479 bfd_vma base_vma;
5498 {
5509 /* Span is entirely within a single 4KB region: skip scanning. */
5514 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5516 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5517 * The branch target is in the same 4KB region as the
5518 first half of the branch.
5519 * The instruction before the branch is a 32-bit
5520 length non-branch instruction. */
5522 {
5531 {
5532 /* Load the rest of the insn (in manual-friendly order). */
5535 /* Encoding T4: B<c>.W. */
5537 /* Encoding T1: BL<c>.W. */
5539 /* Encoding T2: BLX<c>.W. */
5541 /* Encoding T3: B<c>.W (not permitted in IT block). */
5544 }
5549 && insn_32bit
5550 && is_32bit_branch
5551 && last_was_32bit
5553 {
5557 bfd_vma target;
5569 {
5573 /* We don't care about the error returned from this
5574 function, only if there is glue or not. */
5581 /* Keep a simpler condition, for the sake of clarity. */
5587 {
5591 else
5593 }
5594 }
5596 /* Check if we have an offending branch instruction. */
5599 /* We've already made a stub for this instruction, e.g.
5600 it's a long branch or a Thumb->ARM stub. Assume that
5601 stub will suffice to work around the A8 erratum (see
5602 setting of always_after_branch above). */
5603 ;
5605 {
5614 }
5616 {
5636 }
5639 {
5642 /* The original instruction is a BL, but the target is
5643 an ARM instruction. If we were not making a stub,
5644 the BL would have been converted to a BLX. Use the
5645 BLX stub instead in that case. */
5648 {
5652 }
5653 /* Conversely, if the original instruction was
5654 BLX but the target is Thumb mode, use the BL
5655 stub. */
5658 {
5662 }
5667 /* If we found a relocation, use the proper destination,
5668 not the offset in the (unrelocated) instruction.
5669 Note this is always done if we switched the stub type
5670 above. */
5672 offset =
5675 /* If the stub will use a Thumb-mode branch to a
5676 PLT target, redirect it to the preceding Thumb
5677 entry point. */
5683 /* The BLX stub is ARM-mode code. Adjust the offset to
5684 take the different PC value (+8 instead of +4) into
5685 account. */
5690 {
5694 {
5700 }
5703 {
5704 /* If we're doing a subsequent scan,
5705 check if we've found the same fix as
5706 before, and try and reuse the stub
5707 name. */
5711 {
5715 }
5716 }
5719 {
5723 }
5736 num_a8_fixes++;
5737 }
5738 }
5739 }
5744 }
5745 }
5749 }
5756 }
5758 /* Create or update a stub entry depending on whether the stub can already be
5759 found in HTAB. The stub is identified by:
5760 - its type STUB_TYPE
5761 - its source branch (note that several can share the same stub) whose
5762 section and relocation (if any) are given by SECTION and IRELA
5763 respectively
5764 - its target symbol whose input section, hash, name, value and branch type
5765 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5766 respectively
5768 If found, the value of the stub's target symbol is updated from SYM_VALUE
5769 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5770 TRUE and the stub entry is initialized.
5772 Returns the stub that was created or updated, or NULL if an error
5773 occurred. */
5782 {
5794 else
5795 {
5800 /* Support for grouping stub sections. */
5803 /* Get the name of this stub. */
5805 stub_type);
5808 }
5811 FALSE);
5812 /* The proper stub has already been created, just update its value. */
5814 {
5819 }
5823 {
5827 }
5837 else
5838 {
5845 {
5848 }
5850 /* For historical reasons, use the existing names for ARM-to-Thumb and
5851 Thumb-to-ARM stubs. */
5862 else
5864 }
5868 }
5870 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5871 gateway veneer to transition from non secure to secure state and create them
5872 accordingly.
5874 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5875 defines the conditions that govern Secure Gateway veneer creation for a
5876 given symbol <SYM> as follows:
5877 - it has function type
5878 - it has non local binding
5879 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5880 same type, binding and value as <SYM> (called normal symbol).
5881 An entry function can handle secure state transition itself in which case
5882 its special symbol would have a different value from the normal symbol.
5884 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5885 entry mapping while HTAB gives the name to hash entry mapping.
5886 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5887 created.
5889 The return value gives whether a stub failed to be allocated. */
5891 static bfd_boolean
5895 {
5903 bfd_vma sym_value;
5919 NULL);
5923 /* Scan symbols. */
5925 {
5929 {
5931 /* Not a special symbol. */
5937 /* Special symbol with local binding. */
5939 }
5940 else
5941 {
5945 /* Not a special symbol. */
5949 /* Special symbol has incorrect binding or type. */
5954 }
5957 {
5963 }
5966 {
5973 }
5979 /* No associated normal symbol or it is neither global nor weak. */
5984 {
5985 /* Initialize here to avoid warning about use of possibly
5986 uninitialized variable. */
5990 {
5991 /* Searching for a normal symbol with local binding. */
5993 {
5994 lsym_name =
6000 }
6001 }
6004 {
6005 _bfd_error_handler
6009 }
6010 else
6011 _bfd_error_handler
6016 }
6022 {
6023 _bfd_error_handler
6027 }
6031 /* If this section is a link-once section that will be discarded, then
6032 don't create any stubs. */
6034 {
6035 _bfd_error_handler
6038 }
6041 {
6042 _bfd_error_handler
6045 }
6050 stub_entry
6057 else
6058 {
6061 }
6062 }
6067 }
6069 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6070 code entry function, ie can be called from non secure code without using a
6071 veneer. */
6073 static bfd_boolean
6075 {
6079 file_ptr offset;
6082 /* Defined symbol of function type. */
6089 /* Read first instruction. */
6099 /* Starts by SG instruction. */
6101 }
6103 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6104 secure gateway veneers (ie. the veneers was not in the input import library)
6105 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6107 static bfd_boolean
6109 {
6113 /* Massage our args to the form they really have. */
6127 }
6129 /* Set offset of each secure gateway veneers so that its address remain
6130 identical to the one in the input import library referred by
6131 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6132 (present in input import library but absent from the executable being
6133 linked) or if new veneers appeared and there is no output import library
6134 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6135 number of secure gateway veneers found in the input import library.
6137 The function returns whether an error occurred. If no error occurred,
6138 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6139 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6140 veneer observed set for new veneers to be layed out after. */
6142 static bfd_boolean
6146 {
6149 flagword flags;
6156 bfd_size_type cmse_stub_size;
6165 /* No input secure gateway import library. */
6171 {
6175 }
6177 /* Get symbol table size. */
6182 /* Read in the input secure gateway import library's symbol table. */
6186 {
6189 }
6192 cmse_stub_size =
6196 out_sec_name =
6198 stub_out_sec =
6203 /* Set addresses of veneers mentionned in input secure gateway import
6204 library's symbol table. */
6206 {
6217 {
6219 "symbol should be absolute, global and "
6224 }
6233 /* Stub entry should have been created by cmse_scan or the symbol be of
6234 a secure function callable from non secure code. */
6236 {
6237 bfd_boolean new_stub;
6239 _bfd_error_handler
6243 stub_entry
6250 else
6251 {
6253 new_cmse_stubs_created++;
6255 }
6258 }
6259 /* Symbol found is not callable from non secure code. */
6261 {
6263 {
6265 sym_name);
6267 }
6269 }
6270 else
6271 {
6272 /* Only stubs for SG veneers should have been created. */
6275 /* Check visibility hasn't changed. */
6278 _bfd_error_handler
6280 sym_name);
6283 }
6285 /* Size should match that of a SG veneer. */
6287 {
6291 }
6293 /* Previous veneer address is before current SG veneer section. */
6295 {
6296 /* Avoid offset underflow. */
6301 }
6303 /* Complain if stub offset not a multiple of stub size. */
6305 {
6306 _bfd_error_handler
6310 }
6315 new_cmse_stubs_created--;
6321 }
6324 {
6326 _bfd_error_handler
6330 }
6333 {
6334 _bfd_error_handler
6336 out_sec_name);
6338 }
6340 free_sym_buf:
6343 }
6345 /* Determine and set the size of the stub section for a final link.
6347 The basic idea here is to examine all the relocations looking for
6348 PC-relative calls to a target that is unreachable with a "bl"
6349 instruction. */
6351 bfd_boolean
6355 bfd_signed_vma group_size,
6357 asection *,
6360 {
6364 bfd_size_type stub_group_size;
6376 {
6381 }
6383 /* Propagate mach to stub bfd, because it may not have been
6384 finalized when we created stub_bfd. */
6388 /* Stash our params away. */
6397 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6398 as the first half of a 32-bit branch straddling two 4K pages. This is a
6399 crude way of enforcing that. */
6405 else
6409 {
6410 /* Default values. */
6411 /* Thumb branch range is +-4MB has to be used as the default
6412 maximum size (a given section can contain both ARM and Thumb
6413 code, so the worst case has to be taken into account).
6415 This value is 24K less than that, which allows for 2025
6416 12-byte stubs. If we exceed that, then we will fail to link.
6417 The user will have to relink with an explicit group size
6418 option. */
6420 }
6424 /* If we're applying the cortex A8 fix, we need to determine the
6425 program header size now, because we cannot change it later --
6426 that could alter section placements. Notice the A8 erratum fix
6427 ends up requiring the section addresses to remain unchanged
6428 modulo the page size. That's something we cannot represent
6429 inside BFD, and we don't want to force the section alignment to
6430 be the page size. */
6435 {
6447 {
6457 /* We'll need the symbol table in a second. */
6462 /* Limit scan of symbols to object file whose profile is
6463 Microcontroller to not hinder performance in the general case. */
6465 {
6475 }
6477 /* Walk over each section attached to the input bfd. */
6481 {
6484 /* If there aren't any relocs, then there's nothing more
6485 to do. */
6491 /* If this section is a link-once section that will be
6492 discarded, then don't create any stubs. */
6497 /* Get the relocs. */
6498 internal_relocs
6504 /* Now examine each relocation. */
6508 {
6511 bfd_vma sym_value;
6512 bfd_vma destination;
6523 {
6525 error_ret_free_internal:
6528 /* Fall through. */
6529 error_ret_free_local:
6535 }
6539 hash = elf32_arm_hash_entry
6543 /* Only look for stubs on branch instructions, or
6544 non-relaxed TLSCALL */
6557 : (elf32_arm_local_got_tls_type
6562 /* Now determine the call target, its name, value,
6563 section. */
6571 {
6572 /* A non-relaxed TLS call. The target is the
6573 plt-resident trampoline and nothing to do
6574 with the symbol. */
6581 }
6583 {
6584 /* It's a local symbol. */
6588 {
6589 local_syms
6592 local_syms
6598 }
6607 else
6608 sym_sec =
6612 /* This is an undefined symbol. It can never
6613 be resolved. */
6622 branch_type =
6624 sym_name
6628 }
6629 else
6630 {
6631 /* It's an external symbol. */
6639 {
6646 /* For a destination in a shared library,
6647 use the PLT stub as target address to
6648 decide whether a branch stub is
6649 needed. */
6654 {
6658 destination = (sym_value
6661 }
6666 }
6669 {
6670 /* For a shared library, use the PLT stub as
6671 target address to decide whether a long
6672 branch stub is needed.
6673 For absolute code, they cannot be handled. */
6681 {
6685 destination = (sym_value
6688 }
6689 else
6691 }
6692 else
6693 {
6696 }
6698 branch_type =
6701 }
6703 do
6704 {
6705 bfd_boolean new_stub;
6708 /* Determine what (if any) linker stub is needed. */
6716 /* We've either created a stub for this reloc already,
6717 or we are about to. */
6718 stub_entry =
6729 else
6731 }
6734 /* Look for relocations which might trigger Cortex-A8
6735 erratum. */
6741 {
6747 {
6748 /* Found a candidate. Note we haven't checked the
6749 destination is within 4K here: if we do so (and
6750 don't create an entry in a8_relocs) we can't tell
6751 that a branch should have been relocated when
6752 scanning later. */
6754 {
6760 }
6770 num_a8_relocs++;
6771 }
6772 }
6773 }
6775 /* We're done with the internal relocs, free them. */
6778 }
6781 {
6782 /* Sort relocs which might apply to Cortex-A8 erratum. */
6787 /* Scan for branches which might trigger Cortex-A8 erratum. */
6794 }
6798 {
6801 else
6803 }
6804 }
6817 /* OK, we've added some stubs. Find out the new size of the
6818 stub sections. */
6822 {
6823 /* Ignore non-stub sections. */
6828 }
6830 /* Add new SG veneers after those already in the input import
6831 library. */
6833 stub_type++)
6834 {
6846 }
6848 /* Compute stub section size, considering padding. */
6851 stub_type++)
6852 {
6858 /* Skip if no stub input section or no stub section padding
6859 required. */
6862 /* Stub section padding required but no dedicated section. */
6868 }
6870 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6873 {
6880 stub_sec->size
6882 NULL);
6883 }
6886 /* Ask the linker to do its stuff. */
6889 }
6891 /* Add stubs for Cortex-A8 erratum fixes now. */
6893 {
6895 {
6908 {
6912 }
6931 }
6933 /* Stash the Cortex-A8 erratum fix array for use later in
6934 elf32_arm_write_section(). */
6937 }
6938 else
6939 {
6942 }
6944 }
6946 /* Build all the stubs associated with the current output file. The
6947 stubs are kept in a hash table attached to the main linker hash
6948 table. We also set up the .plt entries for statically linked PIC
6949 functions here. This function is called via arm_elf_finish in the
6950 linker. */
6952 bfd_boolean
6954 {
6967 {
6968 bfd_size_type size;
6970 /* Ignore non-stub sections. */
6974 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
6975 must at least be done for stub section requiring padding and for SG
6976 veneers to ensure that a non secure code branching to a removed SG
6977 veneer causes an error. */
6984 }
6986 /* Add new SG veneers after those already in the input import library. */
6988 {
7000 }
7002 /* Build the stubs as directed by the stub hash table. */
7006 {
7007 /* Place the cortex a8 stubs last. */
7010 }
7013 }
7015 /* Locate the Thumb encoded calling stub for NAME. */
7021 {
7026 /* We need a pointer to the armelf specific hash table. */
7038 hash = elf_link_hash_lookup
7049 }
7051 /* Locate the ARM encoded calling stub for NAME. */
7057 {
7062 /* We need a pointer to the elfarm specific hash table. */
7074 myh = elf_link_hash_lookup
7085 }
7087 /* ARM->Thumb glue (static images):
7089 .arm
7090 __func_from_arm:
7091 ldr r12, __func_addr
7092 bx r12
7093 __func_addr:
7094 .word func @ behave as if you saw a ARM_32 reloc.
7096 (v5t static images)
7097 .arm
7098 __func_from_arm:
7099 ldr pc, __func_addr
7100 __func_addr:
7101 .word func @ behave as if you saw a ARM_32 reloc.
7103 (relocatable images)
7104 .arm
7105 __func_from_arm:
7106 ldr r12, __func_offset
7107 add r12, r12, pc
7108 bx r12
7109 __func_offset:
7110 .word func - . */
7112 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7117 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7121 #define ARM2THUMB_PIC_GLUE_SIZE 16
7126 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7128 .thumb .thumb
7129 .align 2 .align 2
7130 __func_from_thumb: __func_from_thumb:
7131 bx pc push {r6, lr}
7132 nop ldr r6, __func_addr
7133 .arm mov lr, pc
7134 b func bx r6
7135 .arm
7136 ;; back_to_thumb
7137 ldmia r13! {r6, lr}
7138 bx lr
7139 __func_addr:
7140 .word func */
7142 #define THUMB2ARM_GLUE_SIZE 8
7147 #define VFP11_ERRATUM_VENEER_SIZE 8
7148 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7149 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7151 #define ARM_BX_VENEER_SIZE 12
7156 #ifndef ELFARM_NABI_C_INCLUDED
7157 static void
7159 {
7164 {
7165 /* Do not include empty glue sections in the output. */
7167 {
7171 }
7173 }
7184 }
7186 bfd_boolean
7188 {
7196 ARM2THUMB_GLUE_SECTION_NAME);
7200 THUMB2ARM_GLUE_SECTION_NAME);
7204 VFP11_ERRATUM_VENEER_SECTION_NAME);
7208 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7212 ARM_BX_GLUE_SECTION_NAME);
7215 }
7217 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7218 returns the symbol identifying the stub. */
7223 {
7230 bfd_vma val;
7231 bfd_size_type size;
7237 s = bfd_get_linker_section
7249 myh = elf_link_hash_lookup
7253 {
7254 /* We've already seen this guy. */
7257 }
7259 /* The only trick here is using hash_table->arm_glue_size as the value.
7260 Even though the section isn't allocated yet, this is where we will be
7261 putting it. The +1 on the value marks that the stub has not been
7262 output yet - not that it is a Thumb function. */
7281 else
7288 }
7290 /* Allocate space for ARMv4 BX veneers. */
7292 static void
7294 {
7300 bfd_vma val;
7302 /* BX PC does not need a veneer. */
7310 /* Check if this veneer has already been allocated. */
7314 s = bfd_get_linker_section
7319 /* Add symbol for veneer. */
7327 myh = elf_link_hash_lookup
7345 }
7348 /* Add an entry to the code/data map for section SEC. */
7350 static void
7352 {
7357 {
7362 }
7367 {
7372 }
7375 {
7378 }
7379 }
7382 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7383 veneers are handled for now. */
7385 static bfd_vma
7391 {
7397 bfd_vma val;
7405 s = bfd_get_linker_section
7420 myh = elf_link_hash_lookup
7435 /* Link veneer back to calling location. */
7449 /* A symbol for the return from the veneer. */
7453 myh = elf_link_hash_lookup
7470 /* Generate a mapping symbol for the veneer section, and explicitly add an
7471 entry for that symbol to the code/data map for the section. */
7473 {
7475 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7476 ever requires this erratum fix. */
7486 /* The elf32_arm_init_maps function only cares about symbols from input
7487 BFDs. We must make a note of this generated mapping symbol
7488 ourselves so that code byteswapping works properly in
7489 elf32_arm_write_section. */
7491 }
7497 /* The offset of the veneer. */
7499 }
7501 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7502 veneers need to be handled because used only in Cortex-M. */
7504 static bfd_vma
7510 bfd_size_type veneer_size)
7511 {
7517 bfd_vma val;
7525 s = bfd_get_linker_section
7540 myh = elf_link_hash_lookup
7555 /* Link veneer back to calling location. */
7569 /* A symbol for the return from the veneer. */
7573 myh = elf_link_hash_lookup
7590 /* Generate a mapping symbol for the veneer section, and explicitly add an
7591 entry for that symbol to the code/data map for the section. */
7593 {
7595 /* Creates a THUMB symbol since there is no other choice. */
7605 /* The elf32_arm_init_maps function only cares about symbols from input
7606 BFDs. We must make a note of this generated mapping symbol
7607 ourselves so that code byteswapping works properly in
7608 elf32_arm_write_section. */
7610 }
7616 /* The offset of the veneer. */
7618 }
7620 #define ARM_GLUE_SECTION_FLAGS \
7621 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7622 | SEC_READONLY | SEC_LINKER_CREATED)
7624 /* Create a fake section for use by the ARM backend of the linker. */
7626 static bfd_boolean
7628 {
7633 /* Already made. */
7642 /* Set the gc mark to prevent the section from being removed by garbage
7643 collection, despite the fact that no relocs refer to this section. */
7647 }
7649 /* Set size of .plt entries. This function is called from the
7650 linker scripts in ld/emultempl/{armelf}.em. */
7652 void
7654 {
7656 }
7658 /* Add the glue sections to ABFD. This function is called from the
7659 linker scripts in ld/emultempl/{armelf}.em. */
7661 bfd_boolean
7664 {
7666 bfd_boolean dostm32l4xx = globals
7668 bfd_boolean addglue;
7670 /* If we are only performing a partial
7671 link do not bother adding the glue. */
7683 return addglue
7685 }
7687 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7688 ensures they are not marked for deletion by
7689 strip_excluded_output_sections () when veneers are going to be created
7690 later. Not doing so would trigger assert on empty section size in
7691 lang_size_sections_1 (). */
7693 void
7695 {
7698 /* If we are only performing a partial
7699 link do not bother adding the glue. */
7704 {
7715 }
7716 }
7718 /* Select a BFD to be used to hold the sections used by the glue code.
7719 This function is called from the linker scripts in ld/emultempl/
7720 {armelf/pe}.em. */
7722 bfd_boolean
7724 {
7727 /* If we are only performing a partial link
7728 do not bother getting a bfd to hold the glue. */
7732 /* Make sure we don't attach the glue sections to a dynamic object. */
7741 /* Save the bfd for later use. */
7745 }
7747 static void
7749 {
7753 Tag_CPU_arch);
7756 {
7759 }
7760 else
7761 {
7764 }
7765 }
7767 bfd_boolean
7770 {
7779 /* If we are only performing a partial link do not bother
7780 to construct any glue. */
7784 /* Here we have a bfd that is to be included on the link. We have a
7785 hook to do reloc rummaging, before section sizes are nailed down. */
7792 {
7794 abfd);
7796 }
7798 /* PR 5398: If we have not decided to include any loadable sections in
7799 the output then we will not have a glue owner bfd. This is OK, it
7800 just means that there is nothing else for us to do here. */
7804 /* Rummage around all the relocs and map the glue vectors. */
7811 {
7820 /* Load the relocs. */
7821 internal_relocs
7829 {
7838 /* These are the only relocation types we care about. */
7843 /* Get the section contents if we haven't done so already. */
7845 {
7846 /* Get cached copy if it exists. */
7849 else
7850 {
7851 /* Go get them off disk. */
7854 }
7855 }
7858 {
7864 }
7866 /* If the relocation is not against a symbol it cannot concern us. */
7869 /* We don't care about local symbols. */
7873 /* This is an external symbol. */
7878 /* If the relocation is against a static symbol it must be within
7879 the current section and so cannot be a cross ARM/Thumb relocation. */
7883 /* If the call will go through a PLT entry then we do not need
7884 glue. */
7889 {
7891 /* This one is a call from arm code. We need to look up
7892 the target of the call. If it is a thumb target, we
7893 insert glue. */
7901 }
7902 }
7913 }
7917 error_return:
7926 }
7927 #endif
7930 /* Initialise maps of ARM/Thumb/data for input BFDs. */
7932 void
7934 {
7939 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7949 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7950 should contain the number of local symbols, which should come before any
7951 global symbols. Mapping symbols are always local. */
7953 NULL);
7955 /* No internal symbols read? Skip this BFD. */
7960 {
7967 {
7972 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
7974 }
7975 }
7976 }
7979 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7980 say what they wanted. */
7982 void
7984 {
7992 {
7993 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7998 else
8000 }
8001 }
8004 void
8006 {
8012 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8014 {
8016 {
8023 /* Give a warning, but do as the user requests anyway. */
8026 }
8027 }
8029 /* For earlier architectures, we might need the workaround, but do not
8030 enable it by default. If users is running with broken hardware, they
8031 must enable the erratum fix explicitly. */
8033 }
8035 void
8037 {
8044 /* We assume only Cortex-M4 may require the fix. */
8047 {
8049 /* Give a warning, but do as the user requests anyway. */
8050 _bfd_error_handler
8053 }
8054 }
8056 enum bfd_arm_vfp11_pipe
8057 {
8058 VFP11_FMAC,
8059 VFP11_LS,
8060 VFP11_DS,
8061 VFP11_BAD
8062 };
8064 /* Return a VFP register number. This is encoded as RX:X for single-precision
8065 registers, or X:RX for double-precision registers, where RX is the group of
8066 four bits in the instruction encoding and X is the single extension bit.
8067 RX and X fields are specified using their lowest (starting) bit. The return
8068 value is:
8070 0...31: single-precision registers s0...s31
8071 32...63: double-precision registers d0...d31.
8073 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8074 encounter VFP3 instructions, so we allow the full range for DP registers. */
8076 static unsigned int
8079 {
8082 else
8084 }
8086 /* Set bits in *WMASK according to a register number REG as encoded by
8087 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8089 static void
8091 {
8096 }
8098 /* Return TRUE if WMASK overwrites anything in REGS. */
8100 static bfd_boolean
8102 {
8106 {
8119 }
8122 }
8124 /* In this function, we're interested in two things: finding input registers
8125 for VFP data-processing instructions, and finding the set of registers which
8126 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8127 hold the written set, so FLDM etc. are easy to deal with (we're only
8128 interested in 32 SP registers or 16 dp registers, due to the VFP version
8129 implemented by the chip in question). DP registers are marked by setting
8130 both SP registers in the write mask). */
8132 static enum bfd_arm_vfp11_pipe
8135 {
8140 {
8150 {
8172 vfp_binop:
8180 {
8185 {
8199 /* These instructions will not bounce due to underflow. */
8205 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8206 registers to cause the erratum in previous instructions. */
8212 {
8217 /* Only FCVTSD can underflow. */
8224 }
8229 }
8230 }
8235 }
8236 }
8237 /* Two-register transfer. */
8239 {
8243 {
8246 else
8247 {
8250 }
8251 }
8254 }
8256 {
8261 {
8268 {
8276 }
8286 }
8289 }
8290 /* Single-register transfer. Note L==0. */
8292 {
8297 {
8300 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8301 destination register. I don't know if this is exactly right,
8302 but it is the conservative choice. */
8308 }
8311 }
8314 }
8320 /* Look for potentially-troublesome code sequences which might trigger the
8321 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8322 (available from ARM) for details of the erratum. A short version is
8323 described in ld.texinfo. */
8325 bfd_boolean
8327 {
8338 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8339 The states transition as follows:
8341 0 -> 1 (vector) or 0 -> 2 (scalar)
8342 A VFP FMAC-pipeline instruction has been seen. Fill
8343 regs[0]..regs[numregs-1] with its input operands. Remember this
8344 instruction in 'first_fmac'.
8346 1 -> 2
8347 Any instruction, except for a VFP instruction which overwrites
8348 regs[*].
8350 1 -> 3 [ -> 0 ] or
8351 2 -> 3 [ -> 0 ]
8352 A VFP instruction has been seen which overwrites any of regs[*].
8353 We must make a veneer! Reset state to 0 before examining next
8354 instruction.
8356 2 -> 0
8357 If we fail to match anything in state 2, reset to state 0 and reset
8358 the instruction pointer to the instruction after 'first_fmac'.
8360 If the VFP11 vector mode is in use, there must be at least two unrelated
8361 instructions between anti-dependent VFP11 instructions to properly avoid
8362 triggering the erratum, hence the use of the extra state 1. */
8364 /* If we are only performing a partial link do not bother
8365 to construct any glue. */
8369 /* Skip if this bfd does not correspond to an ELF image. */
8373 /* We should have chosen a fix type by the time we get here. */
8379 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8384 {
8388 /* If we don't have executable progbits, we're not interested in this
8389 section. Also skip if section is to be excluded. */
8409 elf32_arm_compare_mapping);
8412 {
8418 /* FIXME: Only ARM mode is supported at present. We may need to
8419 support Thumb-2 mode also at some point. */
8424 {
8439 {
8443 /* I'm assuming the VFP11 erratum can trigger with denorm
8444 operands on either the FMAC or the DS pipeline. This might
8445 lead to slightly overenthusiastic veneer insertion. */
8447 {
8451 }
8455 {
8458 other_regs,
8462 numregs))
8464 else
8466 }
8470 {
8473 other_regs,
8477 numregs))
8479 else
8480 {
8483 }
8484 }
8489 }
8492 {
8501 {
8508 }
8511 first_fmac);
8519 }
8522 }
8523 }
8529 }
8533 error_return:
8539 }
8541 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8542 after sections have been laid out, using specially-named symbols. */
8544 void
8547 {
8555 /* Skip if this bfd does not correspond to an ELF image. */
8567 {
8572 {
8574 bfd_vma vma;
8577 {
8580 /* Find veneer symbol. */
8584 myh = elf_link_hash_lookup
8600 /* Find return location. */
8604 myh = elf_link_hash_lookup
8620 }
8621 }
8622 }
8625 }
8627 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8628 return locations after sections have been laid out, using
8629 specially-named symbols. */
8631 void
8634 {
8642 /* Skip if this bfd does not correspond to an ELF image. */
8654 {
8659 {
8661 bfd_vma vma;
8664 {
8666 /* Find veneer symbol. */
8670 myh = elf_link_hash_lookup
8685 /* Find return location. */
8689 myh = elf_link_hash_lookup
8705 }
8706 }
8707 }
8710 }
8714 {
8715 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8716 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8718 }
8722 {
8723 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8724 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8726 }
8730 {
8731 /* A6.5 Extension register load or store instruction
8732 A7.7.229
8733 We look for SP 32-bit and DP 64-bit registers.
8734 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8735 <list> is consecutive 64-bit registers
8736 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8737 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8738 <list> is consecutive 32-bit registers
8739 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8740 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8741 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8742 return
8747 /* (IA with !), includes VPOP (when reg number is SP). */
8749 /* (DB with !). */
8751 }
8753 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8754 VLDM opcode and:
8755 - computes the number and the mode of memory accesses
8756 - decides if the replacement should be done:
8757 . replaces only if > 8-word accesses
8758 . or (testing purposes only) replaces all accesses. */
8760 static bfd_boolean
8762 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8763 {
8766 /* The field encoding the register list is the same for both LDMIA
8767 and LDMDB encodings. */
8773 /* DEFAULT mode accounts for the real bug condition situation,
8774 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8775 return
8778 }
8780 /* Look for potentially-troublesome code sequences which might trigger
8781 the STM STM32L4XX erratum. */
8783 bfd_boolean
8786 {
8794 /* If we are only performing a partial link do not bother
8795 to construct any glue. */
8799 /* Skip if this bfd does not correspond to an ELF image. */
8806 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8811 {
8815 /* If we don't have executable progbits, we're not interested in this
8816 section. Also skip if section is to be excluded. */
8836 elf32_arm_compare_mapping);
8839 {
8846 /* Only Thumb2 mode need be supported with this CM4 specific
8847 code, we should not encounter any arm mode eg span_type
8848 != 'a'. */
8853 {
8860 /* The first 16-bits of all 32-bit thumb2 instructions start
8861 with opcode[15..13]=0b111 and the encoded op1 can be anything
8862 except opcode[12..11]!=0b00.
8863 See 32-bit Thumb instruction encoding. */
8867 /* Compute the predicate that tells if the instruction
8868 is concerned by the IT block
8869 - Creates an error if there is a ldm that is not
8870 last in the IT block thus cannot be replaced
8871 - Otherwise we can create a branch at the end of the
8872 IT block, it will be controlled naturally by IT
8873 with the proper pseudo-predicate
8874 - So the only interesting predicate is the one that
8875 tells that we are not on the last item of an IT
8876 block. */
8881 {
8882 /* Load the rest of the insn (in manual-friendly order). */
8887 /* Veneers are created for (v)ldm depending on
8888 option flags and memory accesses conditions; but
8889 if the instruction is not the last instruction of
8890 an IT block, we cannot create a jump there, so we
8891 bail out. */
8893 && stm32l4xx_need_create_replacing_stub
8895 {
8897 {
8898 _bfd_error_handler
8899 /* xgettext:c-format */
8901 " in non-last IT block instruction:"
8902 " STM32L4XX veneer cannot be generated; "
8903 "use gcc option -mrestrict-it to generate"
8906 }
8907 else
8908 {
8911 bfd_zmalloc
8917 /* We create only thumb branches. */
8919 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8920 record_stm32l4xx_erratum_veneer
8922 i,
8923 is_ldm ?
8924 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8925 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8929 }
8930 }
8931 }
8932 else
8933 {
8934 /* A7.7.37 IT p208
8935 IT blocks are only encoded in T1
8936 Encoding T1: IT{x{y{z}}} <firstcond>
8937 1 0 1 1 - 1 1 1 1 - firstcond - mask
8938 if mask = '0000' then see 'related encodings'
8939 We don't deal with UNPREDICTABLE, just ignore these.
8940 There can be no nested IT blocks so an IT block
8941 is naturally a new one for which it is worth
8942 computing its size. */
8945 /* If we have a new IT block we compute its size. */
8947 {
8948 /* Compute the number of instructions controlled
8949 by the IT block, it will be used to decide
8950 whether we are inside an IT block or not. */
8953 }
8954 }
8957 }
8958 }
8964 }
8968 error_return:
8974 }
8976 /* Set target relocation values needed during linking. */
8978 void
8982 {
8998 else
8999 {
9002 }
9009 else
9021 }
9023 /* Replace the target offset of a Thumb bl or b.w instruction. */
9025 static void
9027 {
9028 bfd_vma upper;
9029 bfd_vma lower;
9046 }
9048 /* Thumb code calling an ARM function. */
9050 static int
9058 bfd_vma offset,
9059 bfd_signed_vma addend,
9060 bfd_vma val,
9062 {
9064 bfd_vma my_offset;
9080 THUMB2ARM_GLUE_SECTION_NAME);
9087 {
9091 {
9092 _bfd_error_handler
9098 }
9109 ret_offset =
9110 /* Address of destination of the stub. */
9113 /* Offset from the start of the current section
9114 to the start of the stubs. */
9116 /* Offset of the start of this stub from the start of the stubs. */
9117 + my_offset
9118 /* Address of the start of the current section. */
9120 /* The branch instruction is 4 bytes into the stub. */
9122 /* ARM branches work from the pc of the instruction + 8. */
9128 }
9132 /* Now go back and fix up the original BL insn to point to here. */
9133 ret_offset =
9134 /* Address of where the stub is located. */
9136 /* Address of where the BL is located. */
9139 /* Addend in the relocation. */
9140 - addend
9141 /* Biassing for PC-relative addressing. */
9147 }
9149 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9157 bfd_vma val,
9160 {
9161 bfd_vma my_offset;
9177 {
9181 {
9182 _bfd_error_handler
9186 }
9194 {
9195 /* For relocatable objects we can't use absolute addresses,
9196 so construct the address from a relative offset. */
9197 /* TODO: If the offset is small it's probably worth
9198 constructing the address with adds. */
9205 /* Adjust the offset by 4 for the position of the add,
9206 and 8 for the pipeline offset. */
9213 }
9215 {
9219 /* It's a thumb address. Add the low order bit. */
9222 }
9223 else
9224 {
9231 /* It's a thumb address. Add the low order bit. */
9236 }
9237 }
9242 }
9244 /* Arm code calling a Thumb function. */
9246 static int
9254 bfd_vma offset,
9255 bfd_signed_vma addend,
9256 bfd_vma val,
9258 {
9260 bfd_vma my_offset;
9271 ARM2THUMB_GLUE_SECTION_NAME);
9285 /* Somehow these are both 4 too far, so subtract 8. */
9287 + my_offset
9299 }
9301 /* Populate Arm stub for an exported Thumb function. */
9303 static bfd_boolean
9305 {
9312 bfd_vma val;
9316 /* Allocate stubs for exported Thumb functions on v4t. */
9325 ARM2THUMB_GLUE_SECTION_NAME);
9343 }
9345 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9347 static bfd_vma
9349 {
9351 bfd_vma glue_addr;
9360 ARM_BX_GLUE_SECTION_NAME);
9370 {
9376 }
9379 }
9381 /* Generate Arm stubs for exported Thumb symbols. */
9382 static void
9385 {
9389 /* Ignore this if we are not called by the ELF backend linker. */
9396 /* If blx is available then exported Thumb symbols are OK and there is
9397 nothing to do. */
9402 link_info);
9403 }
9405 /* Reserve space for COUNT dynamic relocations in relocation selection
9406 SRELOC. */
9408 static void
9410 bfd_size_type count)
9411 {
9419 }
9421 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9422 dynamic, the relocations should go in SRELOC, otherwise they should
9423 go in the special .rel.iplt section. */
9425 static void
9427 bfd_size_type count)
9428 {
9434 else
9435 {
9438 }
9439 }
9441 /* Add relocation REL to the end of relocation section SRELOC. */
9443 static void
9446 {
9461 }
9463 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9464 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9465 to .plt. */
9467 static void
9469 bfd_boolean is_iplt_entry,
9472 {
9480 {
9484 /* NaCl uses a special first entry in .iplt too. */
9488 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9490 }
9491 else
9492 {
9497 {
9498 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9499 /* For lazy binding, relocations will be put into .rel.plt, in
9500 .rel.got otherwise. */
9501 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9504 else
9506 }
9507 else
9508 {
9509 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9511 }
9513 /* If this is the first .plt entry, make room for the special
9514 first entry. */
9519 }
9521 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9528 {
9529 /* We also need to make an entry in the .got.plt section, which
9530 will be placed in the .got section by the linker script. */
9533 else
9536 /* Function descriptor takes 64 bits in GOT. */
9538 else
9540 }
9541 }
9543 static bfd_vma
9545 {
9547 }
9549 static bfd_vma
9551 {
9553 }
9555 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9556 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9557 Otherwise, DYNINDX is the index of the symbol in the dynamic
9558 symbol table and SYM_VALUE is undefined.
9560 ROOT_PLT points to the offset of the PLT entry from the start of its
9561 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9562 bookkeeping information.
9564 Returns FALSE if there was a problem. */
9566 static bfd_boolean
9571 {
9577 bfd_vma plt_index;
9578 Elf_Internal_Rela rel;
9579 bfd_vma plt_header_size;
9580 bfd_vma got_header_size;
9584 /* Pick the appropriate sections and sizes. */
9586 {
9591 /* There are no reserved entries in .igot.plt, and no special
9592 first entry in .iplt. */
9595 }
9596 else
9597 {
9604 }
9607 /* Fill in the entry in the procedure linkage table. */
9609 {
9618 /* Fill in the entry in the .rel.plt section. */
9624 /* Get the index in the procedure linkage table which
9625 corresponds to this symbol. This is the index of this symbol
9626 in all the symbols for which we are making plt entries. The
9627 first entry in the procedure linkage table is reserved. */
9630 }
9631 else
9632 {
9639 /* Get the offset into the .(i)got.plt table of the entry that
9640 corresponds to this function. */
9643 /* Get the index in the procedure linkage table which
9644 corresponds to this symbol. This is the index of this symbol
9645 in all the symbols for which we are making plt entries.
9646 After the reserved .got.plt entries, all symbols appear in
9647 the same order as in .plt. */
9649 /* Function descriptor takes 8 bytes. */
9651 else
9654 /* Calculate the address of the GOT entry. */
9659 /* ...and the address of the PLT entry. */
9666 {
9668 bfd_vma val;
9671 {
9679 else
9681 }
9682 }
9684 {
9686 bfd_vma val;
9689 {
9699 else
9701 }
9706 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9707 referencing the GOT for this PLT entry. */
9714 /* Create the R_ARM_ABS32 relocation referencing the
9715 beginning of the PLT for this GOT entry. */
9720 }
9722 {
9723 /* Calculate the displacement between the PLT slot and the
9724 common tail that's part of the special initial PLT slot. */
9725 int32_t tail_displacement
9735 /* Calculate the displacement between the PLT slot and the entry
9736 in the GOT. The offset accounts for the value produced by
9737 adding to pc in the penultimate instruction of the PLT stub. */
9738 got_displacement = (got_address
9741 /* NaCl does not support interworking at all. */
9759 }
9761 {
9763 ? elf32_arm_fdpic_thumb_plt_entry
9766 /* Fill-up Thumb stub if needed. */
9768 {
9773 }
9774 /* As we are using 32 bit instructions even for the Thumb
9775 version, we have to use 'put_arm_insn' instead of
9776 'put_thumb_insn'. */
9784 {
9785 /* funcdesc_value_reloc_offset. */
9793 }
9794 }
9796 {
9797 /* PR ld/16017: Generate thumb only PLT entries. */
9799 {
9800 /* FIXME: We ought to be able to generate thumb-1 PLT
9801 instructions... */
9803 output_bfd);
9805 }
9807 /* Calculate the displacement between the PLT slot and the entry in
9808 the GOT. The 12-byte offset accounts for the value produced by
9809 adding to pc in the 3rd instruction of the PLT stub. */
9812 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9813 instead of 'put_thumb_insn'. */
9834 }
9835 else
9836 {
9837 /* Calculate the displacement between the PLT slot and the
9838 entry in the GOT. The eight-byte offset accounts for the
9839 value produced by adding to pc in the first instruction
9840 of the PLT stub. */
9844 {
9849 }
9852 {
9867 #ifdef FOUR_WORD_PLT
9869 #endif
9870 }
9871 else
9872 {
9889 }
9890 }
9892 /* Fill in the entry in the .rel(a).(i)plt section. */
9896 {
9897 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9898 The dynamic linker or static executable then calls SYM_VALUE
9899 to determine the correct run-time value of the .igot.plt entry. */
9902 }
9903 else
9904 {
9905 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9906 used by PLT entry. */
9908 {
9911 }
9912 else
9913 {
9917 }
9918 }
9920 /* Fill in the entry in the global offset table. */
9925 {
9926 /* Setup initial funcdesc value. */
9927 /* FIXME: we don't support lazy binding because there is a
9928 race condition between both words getting written and
9929 some other thread attempting to read them. The ARM
9930 architecture does not have an atomic 64 bit load/store
9931 instruction that could be used to prevent it; it is
9932 recommended that threaded FDPIC applications run with the
9933 LD_BIND_NOW environment variable set. */
9938 }
9939 }
9943 else
9944 {
9946 {
9947 /* For FDPIC we put PLT relocationss into .rel.got when not
9948 lazy binding otherwise we put them in .rel.plt. For now,
9949 we don't support lazy binding so put it in .rel.got. */
9952 else
9954 }
9955 else
9956 {
9959 }
9960 }
9963 }
9965 /* Some relocations map to different relocations depending on the
9966 target. Return the real relocation. */
9968 static int
9971 {
9973 {
9977 else
9985 }
9986 }
9988 /* Return the base VMA address which should be subtracted from real addresses
9989 when resolving @dtpoff relocation.
9990 This is PT_TLS segment p_vaddr. */
9992 static bfd_vma
9994 {
9995 /* If tls_sec is NULL, we should have signalled an error already. */
9999 }
10001 /* Return the relocation value for @tpoff relocation
10002 if STT_TLS virtual address is ADDRESS. */
10004 static bfd_vma
10006 {
10008 bfd_vma base;
10010 /* If tls_sec is NULL, we should have signalled an error already. */
10015 }
10017 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10018 VALUE is the relocation value. */
10020 static bfd_reloc_status_type
10022 {
10029 }
10031 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10032 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10033 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10035 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10036 is to then call final_link_relocate. Return other values in the
10037 case of error.
10039 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10040 the pre-relaxed code. It would be nice if the relocs were updated
10041 to match the optimization. */
10043 static bfd_reloc_status_type
10047 {
10051 {
10058 else
10059 {
10063 else
10065 }
10070 /* Thumb insn. */
10073 {
10075 /* nop */
10077 }
10079 {
10081 /* nop */
10083 else
10084 /* ldr rx,[ry] */
10086 }
10088 {
10090 /* nop */
10092 else
10093 /* mov r0, rx */
10096 }
10097 else
10098 {
10100 /* It's a 32 bit instruction, fetch the rest of it for
10101 error generation. */
10104 _bfd_error_handler
10105 /* xgettext:c-format */
10111 }
10115 /* arm insn. */
10118 {
10120 /* mov rx, ry */
10123 }
10125 {
10127 /* nop */
10129 else
10130 /* ldr rx,[ry] */
10133 }
10135 {
10137 /* nop */
10139 else
10140 /* mov r0, rx */
10143 }
10144 else
10145 {
10146 _bfd_error_handler
10147 /* xgettext:c-format */
10153 }
10157 /* GD->IE relaxation, turn the instruction into 'nop' or
10158 'ldr r0, [pc,r0]' */
10164 /* GD->IE relaxation. */
10166 /* add r0,pc; ldr r0, [r0] */
10169 /* nop.w */
10171 else
10172 /* nop; nop */
10178 }
10180 }
10182 /* For a given value of n, calculate the value of G_n as required to
10183 deal with group relocations. We return it in the form of an
10184 encoded constant-and-rotation, together with the final residual. If n is
10185 specified as less than zero, then final_residual is filled with the
10186 input value and no further action is performed. */
10188 static bfd_vma
10190 {
10192 bfd_vma g_n;
10197 {
10200 /* Calculate which part of the value to mask. */
10203 else
10204 {
10207 /* Determine the most significant bit in the residual and
10208 align the resulting value to a 2-bit boundary. */
10213 /* The desired shift is now (msb - 6), or zero, whichever
10214 is the greater. */
10218 }
10220 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10225 /* Calculate the residual for the next time around. */
10227 }
10232 }
10234 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10235 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10237 static int
10239 {
10249 }
10251 /* Perform a relocation as part of a final link. */
10253 static bfd_reloc_status_type
10260 bfd_vma value,
10269 {
10279 bfd_vma addend;
10280 bfd_signed_vma signed_addend;
10282 bfd_vma dynreloc_value;
10287 bfd_vma plt_offset;
10288 bfd_vma gotplt_offset;
10289 bfd_boolean has_iplt_entry;
10290 bfd_boolean resolved_to_zero;
10299 /* Some relocation types map to different relocations depending on the
10300 target. We pick the right one here. */
10303 /* It is possible to have linker relaxations on some TLS access
10304 models. Update our information here. */
10317 else
10323 {
10327 {
10331 }
10332 else
10334 }
10335 else
10338 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10339 are resolving a function call relocation. */
10346 /* Record the symbol information that should be used in dynamic
10347 relocations. */
10353 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10354 VALUE appropriately for relocations that we resolve at link time. */
10359 {
10364 {
10368 /* Populate .iplt entries here, because not all of them will
10369 be seen by finish_dynamic_symbol. The lower bit is set if
10370 we have already populated the entry. */
10372 plt_offset--;
10373 else
10374 {
10378 else
10380 }
10382 /* Static relocations always resolve to the .iplt entry. */
10389 /* If there are non-call relocations that resolve to the .iplt
10390 entry, then all dynamic ones must too. */
10392 {
10395 }
10396 }
10397 else
10398 /* We populate the .plt entry in finish_dynamic_symbol. */
10400 }
10401 else
10402 {
10406 }
10412 {
10414 /* We don't need to find a value for this symbol. It's just a
10415 marker. */
10422 /* Fall through. */
10434 /* Handle relocations which should use the PLT entry. ABS32/REL32
10435 will use the symbol's value, which may point to a PLT entry, but we
10436 don't need to handle that here. If we created a PLT entry, all
10437 branches in this object should go to it, except if the PLT is too
10438 far away, in which case a long branch stub should be inserted. */
10445 {
10446 /* If we've created a .plt section, and assigned a PLT entry
10447 to this function, it must either be a STT_GNU_IFUNC reference
10448 or not be known to bind locally. In other cases, we should
10449 have cleared the PLT entry by now. */
10459 }
10461 /* When generating a shared object or relocatable executable, these
10462 relocations are copied into the output file to be resolved at
10463 run time. */
10484 {
10485 Elf_Internal_Rela outrel;
10491 {
10497 _bfd_error_handler
10502 }
10507 {
10513 }
10538 else
10539 {
10542 /* This symbol is local, or marked to become local. */
10546 {
10549 /* On Symbian OS, the data segment and text segement
10550 can be relocated independently. Therefore, we
10551 must indicate the segment to which this
10552 relocation is relative. The BPABI allows us to
10553 use any symbol in the right segment; we just use
10554 the section symbol as it is convenient. (We
10555 cannot use the symbol given by "h" directly as it
10556 will not appear in the dynamic symbol table.)
10558 Note that the dynamic linker ignores the section
10559 symbol value, so we don't subtract osec->vma
10560 from the emitted reloc addend. */
10563 else
10567 {
10573 else
10576 }
10578 }
10579 else
10580 /* On SVR4-ish systems, the dynamic loader cannot
10581 relocate the text and data segments independently,
10582 so the symbol does not matter. */
10585 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10586 to the .iplt entry. Instead, every non-call reference
10587 must use an R_ARM_IRELATIVE relocation to obtain the
10588 correct run-time address. */
10592 else
10596 else
10598 }
10602 else
10605 /* If this reloc is against an external symbol, we do not want to
10606 fiddle with the addend. Otherwise, we need to include the symbol
10607 value so that it becomes an addend for the dynamic reloc. */
10614 }
10616 {
10625 {
10629 {
10630 /* Check for Arm calling Arm function. */
10631 /* FIXME: Should we translate the instruction into a BL
10632 instruction instead ? */
10634 _bfd_error_handler
10639 }
10641 {
10642 /* Check for Arm calling Thumb function. */
10644 {
10649 error_message))
10651 else
10653 }
10654 }
10656 /* Check if a stub has to be inserted because the
10657 destination is too far or we are changing mode. */
10661 {
10672 {
10673 /* The target is out of reach, so redirect the
10674 branch to the local stub for this function. */
10678 stub_type);
10679 {
10687 }
10688 }
10689 else
10690 {
10691 /* If the call goes through a PLT entry, make sure to
10692 check distance to the right destination address. */
10694 {
10699 /* The PLT entry is in ARM mode, regardless of the
10700 target function. */
10702 }
10703 }
10704 }
10706 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10707 where:
10708 S is the address of the symbol in the relocation.
10709 P is address of the instruction being relocated.
10710 A is the addend (extracted from the instruction) in bytes.
10712 S is held in 'value'.
10713 P is the base address of the section containing the
10714 instruction plus the offset of the reloc into that
10715 section, ie:
10716 (input_section->output_section->vma +
10717 input_section->output_offset +
10718 rel->r_offset).
10719 A is the addend, converted into bytes, ie:
10720 (signed_addend * 4)
10722 Note: None of these operations have knowledge of the pipeline
10723 size of the processor, thus it is up to the assembler to
10724 encode this information into the addend. */
10730 else
10731 /* RELA addends do not have to be adjusted by howto->size. */
10737 /* A branch to an undefined weak symbol is turned into a jump to
10738 the next instruction unless a PLT entry will be created.
10739 Do the same for local undefined symbols (but not for STN_UNDEF).
10740 The jump to the next instruction is optimized as a NOP depending
10741 on the architecture. */
10745 {
10750 else
10752 }
10753 else
10754 {
10755 /* Perform a signed range check. */
10766 {
10767 /* Set the H bit in the BLX instruction. */
10769 {
10772 else
10774 }
10776 /* Select the correct instruction (BL or BLX). */
10777 /* Only if we are not handling a BL to a stub. In this
10778 case, mode switching is performed by the stub. */
10782 {
10785 }
10786 }
10787 }
10788 }
10820 {
10821 /* Check for overflow. */
10824 }
10830 }
10836 /* PR 16202: Refectch the addend using the correct size. */
10841 /* There is no way to tell whether the user intended to use a signed or
10842 unsigned addend. When checking for overflow we accept either,
10843 as specified by the AAELF. */
10851 /* PR 16202: Refectch the addend using the correct size. */
10856 /* See comment for R_ARM_ABS8. */
10864 /* Support ldr and str instructions for the thumb. */
10866 {
10867 /* Need to refetch addend. */
10869 /* ??? Need to determine shift amount from operand size. */
10871 }
10874 /* ??? Isn't value unsigned? */
10878 /* ??? Value needs to be properly shifted into place first. */
10884 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10885 {
10886 bfd_vma insn;
10887 bfd_signed_vma relocation;
10893 {
10898 }
10905 /* PR 21523: Use an absolute value. The user of this reloc will
10906 have already selected an ADD or SUB insn appropriately. */
10912 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10926 }
10929 /* PR 10073: This reloc is not generated by the GNU toolchain,
10930 but it is supported for compatibility with third party libraries
10931 generated by other compilers, specifically the ARM/IAR. */
10932 {
10933 bfd_vma insn;
10934 bfd_signed_vma relocation;
10948 /* We do not check for overflow of this reloc. Although strictly
10949 speaking this is incorrect, it appears to be necessary in order
10950 to work with IAR generated relocs. Since GCC and GAS do not
10951 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10952 a problem for them. */
10960 }
10963 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10964 {
10965 bfd_vma insn;
10966 bfd_signed_vma relocation;
10972 {
10976 }
10996 }
11001 /* Thumb BL (branch long instruction). */
11002 {
11003 bfd_vma relocation;
11004 bfd_vma reloc_sign;
11008 bfd_signed_vma reloc_signed_max;
11009 bfd_signed_vma reloc_signed_min;
11010 bfd_vma check;
11011 bfd_signed_vma signed_check;
11016 /* A branch to an undefined weak symbol is turned into a jump to
11017 the next instruction unless a PLT entry will be created.
11018 The jump to the next instruction is optimized as a NOP.W for
11019 Thumb-2 enabled architectures. */
11022 {
11024 {
11027 }
11028 else
11029 {
11032 }
11034 }
11036 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11037 with Thumb-1) involving the J1 and J2 bits. */
11039 {
11049 /* Sign extend. */
11053 }
11056 {
11057 /* Check for Thumb to Thumb call. */
11058 /* FIXME: Should we translate the instruction into a BL
11059 instruction instead ? */
11061 _bfd_error_handler
11066 }
11067 else
11068 {
11069 /* If it is not a call to Thumb, assume call to Arm.
11070 If it is a call relative to a section name, then it is not a
11071 function call at all, but rather a long jump. Calls through
11072 the PLT do not require stubs. */
11074 {
11076 {
11077 /* Convert BL to BLX. */
11079 }
11082 {
11086 error_message))
11088 else
11090 }
11091 }
11095 {
11096 /* Make sure this is a BL. */
11098 }
11099 }
11103 {
11104 /* Check if a stub has to be inserted because the destination
11105 is too far. */
11117 {
11118 /* The target is out of reach or we are changing modes, so
11119 redirect the branch to the local stub for this
11120 function. */
11124 stub_type);
11126 {
11133 }
11135 /* If this call becomes a call to Arm, force BLX. */
11137 {
11142 }
11143 }
11144 }
11146 /* Handle calls via the PLT. */
11148 {
11156 {
11157 /* If the Thumb BLX instruction is available, convert
11158 the BL to a BLX instruction to call the ARM-mode
11159 PLT entry. */
11162 }
11163 else
11164 {
11166 /* Target the Thumb stub before the ARM PLT entry. */
11169 }
11171 }
11181 /* If this is a signed value, the rightshift just dropped
11182 leading 1 bits (assuming twos complement). */
11185 else
11188 /* Calculate the permissable maximum and minimum values for
11189 this relocation according to whether we're relocating for
11190 Thumb-2 or not. */
11197 /* Assumes two's complement. */
11202 /* For a BLX instruction, make sure that the relocation is rounded up
11203 to a word boundary. This follows the semantics of the instruction
11204 which specifies that bit 1 of the target address will come from bit
11205 1 of the base address. */
11208 /* Put RELOCATION back into the insn. Assumes two's complement.
11209 We use the Thumb-2 encoding, which is safe even if dealing with
11210 a Thumb-1 instruction by virtue of our overflow check above. */
11220 /* Put the relocated value back in the object file: */
11225 }
11229 /* Thumb32 conditional branch instruction. */
11230 {
11231 bfd_vma relocation;
11237 bfd_signed_vma signed_check;
11242 /* Need to refetch the addend, reconstruct the top three bits,
11243 and squish the two 11 bit pieces together. */
11245 {
11259 }
11261 /* Handle calls via the PLT. */
11263 {
11267 /* Target the Thumb stub before the ARM PLT entry. */
11270 }
11279 {
11283 stub_type);
11285 {
11289 }
11290 }
11301 /* Put RELOCATION back into the insn. */
11302 {
11311 }
11313 /* Put the relocated value back in the object file: */
11318 }
11323 /* Thumb B (branch) instruction). */
11324 {
11325 bfd_signed_vma relocation;
11328 bfd_signed_vma signed_check;
11330 /* CZB cannot jump backward. */
11335 {
11336 /* Need to refetch addend. */
11339 {
11343 }
11344 else
11346 /* The value in the insn has been right shifted. We need to
11347 undo this, so that we can perform the address calculation
11348 in terms of bytes. */
11350 }
11362 else
11368 /* Assumes two's complement. */
11373 }
11378 {
11379 bfd_vma insn;
11380 bfd_vma relocation;
11384 {
11385 /* Extract the addend. */
11388 }
11398 }
11406 /* Relocation is relative to the start of the
11407 global offset table. */
11413 /* If we are addressing a Thumb function, we need to adjust the
11414 address by one, so that attempts to call the function pointer will
11415 correctly interpret it as Thumb code. */
11419 /* Note that sgot->output_offset is not involved in this
11420 calculation. We always want the start of .got. If we
11421 define _GLOBAL_OFFSET_TABLE in a different way, as is
11422 permitted by the ABI, we might have to change this
11423 calculation. */
11430 /* Use global offset table as symbol value. */
11444 /* Relocation is to the entry for this symbol in the
11445 global offset table. */
11452 {
11453 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11454 symbol, and the relocation resolves directly to the runtime
11455 target rather than to the .iplt entry. This means that any
11456 .got entry would be the same value as the .igot.plt entry,
11457 so there's no point creating both. */
11460 }
11462 {
11463 bfd_vma off;
11468 {
11469 /* We have already processsed one GOT relocation against
11470 this symbol. */
11475 }
11476 else
11477 {
11478 Elf_Internal_Rela outrel;
11483 {
11484 /* If the symbol doesn't resolve locally in a static
11485 object, we have an undefined reference. If the
11486 symbol doesn't resolve locally in a dynamic object,
11487 it should be resolved by the dynamic linker. */
11489 {
11492 }
11493 else
11496 }
11497 else
11498 {
11505 else
11506 {
11510 }
11512 }
11514 /* The GOT entry is initialized to zero by default.
11515 See if we should install a different value. */
11518 {
11522 }
11531 {
11536 }
11539 }
11541 }
11542 else
11543 {
11544 bfd_vma off;
11551 /* The offset must always be a multiple of 4. We use the
11552 least significant bit to record whether we have already
11553 generated the necessary reloc. */
11556 else
11557 {
11558 Elf_Internal_Rela outrel;
11565 else
11566 {
11570 }
11572 /* The GOT entry is initialized to zero by default.
11573 See if we should install a different value. */
11584 {
11590 }
11593 }
11596 }
11613 {
11614 bfd_vma off;
11623 else
11624 {
11625 /* If we don't know the module number, create a relocation
11626 for it. */
11628 {
11629 Elf_Internal_Rela outrel;
11644 }
11645 else
11649 }
11652 {
11658 }
11659 else
11660 {
11668 }
11669 }
11680 {
11688 {
11689 bfd_boolean dyn;
11693 h)
11696 {
11699 }
11703 }
11704 else
11705 {
11710 }
11712 /* Linker relaxations happens from one of the
11713 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11721 else
11722 {
11724 Elf_Internal_Rela outrel;
11727 /* The GOT entries have not been initialized yet. Do it
11728 now, and emit any relocations. If both an IE GOT and a
11729 GD GOT are necessary, we emit the GD first. */
11736 {
11739 }
11742 {
11745 /* We should have relaxed, unless this is an undefined
11746 weak symbol. */
11755 + offplt
11767 /* For globals, the first word in the relocation gets
11768 the relocation index and the top bit set, or zero,
11769 if we're binding now. For locals, it gets the
11770 symbol's offset in the tls section. */
11778 /* Second word in the relocation is always zero. */
11782 }
11784 {
11786 {
11802 else
11803 {
11806 R_ARM_TLS_DTPOFF32);
11815 }
11816 }
11817 else
11818 {
11819 /* If we are not emitting relocations for a
11820 general dynamic reference, then we must be in a
11821 static link or an executable link with the
11822 symbol binding locally. Mark it as belonging
11823 to module 1, the executable. */
11828 }
11831 }
11834 {
11836 {
11839 else
11851 }
11852 else
11856 }
11860 else
11862 }
11871 {
11872 bfd_signed_vma offset;
11873 /* TLS stubs are arm mode. The original symbol is a
11874 data object, so branch_type is bogus. */
11876 enum elf32_arm_stub_type stub_type
11884 {
11886 = elf32_arm_get_stub_entry
11892 }
11893 else
11899 {
11909 }
11910 else
11911 {
11912 /* Thumb blx encodes the offset in a complicated
11913 fashion. */
11923 {
11925 }
11926 else
11927 {
11929 /* Round up the offset to a word boundary. */
11931 }
11943 }
11944 }
11945 /* These relocations needs special care, as besides the fact
11946 they point somewhere in .gotplt, the addend must be
11947 adjusted accordingly depending on the type of instruction
11948 we refer to. */
11950 {
11959 {
11966 /* bl/blx */
11969 /* add */
11971 else
11972 {
11973 _bfd_error_handler
11974 /* xgettext:c-format */
11976 "unexpected %s instruction '%#lx' "
11981 }
11982 }
11983 else
11984 {
11988 {
11999 _bfd_error_handler
12000 /* xgettext:c-format */
12002 "unexpected %s instruction '%#lx' "
12007 }
12008 }
12016 }
12017 else
12025 {
12026 /* For FDPIC relocations, resolve to the offset of the GOT
12027 entry from the start of GOT. */
12033 }
12034 else
12035 {
12039 }
12040 }
12044 {
12045 _bfd_error_handler
12046 /* xgettext:c-format */
12051 }
12052 else
12061 {
12064 /* Ensure that we have a BX instruction. */
12068 {
12069 /* Branch to veneer. */
12070 bfd_vma glue_addr;
12077 }
12078 else
12079 {
12080 /* Preserve Rm (lowest four bits) and the condition code
12081 (highest four bits). Other bits encode MOV PC,Rm. */
12083 }
12086 }
12093 /* Until we properly support segment-base-relative addressing then
12094 we assume the segment base to be zero, as for the group relocations.
12095 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12096 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12100 {
12104 {
12107 }
12129 }
12136 /* Until we properly support segment-base-relative addressing then
12137 we assume the segment base to be zero, as for the above relocations.
12138 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12139 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12140 as R_ARM_THM_MOVT_ABS. */
12144 {
12145 bfd_vma insn;
12151 {
12157 }
12183 }
12196 {
12200 /* sb is the origin of the *segment* containing the symbol. */
12202 bfd_vma residual;
12203 bfd_vma g_n;
12204 bfd_signed_vma signed_value;
12207 /* Determine which group of bits to select. */
12209 {
12231 }
12233 /* If REL, extract the addend from the insn. If RELA, it will
12234 have already been fetched for us. */
12236 {
12243 else
12244 {
12245 /* Compensate for the fact that in the instruction, the
12246 rotation is stored in multiples of 2 bits. */
12249 /* Rotate "constant" right by "rotation" bits. */
12252 }
12254 /* Determine if the instruction is an ADD or a SUB.
12255 (For REL, this determines the sign of the addend.) */
12258 {
12259 _bfd_error_handler
12260 /* xgettext:c-format */
12265 }
12268 }
12270 /* Compute the value (X) to go in the place. */
12276 /* PC relative. */
12278 else
12279 /* Section base relative. */
12282 /* If the target symbol is a Thumb function, then set the
12283 Thumb bit in the address. */
12287 /* Calculate the value of the relevant G_n, in encoded
12288 constant-with-rotation format. */
12292 /* Check for overflow if required. */
12299 {
12300 _bfd_error_handler
12301 /* xgettext:c-format */
12308 }
12310 /* Mask out the value and the ADD/SUB part of the opcode; take care
12311 not to destroy the S bit. */
12314 /* Set the opcode according to whether the value to go in the
12315 place is negative. */
12318 else
12321 /* Encode the offset. */
12325 }
12334 {
12338 /* sb is the origin of the *segment* containing the symbol. */
12340 bfd_vma residual;
12341 bfd_signed_vma signed_value;
12344 /* Determine which groups of bits to calculate. */
12346 {
12364 }
12366 /* If REL, extract the addend from the insn. If RELA, it will
12367 have already been fetched for us. */
12369 {
12372 }
12374 /* Compute the value (X) to go in the place. */
12378 /* PC relative. */
12380 else
12381 /* Section base relative. */
12384 /* Calculate the value of the relevant G_{n-1} to obtain
12385 the residual at that stage. */
12389 /* Check for overflow. */
12391 {
12392 _bfd_error_handler
12393 /* xgettext:c-format */
12400 }
12402 /* Mask out the value and U bit. */
12405 /* Set the U bit if the value to go in the place is non-negative. */
12409 /* Encode the offset. */
12413 }
12422 {
12426 /* sb is the origin of the *segment* containing the symbol. */
12428 bfd_vma residual;
12429 bfd_signed_vma signed_value;
12432 /* Determine which groups of bits to calculate. */
12434 {
12452 }
12454 /* If REL, extract the addend from the insn. If RELA, it will
12455 have already been fetched for us. */
12457 {
12460 }
12462 /* Compute the value (X) to go in the place. */
12466 /* PC relative. */
12468 else
12469 /* Section base relative. */
12472 /* Calculate the value of the relevant G_{n-1} to obtain
12473 the residual at that stage. */
12477 /* Check for overflow. */
12479 {
12480 _bfd_error_handler
12481 /* xgettext:c-format */
12488 }
12490 /* Mask out the value and U bit. */
12493 /* Set the U bit if the value to go in the place is non-negative. */
12497 /* Encode the offset. */
12501 }
12510 {
12514 /* sb is the origin of the *segment* containing the symbol. */
12516 bfd_vma residual;
12517 bfd_signed_vma signed_value;
12520 /* Determine which groups of bits to calculate. */
12522 {
12540 }
12542 /* If REL, extract the addend from the insn. If RELA, it will
12543 have already been fetched for us. */
12545 {
12548 }
12550 /* Compute the value (X) to go in the place. */
12554 /* PC relative. */
12556 else
12557 /* Section base relative. */
12560 /* Calculate the value of the relevant G_{n-1} to obtain
12561 the residual at that stage. */
12565 /* Check for overflow. (The absolute value to go in the place must be
12566 divisible by four and, after having been divided by four, must
12567 fit in eight bits.) */
12569 {
12570 _bfd_error_handler
12571 /* xgettext:c-format */
12578 }
12580 /* Mask out the value and U bit. */
12583 /* Set the U bit if the value to go in the place is non-negative. */
12587 /* Encode the offset. */
12591 }
12598 {
12604 /* Compute address. */
12610 /* Clean imm8 insn. */
12612 /* And update with correct part of address. */
12614 /* Update insn. */
12616 }
12622 {
12624 {
12634 /* Resolve relocation. */
12637 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12638 not done yet. */
12642 }
12643 else
12644 {
12647 bfd_vma addr;
12650 /* For static binaries, sym_sec can be null. */
12652 {
12655 }
12656 else
12657 {
12660 }
12665 /* This case cannot occur since funcdesc is allocated by
12666 the dynamic loader so we cannot resolve the relocation. */
12670 /* Resolve relocation. */
12673 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12677 }
12678 }
12683 {
12685 {
12686 Elf_Internal_Rela outrel;
12688 /* Resolve relocation. */
12692 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12694 {
12697 bfd_vma addr;
12700 /* For static binaries sym_sec can be null. */
12702 {
12705 }
12706 else
12707 {
12710 }
12712 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12716 }
12718 /* Add a dynamic relocation on GOT entry if not already done. */
12720 {
12722 {
12727 else
12731 sgot->contents
12733 }
12734 else
12735 {
12737 }
12745 else
12747 else
12750 }
12751 }
12752 else
12753 {
12754 /* Such relocation on static function should not have been
12755 emitted by the compiler. */
12757 }
12758 }
12763 {
12765 {
12767 Elf_Internal_Rela outrel;
12776 /* Replace static FUNCDESC relocation with a
12777 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12778 executable. */
12785 else
12791 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12795 }
12796 else
12797 {
12799 {
12802 bfd_vma addr;
12804 Elf_Internal_Rela outrel;
12806 /* For static binaries sym_sec can be null. */
12808 {
12811 }
12812 else
12813 {
12816 }
12821 /* Replace static FUNCDESC relocation with a
12822 R_ARM_RELATIVE dynamic relocation. */
12829 else
12835 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12839 }
12840 else
12841 {
12842 Elf_Internal_Rela outrel;
12844 /* Add a dynamic relocation. */
12850 }
12851 }
12852 }
12858 }
12859 }
12861 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12862 static void
12866 bfd_signed_vma increment)
12867 {
12868 bfd_signed_vma addend;
12872 {
12890 }
12891 else
12892 {
12893 bfd_vma contents;
12897 /* Get the (signed) value from the instruction. */
12900 {
12901 bfd_signed_vma mask;
12906 }
12908 /* Add in the increment, (which is a byte value). */
12910 {
12922 /* Should we check for overflow here ? */
12924 /* Drop any undesired bits. */
12927 }
12932 }
12933 }
12935 #define IS_ARM_TLS_RELOC(R_TYPE) \
12936 ((R_TYPE) == R_ARM_TLS_GD32 \
12937 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
12938 || (R_TYPE) == R_ARM_TLS_LDO32 \
12939 || (R_TYPE) == R_ARM_TLS_LDM32 \
12940 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
12941 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12942 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12943 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12944 || (R_TYPE) == R_ARM_TLS_LE32 \
12945 || (R_TYPE) == R_ARM_TLS_IE32 \
12946 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
12947 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12949 /* Specific set of relocations for the gnu tls dialect. */
12950 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12951 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12952 || (R_TYPE) == R_ARM_TLS_CALL \
12953 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12954 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12955 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
12957 /* Relocate an ARM ELF section. */
12959 static bfd_boolean
12968 {
12986 {
12993 bfd_vma relocation;
12994 bfd_reloc_status_type r;
12995 arelent bfd_reloc;
13018 {
13023 /* An object file might have a reference to a local
13024 undefined symbol. This is a daft object file, but we
13025 should at least do something about it. V4BX & NONE
13026 relocations do not use the symbol and are explicitly
13027 allowed to use the undefined symbol, so allow those.
13028 Likewise for relocations against STN_UNDEF. */
13041 {
13048 {
13053 {
13075 {
13076 _bfd_error_handler
13077 /* xgettext:c-format */
13083 }
13087 /* Get the (signed) value from the instruction. */
13090 {
13091 bfd_signed_vma mask;
13096 }
13098 }
13101 addend =
13106 /* Cases here must match those in the preceding
13107 switch statement. */
13109 {
13132 }
13133 }
13134 }
13135 else
13137 }
13138 else
13139 {
13148 }
13155 {
13156 /* This is a relocatable link. We don't have to change
13157 anything, unless the reloc is against a section symbol,
13158 in which case we have to adjust according to where the
13159 section symbol winds up in the output section. */
13161 {
13165 else
13167 }
13169 }
13173 else
13174 {
13175 name = (bfd_elf_string_from_elf_section
13179 }
13187 {
13188 _bfd_error_handler
13190 /* xgettext:c-format */
13192 /* xgettext:c-format */
13194 input_bfd,
13195 input_section,
13198 name);
13199 }
13201 /* We call elf32_arm_final_link_relocate unless we're completely
13202 done, i.e., the relaxation produced the final output we want,
13203 and we won't let anybody mess with it. Also, we have to do
13204 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13205 both in relaxed and non-relaxed cases. */
13211 {
13214 /* This may have been marked unresolved because it came from
13215 a shared library. But we've just dealt with that. */
13217 }
13218 else
13222 {
13233 }
13235 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13236 because such sections are not SEC_ALLOC and thus ld.so will
13237 not process them. */
13243 {
13244 _bfd_error_handler
13245 /* xgettext:c-format */
13248 input_bfd,
13249 input_section,
13254 }
13257 {
13259 {
13261 /* If the overflowing reloc was to an undefined symbol,
13262 we have already printed one error message and there
13263 is no point complaining again. */
13284 /* error_message should already be set. */
13289 /* Fall through. */
13291 common_error:
13296 }
13297 }
13298 }
13301 }
13303 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13304 adds the edit to the start of the list. (The list must be built in order of
13305 ascending TINDEX: the function's callers are primarily responsible for
13306 maintaining that condition). */
13308 static void
13311 arm_unwind_edit_type type,
13314 {
13323 {
13333 }
13334 else
13335 {
13342 }
13343 }
13347 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13348 static void
13350 {
13358 /* Adjust size of output section. */
13360 }
13362 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13363 static void
13365 {
13377 }
13379 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13380 made to those tables, such that:
13382 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13383 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13384 codes which have been inlined into the index).
13386 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13388 The edits are applied when the tables are written
13389 (in elf32_arm_write_section). */
13391 bfd_boolean
13395 bfd_boolean merge_exidx_entries)
13396 {
13403 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13404 text sections. */
13406 {
13410 {
13418 {
13419 Elf_Internal_Shdr *linked_hdr
13427 /* Link this .ARM.exidx section back from the text section it
13428 describes. */
13430 }
13431 }
13432 }
13434 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13435 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13436 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13439 {
13446 bfd_vma j;
13457 {
13458 /* Section has no unwind data. */
13462 /* Ignore zero sized sections. */
13469 }
13471 /* Skip /DISCARD/ sections. */
13488 /* An error? */
13492 {
13494 /* Add cantunwind if first unwind item does not match section
13495 start. */
13497 {
13500 }
13501 }
13504 {
13509 /* An EXIDX_CANTUNWIND entry. */
13511 {
13515 }
13516 /* Inlined unwinding data. Merge if equal to previous. */
13518 {
13524 }
13525 /* Normal table entry. In theory we could merge these too,
13526 but duplicate entries are likely to be much less common. */
13527 else
13531 {
13536 }
13539 }
13541 /* Free contents if we allocated it ourselves. */
13545 /* Record edits to be applied later (in elf32_arm_write_section). */
13554 }
13556 /* Add terminating CANTUNWIND entry. */
13562 }
13564 static bfd_boolean
13567 {
13583 }
13585 static bfd_boolean
13587 {
13594 /* Invoke the regular ELF backend linker to do all the work. */
13598 /* Process stub sections (eg BE8 encoding, ...). */
13602 {
13604 /* Only process it once, in its link_sec slot. */
13606 {
13612 }
13613 }
13615 /* Write out any glue sections now that we have created all the
13616 stubs. */
13618 {
13621 ARM2THUMB_GLUE_SECTION_NAME))
13626 THUMB2ARM_GLUE_SECTION_NAME))
13631 VFP11_ERRATUM_VENEER_SECTION_NAME))
13636 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13641 ARM_BX_GLUE_SECTION_NAME))
13643 }
13646 }
13648 /* Return a best guess for the machine number based on the attributes. */
13650 static unsigned int
13652 {
13656 {
13663 {
13670 {
13678 {
13684 {
13688 }
13689 }
13690 }
13693 }
13723 /* Force entry to be added for any new known Tag_CPU_arch value. */
13726 /* Unknown Tag_CPU_arch value. */
13728 }
13729 }
13731 /* Set the right machine number. */
13733 static bfd_boolean
13735 {
13741 {
13744 else
13746 }
13750 }
13752 /* Function to keep ARM specific flags in the ELF header. */
13754 static bfd_boolean
13756 {
13759 {
13761 {
13763 _bfd_error_handler
13764 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
13765 abfd);
13766 else
13767 _bfd_error_handler
13769 abfd);
13770 }
13771 }
13772 else
13773 {
13776 }
13779 }
13781 /* Copy backend specific data from one object module to another. */
13783 static bfd_boolean
13785 {
13786 flagword in_flags;
13787 flagword out_flags;
13798 {
13799 /* Cannot mix APCS26 and APCS32 code. */
13803 /* Cannot mix float APCS and non-float APCS code. */
13807 /* If the src and dest have different interworking flags
13808 then turn off the interworking bit. */
13810 {
13812 _bfd_error_handler
13813 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
13817 }
13819 /* Likewise for PIC, though don't warn for this case. */
13822 }
13828 }
13830 /* Values for Tag_ABI_PCS_R9_use. */
13831 enum
13832 {
13833 AEABI_R9_V6,
13834 AEABI_R9_SB,
13835 AEABI_R9_TLS,
13836 AEABI_R9_unused
13837 };
13839 /* Values for Tag_ABI_PCS_RW_data. */
13840 enum
13841 {
13842 AEABI_PCS_RW_data_absolute,
13843 AEABI_PCS_RW_data_PCrel,
13844 AEABI_PCS_RW_data_SBrel,
13845 AEABI_PCS_RW_data_unused
13846 };
13848 /* Values for Tag_ABI_enum_size. */
13849 enum
13850 {
13851 AEABI_enum_unused,
13852 AEABI_enum_short,
13853 AEABI_enum_wide,
13854 AEABI_enum_forced_wide
13855 };
13857 /* Determine whether an object attribute tag takes an integer, a
13858 string or both. */
13860 static int
13862 {
13871 else
13873 }
13875 /* The ABI defines that Tag_conformance should be emitted first, and that
13876 Tag_nodefaults should be second (if either is defined). This sets those
13877 two positions, and bumps up the position of all the remaining tags to
13878 compensate. */
13879 static int
13881 {
13891 }
13893 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
13894 static bfd_boolean
13896 {
13898 {
13899 _bfd_error_handler
13904 }
13905 else
13906 {
13907 _bfd_error_handler
13911 }
13912 }
13914 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
13915 Returns -1 if no architecture could be read. */
13917 static int
13919 {
13923 /* Note: the tag and its argument below are uleb128 values, though
13924 currently-defined values fit in one byte for each. */
13931 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13933 }
13935 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13936 The tag is removed if ARCH is -1. */
13938 static void
13940 {
13945 {
13948 }
13950 /* Note: the tag and its argument below are uleb128 values, though
13951 currently-defined values fit in one byte for each. */
13957 }
13959 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13960 into account. */
13962 static int
13965 {
13966 #define T(X) TAG_CPU_ARCH_##X
13969 {
13979 };
13981 {
13992 };
13994 {
14006 };
14008 {
14021 };
14023 {
14037 };
14039 {
14054 };
14056 {
14072 };
14074 {
14091 };
14093 {
14111 };
14113 {
14132 };
14134 {
14154 };
14156 {
14157 v6t2,
14158 v6k,
14159 v7,
14160 v6_m,
14161 v6s_m,
14162 v7e_m,
14163 v8,
14164 v8r,
14165 v8m_baseline,
14166 v8m_mainline,
14167 /* Pseudo-architecture. */
14168 v4t_plus_v6_m
14169 };
14171 /* Check we've not got a higher architecture than we know about. */
14174 {
14177 }
14179 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14185 /* And override the new tag if we have a Tag_also_compatible_with on the
14186 input. */
14195 /* Architectures before V6KZ add features monotonically. */
14201 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14202 as the canonical version. */
14204 {
14207 }
14208 else
14212 {
14216 }
14219 #undef T
14220 }
14222 /* Query attributes object to see if integer divide instructions may be
14223 present in an object. */
14224 static bfd_boolean
14226 {
14231 {
14233 /* Integer divide allowed if instruction contained in archetecture. */
14238 else
14242 /* Integer divide explicitly prohibited. */
14246 /* Unrecognised case - treat as allowing divide everywhere. */
14248 /* Integer divide allowed in ARM state. */
14250 }
14251 }
14253 /* Query attributes object to see if integer divide instructions are
14254 forbidden to be in the object. This is not the inverse of
14255 elf32_arm_attributes_accept_div. */
14256 static bfd_boolean
14258 {
14260 }
14262 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14263 are conflicting attributes. */
14265 static bfd_boolean
14267 {
14271 /* Some tags have 0 = don't care, 1 = strong requirement,
14272 2 = weak requirement. */
14278 /* Skip the linker stubs file. This preserves previous behavior
14279 of accepting unknown attributes in the first input file - but
14280 is that a bug? */
14284 /* Skip any input that hasn't attribute section.
14285 This enables to link object files without attribute section with
14286 any others. */
14291 {
14292 /* This is the first object. Copy the attributes. */
14297 /* Use the Tag_null value to indicate the attributes have been
14298 initialized. */
14301 /* We do not output objects with Tag_MPextension_use_legacy - we move
14302 the attribute's value to Tag_MPextension_use. */
14304 {
14308 {
14309 _bfd_error_handler
14313 }
14319 }
14322 }
14326 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14328 {
14329 /* Ignore mismatches if the object doesn't use floating point or is
14330 floating point ABI independent. */
14337 {
14338 _bfd_error_handler
14343 }
14344 }
14347 {
14348 /* Merge this attribute with existing attributes. */
14350 {
14353 /* These are merged after Tag_CPU_arch. */
14358 /* Use the first value seen. */
14362 {
14367 {
14368 /* These aren't real CPU names, but we can't guess
14369 that from the architecture version alone. */
14387 };
14389 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14395 secondary_compat);
14397 /* Return with error if failed to merge. */
14405 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14409 {
14410 /* The output architecture has been changed to match the
14411 input architecture. Use the input names. */
14418 }
14419 else
14420 {
14423 }
14425 /* If we still don't have a value for Tag_CPU_name,
14426 make one up now. Tag_CPU_raw_name remains blank. */
14431 }
14438 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14447 /* Use the largest value specified. */
14454 /* Use the smallest value specified. */
14463 {
14464 /* This error message should be enabled once all non-conformant
14465 binaries in the toolchain have had the attributes set
14466 properly.
14467 _bfd_error_handler
14468 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14469 obfd, ibfd);
14470 result = FALSE; */
14471 }
14472 /* Fall through. */
14475 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14476 value if greater than 2 (for future-proofing). */
14484 /* The virtualization tag effectively stores two bits of
14485 information: the intended use of TrustZone (in bit 0), and the
14486 intended use of Virtualization (in bit 1). */
14491 {
14494 else
14495 {
14496 _bfd_error_handler
14501 }
14502 }
14507 {
14508 /* 0 will merge with anything.
14509 'A' and 'S' merge to 'A'.
14510 'R' and 'S' merge to 'R'.
14511 'M' and 'A|R|S' is an error. */
14520 else
14521 {
14522 _bfd_error_handler
14524 ibfd,
14528 }
14529 }
14533 /* No need to change output value if any of:
14534 - pre (<=) ARMv5T input architecture (do not have DSP)
14535 - M input profile not ARMv7E-M and do not have DSP. */
14541 /* Output value should be 0 if DSP part of architecture, ie.
14542 - post (>=) ARMv5te architecture output
14543 - A, R or S profile output or ARMv7E-M output architecture. */
14550 /* Otherwise, DSP instructions are added and not part of output
14551 architecture. */
14552 else
14557 {
14558 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14559 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14560 when it's 0. It might mean absence of FP hardware if
14561 Tag_FP_arch is zero. */
14563 #define VFP_VERSION_COUNT 9
14564 static const struct
14565 {
14569 {
14579 };
14584 /* If the output has no requirement about FP hardware,
14585 follow the requirement of the input. */
14587 {
14588 /* This assert is still reasonable, we shouldn't
14589 produce the suspicious build attribute
14590 combination (See below for in_attr). */
14596 }
14597 /* If the input has no requirement about FP hardware, do
14598 nothing. */
14600 {
14601 /* We used to assert that Tag_ABI_HardFP_use was
14602 zero here, but we should never assert when
14603 consuming an object file that has suspicious
14604 build attributes. The single precision variant
14605 of 'no FP architecture' is still 'no FP
14606 architecture', so we just ignore the tag in this
14607 case. */
14609 }
14611 /* Both the input and the output have nonzero Tag_FP_arch.
14612 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14614 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14615 do nothing. */
14618 ;
14619 /* If the input and the output have different Tag_ABI_HardFP_use,
14620 the combination of them is 0 (implied by Tag_FP_arch). */
14625 /* Now we can handle Tag_FP_arch. */
14627 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14628 pick the biggest. */
14631 {
14634 }
14635 /* The output uses the superset of input features
14636 (ISA version) and registers. */
14643 /* This assumes all possible supersets are also a valid
14644 options. */
14646 {
14650 }
14652 }
14658 {
14659 /* It's sometimes ok to mix different configs, so this is only
14660 a warning. */
14661 _bfd_error_handler
14663 }
14669 {
14670 _bfd_error_handler
14673 }
14681 {
14682 _bfd_error_handler
14684 ibfd);
14686 }
14687 /* Use the smallest value specified. */
14694 {
14695 _bfd_error_handler
14696 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
14698 }
14704 {
14707 {
14708 /* The existing object is compatible with anything.
14709 Use whatever requirements the new object has. */
14711 }
14715 {
14726 _bfd_error_handler
14727 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
14729 }
14730 }
14733 /* Aready done. */
14737 {
14738 _bfd_error_handler
14742 }
14745 /* Merged in target-independent code. */
14748 /* This is handled along with Tag_FP_arch. */
14752 {
14754 {
14755 _bfd_error_handler
14759 }
14760 }
14766 /* A value of zero on input means that the divide instruction may
14767 be used if available in the base architecture as specified via
14768 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14769 the user did not want divide instructions. A value of 2
14770 explicitly means that divide instructions were allowed in ARM
14771 and Thumb state. */
14785 /* We don't output objects with Tag_MPextension_use_legacy - we
14786 move the value to Tag_MPextension_use. */
14788 {
14790 {
14791 _bfd_error_handler
14794 ibfd);
14796 }
14797 }
14805 /* This tag is set if it exists, but the value is unused (and is
14806 typically zero). We don't actually need to do anything here -
14807 the merge happens automatically when the type flags are merged
14808 below. */
14811 /* Already done in Tag_CPU_arch. */
14814 /* Keep the attribute if it matches. Throw it away otherwise.
14815 No attribute means no claim to conform. */
14822 result
14824 }
14826 /* If out_attr was copied from in_attr then it won't have a type yet. */
14829 }
14831 /* Merge Tag_compatibility attributes and any common GNU ones. */
14835 /* Check for any attributes not known on ARM. */
14839 }
14842 /* Return TRUE if the two EABI versions are incompatible. */
14844 static bfd_boolean
14846 {
14847 /* v4 and v5 are the same spec before and after it was released,
14848 so allow mixing them. */
14854 }
14856 /* Merge backend specific data from an object file to the output
14857 object file when linking. */
14859 static bfd_boolean
14862 /* Display the flags field. */
14864 static bfd_boolean
14866 {
14872 /* Print normal ELF private data. */
14876 /* Ignore init flag - it may not be set, despite the flags field
14877 containing valid data. */
14882 {
14884 /* The following flag bits are GNU extensions and not part of the
14885 official ARM ELF extended ABI. Hence they are only decoded if
14886 the EABI version is not set. */
14892 else
14899 else
14928 else
14939 else
14971 eabi:
14984 }
15005 }
15007 static int
15009 {
15011 {
15016 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15017 This allows us to distinguish between data used by Thumb instructions
15018 and non-data (which is probably code) inside Thumb regions of an
15019 executable. */
15026 }
15029 }
15037 {
15040 {
15044 }
15047 }
15049 /* Look through the relocs for a section during the first phase. */
15051 static bfd_boolean
15054 {
15062 bfd_boolean call_reloc_p;
15063 bfd_boolean may_become_dynamic_p;
15064 bfd_boolean may_need_local_target_p;
15078 /* Create dynamic sections for relocatable executables so that we can
15079 copy relocations. */
15082 {
15085 }
15100 {
15112 /* PR 9934: It is possible to have relocations that do not
15113 refer to symbols, thus it is also possible to have an
15114 object file containing relocations but no symbol table. */
15116 {
15118 r_symndx);
15120 }
15125 {
15127 {
15128 /* A local symbol. */
15133 }
15134 else
15135 {
15140 }
15141 }
15149 /* Could be done earlier, if h were already available. */
15152 {
15154 {
15156 {
15161 }
15162 else
15163 {
15165 }
15166 }
15170 {
15172 {
15173 /* Such a relocation is not supposed to be generated
15174 by gcc on a static function. */
15175 /* Anyway if needed it could be handled. */
15177 }
15178 else
15179 {
15181 }
15182 }
15186 {
15188 {
15193 }
15194 else
15195 {
15197 }
15198 }
15212 /* This symbol requires a global offset table entry. */
15213 {
15217 {
15230 }
15236 {
15239 }
15240 else
15241 {
15242 /* This is a global offset table entry for a local symbol. */
15247 }
15249 /* If a variable is accessed with both tls methods, two
15250 slots may be created. */
15255 /* We will already have issued an error message if there
15256 is a TLS/non-TLS mismatch, based on the symbol
15257 type. So just combine any TLS types needed. */
15262 /* If the symbol is accessed in both IE and GDESC
15263 method, we're able to relax. Turn off the GDESC flag,
15264 without messing up with any other kind of tls types
15265 that may be involved. */
15270 {
15273 else
15275 }
15276 }
15277 /* Fall through. */
15283 /* Fall through. */
15305 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15306 ldr __GOTT_INDEX__ offsets. */
15308 {
15311 }
15314 /* Fall through. */
15321 {
15322 _bfd_error_handler
15323 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15328 }
15330 /* Fall through. */
15333 jump_over:
15335 {
15337 }
15338 /* Fall through. */
15346 /* Should the interworking branches be listed here? */
15350 {
15353 {
15354 /* In shared libraries and relocatable executables,
15355 we treat local relative references as calls;
15356 see the related SYMBOL_CALLS_LOCAL code in
15357 allocate_dynrelocs. */
15360 }
15361 else
15362 /* We are creating a shared library or relocatable
15363 executable, and this is a reloc against a global symbol,
15364 or a non-PC-relative reloc against a local symbol.
15365 We may need to copy the reloc into the output. */
15367 }
15368 else
15372 /* This relocation describes the C++ object vtable hierarchy.
15373 Reconstruct it for later use during GC. */
15379 /* This relocation describes which C++ vtable entries are actually
15380 used. Record for later use during GC. */
15387 }
15390 {
15392 /* We may need a .plt entry if the function this reloc
15393 refers to is in a different object, regardless of the
15394 symbol's type. We can't tell for sure yet, because
15395 something later might force the symbol local. */
15398 /* If this reloc is in a read-only section, we might
15399 need a copy reloc. We can't check reliably at this
15400 stage whether the section is read-only, as input
15401 sections have not yet been mapped to output sections.
15402 Tentatively set the flag for now, and correct in
15403 adjust_dynamic_symbol. */
15405 }
15409 {
15415 {
15418 }
15419 else
15420 {
15426 }
15428 /* If the symbol is a function that doesn't bind locally,
15429 this relocation will need a PLT entry. */
15436 /* It's too early to use htab->use_blx here, so we have to
15437 record possible blx references separately from
15438 relocs that definitely need a thumb stub. */
15446 }
15449 {
15452 /* Create a reloc section in dynobj. */
15454 {
15455 sreloc = _bfd_elf_make_dynamic_reloc_section
15461 /* BPABI objects never have dynamic relocations mapped. */
15463 {
15464 flagword flags;
15469 }
15470 }
15472 /* If this is a global symbol, count the number of
15473 relocations we need for this symbol. */
15476 else
15477 {
15481 }
15485 {
15496 }
15503 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15504 that will become rofixup. */
15505 /* This is due to the fact that we suppose all will become rofixup. */
15506 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15507 _bfd_error_handler
15512 }
15513 }
15514 }
15517 }
15519 static void
15522 {
15544 {
15547 }
15549 {
15552 }
15553 else
15565 {
15568 {
15571 irela++;
15572 count++;
15573 }
15575 {
15579 bfd_size_type j;
15580 bfd_vma offset;
15596 else
15600 {
15602 {
15604 bfd_vma bias;
15605 bfd_vma reloc_index;
15615 {
15616 bias++;
15618 }
15622 {
15624 irela++;
15625 count++;
15626 }
15629 }
15632 {
15633 /* New relocation entity. */
15642 irela++;
15643 count++;
15644 }
15645 }
15646 else
15647 {
15649 {
15652 irela++;
15653 }
15656 }
15657 }
15658 }
15666 {
15669 irela++;
15670 count--;
15671 }
15675 /* Hashes are no longer valid. */
15678 }
15680 /* Unwinding tables are not referenced directly. This pass marks them as
15681 required if the corresponding code section is marked. Similarly, ARMv8-M
15682 secure entry functions can only be referenced by SG veneers which are
15683 created after the GC process. They need to be marked in case they reside in
15684 their own section (as would be the case if code was compiled with
15685 -ffunction-sections). */
15687 static bfd_boolean
15689 elf_gc_mark_hook_fn gc_mark_hook)
15690 {
15708 /* Marking EH data may cause additional code sections to be marked,
15709 requiring multiple passes. */
15712 {
15715 {
15723 {
15732 {
15736 }
15737 }
15739 /* Mark section holding ARMv8-M secure entry functions. We mark all
15740 of them so no need for a second browsing. */
15742 {
15749 /* Scan symbols. */
15751 {
15754 /* Assume it is a special symbol. If not, cmse_scan will
15755 warn about it and user can do something about it. */
15757 {
15762 }
15763 }
15764 }
15765 }
15767 }
15770 }
15772 /* Treat mapping symbols as special target symbols. */
15774 static bfd_boolean
15776 {
15778 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
15779 }
15781 /* This is a copy of elf_find_function() from elf.c except that
15782 ARM mapping symbols are ignored when looking for function names
15783 and STT_ARM_TFUNC is considered to a function type. */
15785 static bfd_boolean
15789 bfd_vma offset,
15792 {
15799 {
15805 {
15814 /* Skip mapping symbols. */
15817 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
15819 /* Fall through. */
15823 {
15826 }
15828 }
15829 }
15840 }
15843 /* Find the nearest line to a particular section and offset, for error
15844 reporting. This code is a duplicate of the code in elf.c, except
15845 that it uses arm_elf_find_function. */
15847 static bfd_boolean
15851 bfd_vma offset,
15856 {
15864 {
15868 functionname_ptr);
15871 }
15873 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15874 uses DWARF1. */
15894 }
15896 static bfd_boolean
15901 {
15902 bfd_boolean found;
15907 }
15909 /* Find dynamic relocs for H that apply to read-only sections. */
15913 {
15917 {
15922 }
15924 }
15926 /* Adjust a symbol defined by a dynamic object and referenced by a
15927 regular object. The current definition is in some section of the
15928 dynamic object, but we're not including those sections. We have to
15929 change the definition to something the rest of the link can
15930 understand. */
15932 static bfd_boolean
15935 {
15947 /* Make sure we know what is going on here. */
15958 /* If this is a function, put it in the procedure linkage table. We
15959 will fill in the contents of the procedure linkage table later,
15960 when we know the address of the .got section. */
15962 {
15963 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15964 symbol binds locally. */
15970 {
15971 /* This case can occur if we saw a PLT32 reloc in an input
15972 file, but the symbol was never referred to by a dynamic
15973 object, or if all references were garbage collected. In
15974 such a case, we don't actually need to build a procedure
15975 linkage table, and we can just do a PC24 reloc instead. */
15981 }
15984 }
15985 else
15986 {
15987 /* It's possible that we incorrectly decided a .plt reloc was
15988 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15989 in check_relocs. We can't decide accurately between function
15990 and non-function syms in check-relocs; Objects loaded later in
15991 the link may change h->type. So fix it now. */
15996 }
15998 /* If this is a weak symbol, and there is a real definition, the
15999 processor independent code will have arranged for us to see the
16000 real definition first, and we can just use the same value. */
16002 {
16008 }
16010 /* If there are no non-GOT references, we do not need a copy
16011 relocation. */
16015 /* This is a reference to a symbol defined by a dynamic object which
16016 is not a function. */
16018 /* If we are creating a shared library, we must presume that the
16019 only references to the symbol are via the global offset table.
16020 For such cases we need not do anything here; the relocations will
16021 be handled correctly by relocate_section. Relocatable executables
16022 can reference data in shared objects directly, so we don't need to
16023 do anything here. */
16027 /* We must allocate the symbol in our .dynbss section, which will
16028 become part of the .bss section of the executable. There will be
16029 an entry for this symbol in the .dynsym section. The dynamic
16030 object will contain position independent code, so all references
16031 from the dynamic object to this symbol will go through the global
16032 offset table. The dynamic linker will use the .dynsym entry to
16033 determine the address it must put in the global offset table, so
16034 both the dynamic object and the regular object will refer to the
16035 same memory location for the variable. */
16036 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16037 linker to copy the initial value out of the dynamic object and into
16038 the runtime process image. We need to remember the offset into the
16039 .rel(a).bss section we are going to use. */
16041 {
16044 }
16045 else
16046 {
16049 }
16053 {
16056 }
16059 }
16061 /* Allocate space in .plt, .got and associated reloc sections for
16062 dynamic relocs. */
16064 static bfd_boolean
16066 {
16084 {
16085 /* Make sure this symbol is output as a dynamic symbol.
16086 Undefined weak syms won't yet be marked as dynamic. */
16089 {
16092 }
16094 /* If the call in the PLT entry binds locally, the associated
16095 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16096 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16097 than the .plt section. */
16099 {
16103 /* All non-call references can be resolved directly.
16104 This means that they can (and in some cases, must)
16105 resolve directly to the run-time target, rather than
16106 to the PLT. That in turns means that any .got entry
16107 would be equal to the .igot.plt entry, so there's
16108 no point having both. */
16110 }
16115 {
16118 /* If this symbol is not defined in a regular file, and we are
16119 not generating a shared library, then set the symbol to this
16120 location in the .plt. This is required to make function
16121 pointers compare as equal between the normal executable and
16122 the shared library. */
16125 {
16129 /* Make sure the function is not marked as Thumb, in case
16130 it is the target of an ABS32 relocation, which will
16131 point to the PLT entry. */
16133 }
16135 /* VxWorks executables have a second set of relocations for
16136 each PLT entry. They go in a separate relocation section,
16137 which is processed by the kernel loader. */
16139 {
16140 /* There is a relocation for the initial PLT entry:
16141 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16145 /* There are two extra relocations for each subsequent
16146 PLT entry: an R_ARM_32 relocation for the GOT entry,
16147 and an R_ARM_32 relocation for the PLT entry. */
16149 }
16150 }
16151 else
16152 {
16155 }
16156 }
16157 else
16158 {
16161 }
16167 {
16169 bfd_boolean dyn;
16173 /* Make sure this symbol is output as a dynamic symbol.
16174 Undefined weak syms won't yet be marked as dynamic. */
16177 {
16180 }
16183 {
16191 /* Non-TLS symbols need one GOT slot. */
16193 else
16194 {
16196 {
16197 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16198 eh->tlsdesc_got
16203 /* plt.got_offset needs to know there's a TLS_DESC
16204 reloc in the middle of .got.plt. */
16206 }
16209 {
16210 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16211 consecutive GOT slots. If the symbol is both GD
16212 and GDESC, got.offset may have been
16213 overwritten. */
16216 }
16219 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16220 slot. */
16222 }
16229 h)
16238 {
16246 {
16248 /* GDESC needs a trampoline to jump to. */
16250 }
16252 /* Only GD needs it. GDESC just emits one relocation per
16253 2 entries. */
16256 }
16259 {
16261 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16263 }
16266 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16267 they all resolve dynamically instead. Reserve room for the
16268 GOT entry's R_ARM_IRELATIVE relocation. */
16273 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16276 /* Reserve room for rofixup for FDPIC executable. */
16277 /* TLS relocs do not need space since they are completely
16278 resolved. */
16280 }
16281 }
16282 else
16285 /* FDPIC support. */
16287 {
16288 /* Symbol musn't be exported. */
16292 /* We only allocate one function descriptor with its associated relocation. */
16294 {
16299 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16302 else
16304 }
16305 }
16308 {
16317 {
16318 /* We only allocate one function descriptor with its associated relocation. q */
16320 {
16324 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16327 else
16329 }
16330 }
16332 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16333 R_ARM_RELATIVE/rofixup relocation on it. */
16338 else
16340 }
16343 {
16350 {
16351 /* We only allocate one function descriptor with its associated relocation. */
16353 {
16358 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16361 else
16363 }
16364 }
16366 {
16367 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16369 }
16370 else
16371 {
16372 /* Will need one dynamic reloc per reference. will be either
16373 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16376 }
16377 }
16379 /* Allocate stubs for exported Thumb functions on v4t. */
16384 {
16391 /* Create a new symbol to regist the real location of the function. */
16405 /* Point the symbol at the stub. */
16410 }
16415 /* In the shared -Bsymbolic case, discard space allocated for
16416 dynamic pc-relative relocs against symbols which turn out to be
16417 defined in regular objects. For the normal shared case, discard
16418 space for pc-relative relocs that have become local due to symbol
16419 visibility changes. */
16422 {
16423 /* Relocs that use pc_count are PC-relative forms, which will appear
16424 on something like ".long foo - ." or "movw REG, foo - .". We want
16425 calls to protected symbols to resolve directly to the function
16426 rather than going via the plt. If people want function pointer
16427 comparisons to work as expected then they should avoid writing
16428 assembly like ".long foo - .". */
16430 {
16434 {
16439 else
16441 }
16442 }
16445 {
16449 {
16452 else
16454 }
16455 }
16457 /* Also discard relocs on undefined weak syms with non-default
16458 visibility. */
16461 {
16466 /* Make sure undefined weak symbols are output as a dynamic
16467 symbol in PIEs. */
16470 {
16473 }
16474 }
16478 {
16479 /* Output absolute symbols so that we can create relocations
16480 against them. For normal symbols we output a relocation
16481 against the section that contains them. */
16484 }
16486 }
16487 else
16488 {
16489 /* For the non-shared case, discard space for relocs against
16490 symbols which turn out to need copy relocs or are not
16491 dynamic. */
16499 {
16500 /* Make sure this symbol is output as a dynamic symbol.
16501 Undefined weak syms won't yet be marked as dynamic. */
16504 {
16507 }
16509 /* If that succeeded, we know we'll be keeping all the
16510 relocs. */
16513 }
16517 keep: ;
16518 }
16520 /* Finally, allocate space. */
16522 {
16533 else
16535 }
16538 }
16540 /* Set DF_TEXTREL if we find any dynamic relocs that apply to
16541 read-only sections. */
16543 static bfd_boolean
16545 {
16553 {
16561 /* Not an error, just cut short the traversal. */
16563 }
16566 }
16568 void
16571 {
16579 }
16581 /* Set the sizes of the dynamic sections. */
16583 static bfd_boolean
16586 {
16589 bfd_boolean plt;
16590 bfd_boolean relocs;
16603 {
16604 /* Set the contents of the .interp section to the interpreter. */
16606 {
16611 }
16612 }
16614 /* Set up .got offsets for local syms, and space for local dynamic
16615 relocs. */
16617 {
16623 bfd_size_type locsymcount;
16634 {
16639 {
16642 {
16643 /* Input section has been discarded, either because
16644 it is a copy of a linkonce section or due to
16645 linker script /DISCARD/, so we'll be discarding
16646 the relocs too. */
16647 }
16651 {
16652 /* Relocations in vxworks .tls_vars sections are
16653 handled specially by the loader. */
16654 }
16656 {
16660 else
16664 }
16665 }
16666 }
16685 {
16689 /* FDPIC support. */
16691 {
16693 {
16697 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16700 else
16702 }
16703 }
16706 {
16708 {
16712 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16715 else
16717 }
16719 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16722 else
16724 }
16727 {
16731 {
16736 /* All references to the PLT are calls, so all
16737 non-call references can resolve directly to the
16738 run-time target. This means that the .got entry
16739 would be the same as the .igot.plt entry, so there's
16740 no point creating both. */
16742 }
16743 else
16744 {
16747 }
16750 {
16756 else
16758 }
16759 }
16761 {
16766 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16769 {
16774 /* plt.got_offset needs to know there's a TLS_DESC
16775 reloc in the middle of .got.plt. */
16777 }
16782 {
16783 /* If the symbol is both GD and GDESC, *local_got
16784 may have been overwritten. */
16787 }
16793 /* If all references to an STT_GNU_IFUNC PLT are calls,
16794 then all non-call references, including this GOT entry,
16795 resolve directly to the run-time target. */
16801 {
16809 {
16813 }
16814 }
16815 }
16816 else
16818 }
16819 }
16822 {
16823 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16824 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
16829 }
16830 else
16833 /* At the very end of the .rofixup section is a pointer to the GOT,
16834 reserve space for it. */
16838 /* Allocate global sym .plt and .got entries, and space for global
16839 sym dynamic relocs. */
16842 /* Here we rummage through the found bfds to collect glue information. */
16844 {
16848 /* Initialise mapping tables for code/data. */
16855 }
16857 /* Allocate space for the glue sections now that we've sized them. */
16860 /* For every jump slot reserved in the sgotplt, reloc_count is
16861 incremented. However, when we reserve space for TLS descriptors,
16862 it's not incremented, so in order to compute the space reserved
16863 for them, it suffices to multiply the reloc count by the jump
16864 slot size. */
16869 {
16876 /* If we're not using lazy TLS relocations, don't generate the
16877 PLT and GOT entries they require. */
16879 {
16885 }
16886 }
16888 /* The check_relocs and adjust_dynamic_symbol entry points have
16889 determined the sizes of the various dynamic sections. Allocate
16890 memory for them. */
16894 {
16900 /* It's OK to base decisions on the section name, because none
16901 of the dynobj section names depend upon the input files. */
16905 {
16906 /* Remember whether there is a PLT. */
16908 }
16910 {
16912 {
16913 /* Remember whether there are any reloc sections other
16914 than .rel(a).plt and .rela.plt.unloaded. */
16918 /* We use the reloc_count field as a counter if we need
16919 to copy relocs into the output file. */
16921 }
16922 }
16930 {
16931 /* It's not one of our sections, so don't allocate space. */
16933 }
16936 {
16937 /* If we don't need this section, strip it from the
16938 output file. This is mostly to handle .rel(a).bss and
16939 .rel(a).plt. We must create both sections in
16940 create_dynamic_sections, because they must be created
16941 before the linker maps input sections to output
16942 sections. The linker does that before
16943 adjust_dynamic_symbol is called, and it is that
16944 function which decides whether anything needs to go
16945 into these sections. */
16948 }
16953 /* Allocate memory for the section contents. */
16957 }
16960 {
16961 /* Add some entries to the .dynamic section. We fill in the
16962 values later, in elf32_arm_finish_dynamic_sections, but we
16963 must add the entries now so that we get the correct size for
16964 the .dynamic section. The DT_DEBUG entry is filled in by the
16965 dynamic linker and used by the debugger. */
16966 #define add_dynamic_entry(TAG, VAL) \
16967 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
16970 {
16973 }
16976 {
16988 }
16991 {
16993 {
16998 }
16999 else
17000 {
17005 }
17006 }
17008 /* If any dynamic relocs apply to a read-only section,
17009 then we need a DT_TEXTREL entry. */
17014 {
17017 }
17021 }
17022 #undef add_dynamic_entry
17025 }
17027 /* Size sections even though they're not dynamic. We use it to setup
17028 _TLS_MODULE_BASE_, if needed. */
17030 static bfd_boolean
17033 {
17045 {
17048 tlsbase = elf_link_hash_lookup
17052 {
17068 }
17069 }
17077 }
17079 /* Finish up dynamic symbol handling. We set the contents of various
17080 dynamic sections here. */
17082 static bfd_boolean
17087 {
17098 {
17100 {
17105 }
17108 {
17109 /* Mark the symbol as undefined, rather than as defined in
17110 the .plt section. */
17112 /* If the symbol is weak we need to clear the value.
17113 Otherwise, the PLT entry would provide a definition for
17114 the symbol even if the symbol wasn't defined anywhere,
17115 and so the symbol would never be NULL. Leave the value if
17116 there were any relocations where pointer equality matters
17117 (this is a clue for the dynamic linker, to make function
17118 pointer comparisons work between an application and shared
17119 library). */
17122 }
17124 {
17125 /* At least one non-call relocation references this .iplt entry,
17126 so the .iplt entry is the function's canonical address. */
17134 }
17135 }
17138 {
17140 Elf_Internal_Rela rel;
17142 /* This symbol needs a copy reloc. Set it up. */
17154 else
17157 }
17159 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17160 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17161 it is relative to the ".got" section. */
17167 }
17169 static void
17173 {
17177 {
17180 /* Emit mov pc,rx if bx is not permitted. */
17184 }
17185 }
17187 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17188 other variants, NaCl needs this entry in a static executable's
17189 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17190 zero. For .iplt really only the last bundle is useful, and .iplt
17191 could have a shorter first entry, with each individual PLT entry's
17192 relative branch calculated differently so it targets the last
17193 bundle instead of the instruction before it (labelled .Lplt_tail
17194 above). But it's simpler to keep the size and layout of PLT0
17195 consistent with the dynamic case, at the cost of some dead code at
17196 the start of .iplt and the one dead store to the stack at the start
17197 of .Lplt_tail. */
17198 static void
17201 {
17217 }
17219 /* Finish up the dynamic sections. */
17221 static bfd_boolean
17223 {
17236 /* A broken linker script might have discarded the dynamic sections.
17237 Catch this here so that we do not seg-fault later on. */
17243 {
17255 {
17256 Elf_Internal_Dyn dyn;
17263 {
17296 get_vma:
17299 {
17300 _bfd_error_handler
17304 }
17307 else
17308 /* In the BPABI, tags in the PT_DYNAMIC section point
17309 at the file offset, not the memory address, for the
17310 convenience of the post linker. */
17315 get_vma_if_bpabi:
17331 /* In the BPABI, the DT_REL tag must point at the file
17332 offset, not the VMA, of the first relocation
17333 section. So, we use code similar to that in
17334 elflink.c, but do not check for SHF_ALLOC on the
17335 relocation section, since relocation sections are
17336 never allocated under the BPABI. PLT relocs are also
17337 included. */
17339 {
17345 {
17346 Elf_Internal_Shdr *hdr
17349 {
17356 }
17357 }
17359 }
17376 /* Set the bottom bit of DT_INIT/FINI if the
17377 corresponding function is Thumb. */
17383 get_sym:
17384 /* If it wasn't set by elf_bfd_final_link
17385 then there is nothing to adjust. */
17387 {
17395 {
17398 }
17399 }
17401 }
17402 }
17404 /* Fill in the first entry in the procedure linkage table. */
17406 {
17410 /* Calculate the addresses of the GOT and PLT. */
17415 {
17416 /* The VxWorks GOT is relocated by the dynamic linker.
17417 Therefore, we must emit relocations rather than simply
17418 computing the values now. */
17419 Elf_Internal_Rela rel;
17430 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17436 }
17441 {
17453 }
17454 else
17455 {
17468 #ifdef FOUR_WORD_PLT
17469 /* The displacement value goes in the otherwise-unused
17470 last word of the second entry. */
17472 #else
17474 #endif
17475 }
17476 }
17478 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17479 really seem like the right value. */
17484 {
17485 bfd_vma got_address
17489 bfd_vma plt_address
17505 }
17508 {
17512 #ifdef FOUR_WORD_PLT
17515 #endif
17516 }
17521 {
17522 /* Correct the .rel(a).plt.unloaded relocations. They will have
17523 incorrect symbol indexes. */
17532 {
17533 Elf_Internal_Rela rel;
17544 }
17545 }
17546 }
17549 /* NaCl uses a special first entry in .iplt too. */
17552 /* Fill in the first three entries in the global offset table. */
17554 {
17556 {
17559 else
17565 }
17568 }
17570 /* At the very end of the .rofixup section is a pointer to the GOT. */
17572 {
17581 /* Make sure we allocated and generated the same number of fixups. */
17583 }
17586 }
17588 static void
17589 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
17590 {
17599 else
17604 {
17611 }
17615 {
17619 else
17621 }
17623 /* Scan segment to set p_flags attribute if it contains only sections with
17624 SHF_ARM_PURECODE flag. */
17626 {
17632 {
17635 }
17637 {
17640 }
17641 }
17642 }
17644 static enum elf_reloc_type_class
17648 {
17650 {
17661 }
17662 }
17664 static void
17666 {
17668 }
17670 /* Return TRUE if this is an unwinding table entry. */
17672 static bfd_boolean
17674 {
17677 }
17680 /* Set the type and flags for an ARM section. We do this by
17681 the section name, which is a hack, but ought to work. */
17683 static bfd_boolean
17685 {
17691 {
17694 }
17700 }
17702 /* Handle an ARM specific section when reading an object file. This is
17703 called when bfd_section_from_shdr finds a section with an unknown
17704 type. */
17706 static bfd_boolean
17711 {
17712 /* There ought to be a place to keep ELF backend specific flags, but
17713 at the moment there isn't one. We just keep track of the
17714 sections by their name, instead. Fortunately, the ABI gives
17715 names for all the ARM specific sections, so we will probably get
17716 away with this. */
17718 {
17726 }
17732 }
17736 {
17739 else
17741 }
17744 {
17753 enum map_symbol_type
17754 {
17755 ARM_MAP_ARM,
17756 ARM_MAP_THUMB,
17757 ARM_MAP_DATA
17758 };
17761 /* Output a single mapping symbol. */
17763 static bfd_boolean
17766 bfd_vma offset)
17767 {
17769 Elf_Internal_Sym sym;
17781 }
17783 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17784 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
17786 static bfd_boolean
17788 bfd_boolean is_iplt_entry_p,
17791 {
17803 {
17806 }
17807 else
17808 {
17811 }
17817 {
17822 }
17824 {
17833 }
17835 {
17838 }
17840 {
17842 ? ARM_MAP_THUMB
17855 }
17857 {
17860 }
17861 else
17862 {
17863 bfd_boolean thumb_stub_p;
17867 {
17870 }
17871 #ifdef FOUR_WORD_PLT
17876 #else
17877 /* A three-word PLT with no Thumb thunk contains only Arm code,
17878 so only need to output a mapping symbol for the first PLT entry and
17879 entries with thumb thunks. */
17881 {
17884 }
17885 #endif
17886 }
17889 }
17891 /* Output mapping symbols for PLT entries associated with H. */
17893 static bfd_boolean
17895 {
17903 /* When warning symbols are created, they **replace** the "real"
17904 entry in the hash table, thus we never get to see the real
17905 symbol in a hash traversal. So look at it now. */
17911 }
17913 /* Bind a veneered symbol to its veneer identified by its hash entry
17914 STUB_ENTRY. The veneered location thus loose its symbol. */
17916 static void
17918 {
17925 }
17927 /* Output a single local symbol for a generated stub. */
17929 static bfd_boolean
17932 {
17933 Elf_Internal_Sym sym;
17944 }
17946 static bfd_boolean
17949 {
17952 bfd_vma addr;
17961 /* Massage our args to the form they really have. */
17967 /* Ensure this stub is attached to the current section being
17968 processed. */
17977 else
17978 {
17981 {
17996 }
17997 }
18002 {
18004 {
18021 }
18024 {
18028 }
18031 {
18048 }
18049 }
18052 }
18054 /* Output mapping symbols for linker generated sections,
18055 and for those data-only sections that do not have a
18056 $d. */
18058 static bfd_boolean
18063 Elf_Internal_Sym *,
18064 asection *,
18066 {
18067 output_arch_syminfo osi;
18069 bfd_vma offset;
18070 bfd_size_type size;
18083 /* Add a $d mapping symbol to data-only sections that
18084 don't have any mapping symbol. This may result in (harmless) redundant
18085 mapping symbols. */
18089 {
18094 {
18099 == SEC_HAS_CONTENTS
18104 {
18109 }
18110 }
18111 }
18113 /* ARM->Thumb glue. */
18115 {
18117 ARM2THUMB_GLUE_SECTION_NAME);
18126 else
18130 {
18133 }
18134 }
18136 /* Thumb->ARM glue. */
18138 {
18140 THUMB2ARM_GLUE_SECTION_NAME);
18147 {
18150 }
18151 }
18153 /* ARMv4 BX veneers. */
18155 {
18157 ARM_BX_GLUE_SECTION_NAME);
18163 }
18165 /* Long calls stubs. */
18167 {
18173 {
18174 /* Ignore non-stub sections. */
18184 }
18185 }
18187 /* Finally, output mapping symbols for the PLT. */
18189 {
18194 /* Output mapping symbols for the plt header. SymbianOS does not have a
18195 plt header. */
18197 {
18198 /* VxWorks shared libraries have no PLT header. */
18200 {
18205 }
18206 }
18208 {
18211 }
18213 {
18220 }
18222 {
18225 #ifndef FOUR_WORD_PLT
18228 #endif
18229 }
18230 }
18232 {
18233 /* NaCl uses a special first entry in .iplt too. */
18239 }
18242 {
18247 {
18253 {
18261 }
18262 }
18263 }
18265 {
18266 /* Mapping symbols for the lazy tls trampoline. */
18273 }
18275 {
18276 /* Mapping symbols for the tls trampoline. */
18279 #ifdef FOUR_WORD_PLT
18283 #endif
18284 }
18287 }
18289 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18290 the import library. All SYMCOUNT symbols of ABFD can be examined
18291 from their pointers in SYMS. Pointers of symbols to keep should be
18292 stored continuously at the beginning of that array.
18294 Returns the number of symbols to keep. */
18296 static unsigned int
18300 {
18313 {
18316 flagword flags;
18331 {
18335 }
18350 }
18356 }
18358 /* Filter symbols of ABFD to include in the import library. All
18359 SYMCOUNT symbols of ABFD can be examined from their pointers in
18360 SYMS. Pointers of symbols to keep should be stored continuously at
18361 the beginning of that array.
18363 Returns the number of symbols to keep. */
18365 static unsigned int
18369 {
18372 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18373 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18374 library to be a relocatable object file. */
18378 else
18380 }
18382 /* Allocate target specific section data. */
18384 static bfd_boolean
18386 {
18388 {
18396 }
18399 }
18402 /* Used to order a list of mapping symbols by address. */
18404 static int
18406 {
18415 /* Ensure results do not depend on the host qsort for objects with
18416 multiple mapping symbols at the same address by sorting on type
18417 after vma. */
18421 else
18423 }
18425 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18427 static unsigned long
18429 {
18431 }
18433 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18434 relocations. */
18436 static void
18438 {
18442 /* High bit of first word is supposed to be zero. */
18446 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18447 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18453 }
18455 /* Data for make_branch_to_a8_stub(). */
18457 struct a8_branch_to_stub_data
18458 {
18461 };
18464 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18465 places for a particular section. */
18467 static bfd_boolean
18470 {
18476 bfd_signed_vma branch_offset;
18489 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18490 generated when both source and target are in the same section. */
18507 /* We attempt to avoid this condition by setting stubs_always_after_branch
18508 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18509 This check is just to be on the safe side... */
18511 {
18515 }
18518 {
18529 {
18534 jump24:
18536 {
18537 /* There's not much we can do apart from complain if this
18538 happens. */
18542 }
18544 /* i1 = not(j1 eor s), so:
18545 not i1 = j1 eor s
18546 j1 = (not i1) eor s. */
18558 }
18564 }
18570 }
18572 /* Beginning of stm32l4xx work-around. */
18574 /* Functions encoding instructions necessary for the emission of the
18575 fix-stm32l4xx-629360.
18576 Encoding is extracted from the
18577 ARM (C) Architecture Reference Manual
18578 ARMv7-A and ARMv7-R edition
18579 ARM DDI 0406C.b (ID072512). */
18583 {
18584 /* A8.8.18 B (A8-334)
18585 B target_address (Encoding T4). */
18586 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18587 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18588 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18605 }
18609 {
18610 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18611 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18618 }
18622 {
18623 /* A8.8.60 LDMDB/LDMEA (A8-402)
18624 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18631 }
18635 {
18636 /* A8.8.103 MOV (register) (A8-486)
18637 MOV Rd, Rm (Encoding T1). */
18644 }
18648 {
18649 /* A8.8.221 SUB (immediate) (A8-708)
18650 SUB Rd, Rn, #value (Encoding T3). */
18660 }
18665 {
18666 /* A8.8.332 VLDM (A8-922)
18667 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18676 }
18681 {
18682 /* A8.8.332 VLDM (A8-922)
18683 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18691 }
18695 {
18696 /* A8.8.247 UDF (A8-758)
18697 Undefined (Encoding T2). */
18703 }
18707 {
18708 /* A8.8.247 UDF (A8-758)
18709 Undefined (Encoding T1). */
18714 }
18716 /* Functions writing an instruction in memory, returning the next
18717 memory position to write to. */
18722 {
18725 }
18730 {
18733 }
18735 /* Function filling up a region in memory with T1 and T2 UDFs taking
18736 care of alignment. */
18744 {
18747 /* Fill the remaining of the stub with deterministic contents : UDF
18748 instructions.
18749 Check if realignment is needed on modulo 4 frontier using T1, to
18750 further use T2. */
18754 current_stub_contents =
18759 current_stub_contents =
18764 }
18766 /* Functions writing the stream of instructions equivalent to the
18767 derived sequence for ldmia, ldmdb, vldm respectively. */
18769 static void
18775 {
18788 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18789 smaller than 8 registers load sequences that do not cause the
18790 hardware issue. */
18792 {
18793 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18794 current_stub_contents =
18796 initial_insn);
18798 /* B initial_insn_addr+4. */
18800 current_stub_contents =
18802 create_instruction_branch_absolute
18805 /* Fill the remaining of the stub with deterministic contents. */
18806 current_stub_contents =
18809 base_stub_contents +
18810 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18813 }
18815 /* - reg_list[13] == 0. */
18818 /* - reg_list[14] & reg_list[15] != 1. */
18821 /* - if (wback==1) reg_list[rn] == 0. */
18824 /* - nb_registers > 8. */
18827 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18829 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18830 - One with the 7 lowest registers (register mask 0x007F)
18831 This LDM will finally contain between 2 and 7 registers
18832 - One with the 7 highest registers (register mask 0xDF80)
18833 This ldm will finally contain between 2 and 7 registers. */
18837 /* A spare register may be needed during this veneer to temporarily
18838 handle the base register. This register will be restored with the
18839 last LDM operation.
18840 The usable register may be any general purpose register (that
18841 excludes PC, SP, LR : register mask is 0x1FFF). */
18844 /* Generate the stub function. */
18846 {
18847 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18848 current_stub_contents =
18850 create_instruction_ldmia
18853 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18854 current_stub_contents =
18856 create_instruction_ldmia
18859 {
18860 /* B initial_insn_addr+4. */
18861 current_stub_contents =
18863 create_instruction_branch_absolute
18865 }
18866 }
18868 {
18871 /* If Rn is not part of the high-register-list, move it there. */
18873 {
18874 /* Choose a Ri in the high-register-list that will be restored. */
18877 /* MOV Ri, Rn. */
18878 current_stub_contents =
18881 }
18883 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18884 current_stub_contents =
18886 create_instruction_ldmia
18889 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18890 current_stub_contents =
18892 create_instruction_ldmia
18896 {
18897 /* B initial_insn_addr+4. */
18898 current_stub_contents =
18900 create_instruction_branch_absolute
18902 }
18903 }
18905 /* Fill the remaining of the stub with deterministic contents. */
18906 current_stub_contents =
18909 base_stub_contents +
18910 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18911 }
18913 static void
18919 {
18932 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18933 smaller than 8 registers load sequences that do not cause the
18934 hardware issue. */
18936 {
18937 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18938 current_stub_contents =
18940 initial_insn);
18942 /* B initial_insn_addr+4. */
18943 current_stub_contents =
18945 create_instruction_branch_absolute
18948 /* Fill the remaining of the stub with deterministic contents. */
18949 current_stub_contents =
18952 base_stub_contents +
18953 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18956 }
18958 /* - reg_list[13] == 0. */
18961 /* - reg_list[14] & reg_list[15] != 1. */
18964 /* - if (wback==1) reg_list[rn] == 0. */
18967 /* - nb_registers > 8. */
18970 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18972 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18973 - One with the 7 lowest registers (register mask 0x007F)
18974 This LDM will finally contain between 2 and 7 registers
18975 - One with the 7 highest registers (register mask 0xDF80)
18976 This ldm will finally contain between 2 and 7 registers. */
18980 /* A spare register may be needed during this veneer to temporarily
18981 handle the base register. This register will be restored with
18982 the last LDM operation.
18983 The usable register may be any general purpose register (that excludes
18984 PC, SP, LR : register mask is 0x1FFF). */
18987 /* Generate the stub function. */
18989 {
18990 /* Choose a Ri in the low-register-list that will be restored. */
18993 /* MOV Ri, Rn. */
18994 current_stub_contents =
18998 /* LDMDB Ri!, {R-high-register-list}. */
18999 current_stub_contents =
19001 create_instruction_ldmdb
19004 /* LDMDB Ri, {R-low-register-list}. */
19005 current_stub_contents =
19007 create_instruction_ldmdb
19010 /* B initial_insn_addr+4. */
19011 current_stub_contents =
19013 create_instruction_branch_absolute
19015 }
19017 {
19018 /* LDMDB Rn!, {R-high-register-list}. */
19019 current_stub_contents =
19021 create_instruction_ldmdb
19024 /* LDMDB Rn!, {R-low-register-list}. */
19025 current_stub_contents =
19027 create_instruction_ldmdb
19030 /* B initial_insn_addr+4. */
19031 current_stub_contents =
19033 create_instruction_branch_absolute
19035 }
19037 {
19038 /* Choose a Ri in the high-register-list that will be restored. */
19041 /* SUB Ri, Rn, #(4*nb_registers). */
19042 current_stub_contents =
19046 /* LDMIA Ri!, {R-low-register-list}. */
19047 current_stub_contents =
19049 create_instruction_ldmia
19052 /* LDMIA Ri, {R-high-register-list}. */
19053 current_stub_contents =
19055 create_instruction_ldmia
19057 }
19059 {
19060 /* Choose a Ri in the high-register-list that will be restored. */
19063 /* SUB Rn, Rn, #(4*nb_registers) */
19064 current_stub_contents =
19068 /* MOV Ri, Rn. */
19069 current_stub_contents =
19073 /* LDMIA Ri!, {R-low-register-list}. */
19074 current_stub_contents =
19076 create_instruction_ldmia
19079 /* LDMIA Ri, {R-high-register-list}. */
19080 current_stub_contents =
19082 create_instruction_ldmia
19084 }
19086 {
19089 {
19090 /* Choose a Ri in the low-register-list that will be restored. */
19093 /* MOV Ri, Rn. */
19094 current_stub_contents =
19097 }
19099 /* LDMDB Ri!, {R-high-register-list}. */
19100 current_stub_contents =
19102 create_instruction_ldmdb
19105 /* LDMDB Ri, {R-low-register-list}. */
19106 current_stub_contents =
19108 create_instruction_ldmdb
19111 /* B initial_insn_addr+4. */
19112 current_stub_contents =
19114 create_instruction_branch_absolute
19116 }
19118 {
19121 {
19122 /* Choose a Ri in the high-register-list that will be restored. */
19124 }
19126 /* SUB Ri, Rn, #(4*nb_registers). */
19127 current_stub_contents =
19131 /* LDMIA Ri!, {R-low-register-list}. */
19132 current_stub_contents =
19134 create_instruction_ldmia
19137 /* LDMIA Ri, {R-high-register-list}. */
19138 current_stub_contents =
19140 create_instruction_ldmia
19142 }
19144 {
19145 /* The assembler should not have accepted to encode this. */
19148 }
19150 /* Fill the remaining of the stub with deterministic contents. */
19151 current_stub_contents =
19154 base_stub_contents +
19155 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19157 }
19159 static void
19165 {
19171 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19172 smaller than 8 words load sequences that do not cause the
19173 hardware issue. */
19175 {
19176 /* Untouched instruction. */
19177 current_stub_contents =
19179 initial_insn);
19181 /* B initial_insn_addr+4. */
19182 current_stub_contents =
19184 create_instruction_branch_absolute
19186 }
19187 else
19188 {
19198 /* d = UInt (Vd:D);. */
19202 /* Compute the number of 8-words chunks needed to split. */
19206 /* The test coverage has been done assuming the following
19207 hypothesis that exactly one of the previous is_ predicates is
19208 true. */
19212 /* We treat the cutting of the words in one pass for all
19213 cases, then we emit the adjustments:
19215 vldm rx, {...}
19216 -> vldm rx!, {8_words_or_less} for each needed 8_word
19217 -> sub rx, rx, #size (list)
19219 vldm rx!, {...}
19220 -> vldm rx!, {8_words_or_less} for each needed 8_word
19221 This also handles vpop instruction (when rx is sp)
19223 vldmd rx!, {...}
19224 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19226 {
19230 {
19231 new_insn = create_instruction_vldmia
19233 is_dp,
19238 }
19240 {
19241 new_insn = create_instruction_vldmdb
19243 is_dp,
19247 }
19250 current_stub_contents =
19252 new_insn);
19253 }
19255 /* Only this case requires the base register compensation
19256 subtract. */
19258 {
19259 current_stub_contents =
19261 create_instruction_sub
19263 }
19265 /* B initial_insn_addr+4. */
19266 current_stub_contents =
19268 create_instruction_branch_absolute
19270 }
19272 /* Fill the remaining of the stub with deterministic contents. */
19273 current_stub_contents =
19276 base_stub_contents +
19277 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19278 }
19280 static void
19286 {
19290 stub_contents);
19294 stub_contents);
19298 stub_contents);
19299 }
19301 /* End of stm32l4xx work-around. */
19304 /* Do code byteswapping. Return FALSE afterwards so that the section is
19305 written out as normal. */
19307 static bfd_boolean
19312 {
19319 bfd_vma ptr;
19320 bfd_vma end;
19322 bfd_byte tmp;
19328 /* If this section has not been allocated an _arm_elf_section_data
19329 structure then we cannot record anything. */
19339 {
19344 {
19348 {
19350 {
19351 bfd_vma branch_to_veneer;
19352 /* Original condition code of instruction, plus bit mask for
19353 ARM B instruction. */
19357 /* The instruction is before the label. */
19360 /* Above offset included in -4 below. */
19374 }
19378 {
19379 bfd_vma branch_from_veneer;
19382 /* Take size of veneer into account. */
19391 /* Original instruction. */
19398 /* Branch back to insn after original insn. */
19404 }
19409 }
19410 }
19411 }
19414 {
19418 {
19422 {
19424 {
19426 bfd_vma branch_to_veneer =
19431 {
19432 bfd_vma out_of_range =
19438 _bfd_error_handler
19440 "cannot create STM32L4XX veneer; "
19443 output_bfd,
19447 }
19449 insn = create_instruction_branch_absolute
19452 /* The instruction is before the label. */
19457 }
19461 {
19467 veneer_r = veneer
19472 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19473 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19474 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19477 {
19481 }
19483 /* Original instruction. */
19486 stm32l4xx_create_replacing_stub
19488 }
19493 }
19494 }
19495 }
19498 {
19499 arm_unwind_table_edit *edit_node
19501 /* Now, sec->size is the size of the section we will write. The original
19502 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19503 markers) was sec->rawsize. (This isn't the case if we perform no
19504 edits, then rawsize will be zero and we should use size). */
19511 {
19513 {
19517 {
19520 out_index++;
19521 in_index++;
19522 }
19526 {
19528 {
19530 in_index++;
19535 {
19543 /* Note: this is meant to be equivalent to an
19544 R_ARM_PREL31 relocation. These synthetic
19545 EXIDX_CANTUNWIND markers are not relocated by the
19546 usual BFD method. */
19550 {
19551 /* Here relocation for new EXIDX_CANTUNWIND is
19552 created, so there is no need to
19553 adjust offset by hand. */
19556 }
19558 /* First address we can't unwind. */
19562 /* Code for EXIDX_CANTUNWIND. */
19566 out_index++;
19568 }
19570 }
19573 }
19574 }
19575 else
19576 {
19577 /* No more edits, copy remaining entries verbatim. */
19580 out_index++;
19581 in_index++;
19582 }
19583 }
19587 edited_contents,
19591 }
19593 /* Fix code to point to Cortex-A8 erratum stubs. */
19595 {
19603 }
19609 {
19614 {
19617 else
19621 {
19623 /* Byte swap code words. */
19625 {
19633 }
19637 /* Byte swap code halfwords. */
19639 {
19644 }
19648 /* Leave data alone. */
19650 }
19652 }
19653 }
19661 }
19663 /* Mangle thumb function symbols as we read them in. */
19665 static bfd_boolean
19670 {
19678 /* New EABI objects mark thumb function symbols by setting the low bit of
19679 the address. */
19682 {
19684 {
19687 ST_BRANCH_TO_THUMB);
19688 }
19689 else
19691 }
19693 {
19696 }
19699 else
19702 /* Mark CMSE special symbols. */
19710 }
19713 /* Mangle thumb function symbols as we write them out. */
19715 static void
19720 {
19721 Elf_Internal_Sym newsym;
19723 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19724 of the address set, as per the new EABI. We do this unconditionally
19725 because objcopy does not set the elf header flags until after
19726 it writes out the symbol table. */
19728 {
19733 {
19734 /* Do this only for defined symbols. At link type, the static
19735 linker will simulate the work of dynamic linker of resolving
19736 symbols and will carry over the thumbness of found symbols to
19737 the output symbol table. It's not clear how it happens, but
19738 the thumbness of undefined symbols can well be different at
19739 runtime, and writing '1' for them will be confusing for users
19740 and possibly for dynamic linker itself.
19741 */
19743 }
19746 }
19748 }
19750 /* Add the PT_ARM_EXIDX program header. */
19752 static bfd_boolean
19755 {
19761 {
19762 /* If there is already a PT_ARM_EXIDX header, then we do not
19763 want to add another one. This situation arises when running
19764 "strip"; the input binary already has the header. */
19769 {
19780 }
19781 }
19784 }
19786 /* We may add a PT_ARM_EXIDX program header. */
19788 static int
19791 {
19797 else
19799 }
19801 /* Hook called by the linker routine which adds symbols from an object
19802 file. */
19804 static bfd_boolean
19808 {
19818 }
19820 /* We use this to override swap_symbol_in and swap_symbol_out. */
19822 {
19835 bfd_elf32_write_out_phdrs,
19836 bfd_elf32_write_shdrs_and_ehdr,
19837 bfd_elf32_checksum_contents,
19838 bfd_elf32_write_relocs,
19839 elf32_arm_swap_symbol_in,
19840 elf32_arm_swap_symbol_out,
19841 bfd_elf32_slurp_reloc_table,
19842 bfd_elf32_slurp_symbol_table,
19843 bfd_elf32_swap_dyn_in,
19844 bfd_elf32_swap_dyn_out,
19845 bfd_elf32_swap_reloc_in,
19846 bfd_elf32_swap_reloc_out,
19847 bfd_elf32_swap_reloca_in,
19848 bfd_elf32_swap_reloca_out
19849 };
19851 static bfd_vma
19853 {
19854 /* V7 BE8 code is always little endian. */
19859 }
19861 static bfd_vma
19863 {
19864 /* V7 BE8 code is always little endian. */
19869 }
19871 /* Return size of plt0 entry starting at ADDR
19872 or (bfd_vma) -1 if size can not be determined. */
19874 static bfd_vma
19876 {
19877 bfd_vma first_word;
19878 bfd_vma plt0_size;
19886 else
19887 /* We don't yet handle this PLT format. */
19891 }
19893 /* Return size of plt entry starting at offset OFFSET
19894 of plt section located at address START
19895 or (bfd_vma) -1 if size can not be determined. */
19897 static bfd_vma
19899 {
19900 bfd_vma first_insn;
19904 /* PLT entry size if fixed on Thumb-only platforms. */
19908 /* Respect Thumb stub if necessary. */
19910 {
19912 }
19914 /* Strip immediate from first add. */
19917 #ifdef FOUR_WORD_PLT
19920 #else
19925 #endif
19926 else
19927 /* We don't yet handle this PLT format. */
19931 }
19933 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19935 static long
19942 {
19951 bfd_vma offset;
19980 {
19984 }
19990 {
19994 }
20008 {
20016 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20017 we are defining a symbol, ensure one of them is set. */
20029 {
20036 ;
20040 }
20045 }
20048 }
20050 static bfd_boolean
20052 {
20056 }
20058 static flagword
20060 {
20065 }
20067 static unsigned int
20069 {
20074 }
20076 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20077 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20078 FALSE otherwise. ISECTION is the best guess matching section from the
20079 input bfd IBFD, but it might be NULL. */
20081 static bfd_boolean
20086 {
20088 {
20090 {
20098 /* The sh_link field must be set to the text section associated with
20099 this index section. Unfortunately the ARM EHABI does not specify
20100 exactly how to determine this association. Our caller does try
20101 to match up OSECTION with its corresponding input section however
20102 so that is a good first guess. */
20113 )
20114 {
20119 }
20122 {
20123 /* Failing that we have to find a matching section ourselves. If
20124 we had the output section name available we could compare that
20125 with input section names. Unfortunately we don't. So instead
20126 we use a simple heuristic and look for the nearest executable
20127 section before this one. */
20139 }
20142 {
20144 /* If the text section was part of a group
20145 then the index section should be too. */
20149 }
20150 }
20162 }
20165 }
20167 /* Returns TRUE if NAME is an ARM mapping symbol.
20168 Traditionally the symbols $a, $d and $t have been used.
20169 The ARM ELF standard also defines $x (for A64 code). It also allows a
20170 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20171 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20172 not support them here. $t.x indicates the start of ThumbEE instructions. */
20174 static bfd_boolean
20176 {
20179 the mapping symbols could have acquired a prefix.
20180 We do not support this here, since such symbols no
20181 longer conform to the ARM ELF ABI. */
20184 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20185 any characters that follow the period are legal characters for the body
20186 of a symbol's name. For now we just assume that this is the case. */
20187 }
20189 /* Make sure that mapping symbols in object files are not removed via the
20190 "strip --strip-unneeded" tool. These symbols are needed in order to
20191 correctly generate interworking veneers, and for byte swapping code
20192 regions. Once an object file has been linked, it is safe to remove the
20193 symbols as they will no longer be needed. */
20195 static void
20197 {
20202 }
20204 #undef elf_backend_copy_special_section_fields
20205 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20207 #define ELF_ARCH bfd_arch_arm
20208 #define ELF_TARGET_ID ARM_ELF_DATA
20209 #define ELF_MACHINE_CODE EM_ARM
20210 #ifdef __QNXTARGET__
20211 #define ELF_MAXPAGESIZE 0x1000
20212 #else
20213 #define ELF_MAXPAGESIZE 0x10000
20214 #endif
20215 #define ELF_MINPAGESIZE 0x1000
20216 #define ELF_COMMONPAGESIZE 0x1000
20218 #define bfd_elf32_mkobject elf32_arm_mkobject
20220 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20221 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20222 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20223 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20224 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20225 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20226 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20227 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20228 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20229 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20230 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20231 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20232 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20234 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20235 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20236 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20237 #define elf_backend_check_relocs elf32_arm_check_relocs
20238 #define elf_backend_update_relocs elf32_arm_update_relocs
20239 #define elf_backend_relocate_section elf32_arm_relocate_section
20240 #define elf_backend_write_section elf32_arm_write_section
20241 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20242 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20243 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20244 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20245 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
20246 #define elf_backend_always_size_sections elf32_arm_always_size_sections
20247 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20248 #define elf_backend_post_process_headers elf32_arm_post_process_headers
20249 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20250 #define elf_backend_object_p elf32_arm_object_p
20251 #define elf_backend_fake_sections elf32_arm_fake_sections
20252 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20253 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20254 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20255 #define elf_backend_size_info elf32_arm_size_info
20256 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20257 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20258 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20259 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20260 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20261 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20262 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20263 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20265 #define elf_backend_can_refcount 1
20266 #define elf_backend_can_gc_sections 1
20267 #define elf_backend_plt_readonly 1
20268 #define elf_backend_want_got_plt 1
20269 #define elf_backend_want_plt_sym 0
20270 #define elf_backend_want_dynrelro 1
20271 #define elf_backend_may_use_rel_p 1
20272 #define elf_backend_may_use_rela_p 0
20273 #define elf_backend_default_use_rela_p 0
20274 #define elf_backend_dtrel_excludes_plt 1
20276 #define elf_backend_got_header_size 12
20277 #define elf_backend_extern_protected_data 1
20279 #undef elf_backend_obj_attrs_vendor
20281 #undef elf_backend_obj_attrs_section
20283 #undef elf_backend_obj_attrs_arg_type
20284 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20285 #undef elf_backend_obj_attrs_section_type
20286 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20287 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20288 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20290 #undef elf_backend_section_flags
20291 #define elf_backend_section_flags elf32_arm_section_flags
20292 #undef elf_backend_lookup_section_flags_hook
20293 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20295 #define elf_backend_linux_prpsinfo32_ugid16 TRUE
20299 /* Native Client targets. */
20301 #undef TARGET_LITTLE_SYM
20302 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20303 #undef TARGET_LITTLE_NAME
20305 #undef TARGET_BIG_SYM
20306 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20307 #undef TARGET_BIG_NAME
20310 /* Like elf32_arm_link_hash_table_create -- but overrides
20311 appropriately for NaCl. */
20315 {
20320 {
20328 }
20330 }
20332 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20333 really need to use elf32_arm_modify_segment_map. But we do it
20334 anyway just to reduce gratuitous differences with the stock ARM backend. */
20336 static bfd_boolean
20338 {
20341 }
20343 static void
20345 {
20348 }
20350 static bfd_vma
20353 {
20357 }
20359 #undef elf32_bed
20360 #define elf32_bed elf32_arm_nacl_bed
20361 #undef bfd_elf32_bfd_link_hash_table_create
20362 #define bfd_elf32_bfd_link_hash_table_create \
20363 elf32_arm_nacl_link_hash_table_create
20364 #undef elf_backend_plt_alignment
20365 #define elf_backend_plt_alignment 4
20366 #undef elf_backend_modify_segment_map
20367 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20368 #undef elf_backend_modify_program_headers
20369 #define elf_backend_modify_program_headers nacl_modify_program_headers
20370 #undef elf_backend_final_write_processing
20371 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20372 #undef bfd_elf32_get_synthetic_symtab
20373 #undef elf_backend_plt_sym_val
20374 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20375 #undef elf_backend_copy_special_section_fields
20377 #undef ELF_MINPAGESIZE
20378 #undef ELF_COMMONPAGESIZE
20383 /* Reset to defaults. */
20384 #undef elf_backend_plt_alignment
20385 #undef elf_backend_modify_segment_map
20386 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20387 #undef elf_backend_modify_program_headers
20388 #undef elf_backend_final_write_processing
20389 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20390 #undef ELF_MINPAGESIZE
20391 #define ELF_MINPAGESIZE 0x1000
20392 #undef ELF_COMMONPAGESIZE
20393 #define ELF_COMMONPAGESIZE 0x1000
20396 /* FDPIC Targets. */
20398 #undef TARGET_LITTLE_SYM
20399 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20400 #undef TARGET_LITTLE_NAME
20402 #undef TARGET_BIG_SYM
20403 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20404 #undef TARGET_BIG_NAME
20406 #undef elf_match_priority
20407 #define elf_match_priority 128
20408 #undef ELF_OSABI
20409 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20411 /* Like elf32_arm_link_hash_table_create -- but overrides
20412 appropriately for FDPIC. */
20416 {
20421 {
20425 }
20427 }
20429 /* We need dynamic symbols for every section, since segments can
20430 relocate independently. */
20431 static bfd_boolean
20434 ATTRIBUTE_UNUSED,
20436 {
20438 {
20441 /* If sh_type is yet undecided, assume it could be
20442 SHT_PROGBITS/SHT_NOBITS. */
20446 /* There shouldn't be section relative relocations
20447 against any other section. */
20450 }
20451 }
20453 #undef elf32_bed
20454 #define elf32_bed elf32_arm_fdpic_bed
20456 #undef bfd_elf32_bfd_link_hash_table_create
20457 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20459 #undef elf_backend_omit_section_dynsym
20460 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20464 #undef elf_match_priority
20465 #undef ELF_OSABI
20466 #undef elf_backend_omit_section_dynsym
20468 /* VxWorks Targets. */
20470 #undef TARGET_LITTLE_SYM
20471 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20472 #undef TARGET_LITTLE_NAME
20474 #undef TARGET_BIG_SYM
20475 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20476 #undef TARGET_BIG_NAME
20479 /* Like elf32_arm_link_hash_table_create -- but overrides
20480 appropriately for VxWorks. */
20484 {
20489 {
20494 }
20496 }
20498 static void
20500 {
20503 }
20505 #undef elf32_bed
20506 #define elf32_bed elf32_arm_vxworks_bed
20508 #undef bfd_elf32_bfd_link_hash_table_create
20509 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20510 #undef elf_backend_final_write_processing
20511 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20512 #undef elf_backend_emit_relocs
20513 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20515 #undef elf_backend_may_use_rel_p
20516 #define elf_backend_may_use_rel_p 0
20517 #undef elf_backend_may_use_rela_p
20518 #define elf_backend_may_use_rela_p 1
20519 #undef elf_backend_default_use_rela_p
20520 #define elf_backend_default_use_rela_p 1
20521 #undef elf_backend_want_plt_sym
20522 #define elf_backend_want_plt_sym 1
20523 #undef ELF_MAXPAGESIZE
20524 #define ELF_MAXPAGESIZE 0x1000
20529 /* Merge backend specific data from an object file to the output
20530 object file when linking. */
20532 static bfd_boolean
20534 {
20536 flagword out_flags;
20537 flagword in_flags;
20541 /* Check if we have the same endianness. */
20551 /* The input BFD must have had its flags initialised. */
20552 /* The following seems bogus to me -- The flags are initialized in
20553 the assembler but I don't think an elf_flags_init field is
20554 written into the object. */
20555 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20560 /* In theory there is no reason why we couldn't handle this. However
20561 in practice it isn't even close to working and there is no real
20562 reason to want it. */
20566 {
20568 ibfd);
20570 }
20573 {
20574 /* If the input is the default architecture and had the default
20575 flags then do not bother setting the flags for the output
20576 architecture, instead allow future merges to do this. If no
20577 future merges ever set these flags then they will retain their
20578 uninitialised values, which surprise surprise, correspond
20579 to the default values. */
20592 }
20594 /* Determine what should happen if the input ARM architecture
20595 does not match the output ARM architecture. */
20599 /* Identical flags must be compatible. */
20603 /* Check to see if the input BFD actually contains any sections. If
20604 not, its flags may not have been initialised either, but it
20605 cannot actually cause any incompatiblity. Do not short-circuit
20606 dynamic objects; their section list may be emptied by
20607 elf_link_add_object_symbols.
20609 Also check to see if there are no code sections in the input.
20610 In this case there is no need to check for code specific flags.
20611 XXX - do we need to worry about floating-point format compatability
20612 in data sections ? */
20614 {
20619 {
20620 /* Ignore synthetic glue sections. */
20623 {
20631 }
20632 }
20636 }
20638 /* Complain about various flag mismatches. */
20641 {
20642 _bfd_error_handler
20647 }
20649 /* Not sure what needs to be checked for EABI versions >= 1. */
20650 /* VxWorks libraries do not use these flags. */
20654 {
20656 {
20657 _bfd_error_handler
20662 }
20665 {
20667 _bfd_error_handler
20668 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20670 else
20671 _bfd_error_handler
20672 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20676 }
20679 {
20681 _bfd_error_handler
20684 else
20685 _bfd_error_handler
20690 }
20693 {
20695 _bfd_error_handler
20698 else
20699 _bfd_error_handler
20704 }
20706 #ifdef EF_ARM_SOFT_FLOAT
20708 {
20709 /* We can allow interworking between code that is VFP format
20710 layout, and uses either soft float or integer regs for
20711 passing floating point arguments and results. We already
20712 know that the APCS_FLOAT flags match; similarly for VFP
20713 flags. */
20716 {
20718 _bfd_error_handler
20721 else
20722 _bfd_error_handler
20727 }
20728 }
20729 #endif
20731 /* Interworking mismatch is only a warning. */
20733 {
20735 {
20736 _bfd_error_handler
20739 }
20740 else
20741 {
20742 _bfd_error_handler
20745 }
20746 }
20747 }
20750 }
20753 /* Symbian OS Targets. */
20755 #undef TARGET_LITTLE_SYM
20756 #define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20757 #undef TARGET_LITTLE_NAME
20759 #undef TARGET_BIG_SYM
20760 #define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20761 #undef TARGET_BIG_NAME
20764 /* Like elf32_arm_link_hash_table_create -- but overrides
20765 appropriately for Symbian OS. */
20769 {
20774 {
20777 /* There is no PLT header for Symbian OS. */
20779 /* The PLT entries are each one instruction and one word. */
20782 /* Symbian uses armv5t or above, so use_blx is always true. */
20785 }
20787 }
20789 static const struct bfd_elf_special_section
20790 elf32_arm_symbian_special_sections[] =
20791 {
20792 /* In a BPABI executable, the dynamic linking sections do not go in
20793 the loadable read-only segment. The post-linker may wish to
20794 refer to these sections, but they are not part of the final
20795 program image. */
20801 /* These sections do not need to be writable as the SymbianOS
20802 postlinker will arrange things so that no dynamic relocation is
20803 required. */
20808 };
20810 static void
20813 {
20814 /* BPABI objects are never loaded directly by an OS kernel; they are
20815 processed by a postlinker first, into an OS-specific format. If
20816 the D_PAGED bit is set on the file, BFD will align segments on
20817 page boundaries, so that an OS can directly map the file. With
20818 BPABI objects, that just results in wasted space. In addition,
20819 because we clear the D_PAGED bit, map_sections_to_segments will
20820 recognize that the program headers should not be mapped into any
20821 loadable segment. */
20824 }
20826 static bfd_boolean
20829 {
20833 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20834 segment. However, because the .dynamic section is not marked
20835 with SEC_LOAD, the generic ELF code will not create such a
20836 segment. */
20839 {
20845 {
20849 }
20850 }
20852 /* Also call the generic arm routine. */
20854 }
20856 /* Return address for Ith PLT stub in section PLT, for relocation REL
20857 or (bfd_vma) -1 if it should not be included. */
20859 static bfd_vma
20862 {
20864 }
20866 #undef elf32_bed
20867 #define elf32_bed elf32_arm_symbian_bed
20869 /* The dynamic sections are not allocated on SymbianOS; the postlinker
20870 will process them and then discard them. */
20871 #undef ELF_DYNAMIC_SEC_FLAGS
20872 #define ELF_DYNAMIC_SEC_FLAGS \
20873 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20875 #undef elf_backend_emit_relocs
20877 #undef bfd_elf32_bfd_link_hash_table_create
20878 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20879 #undef elf_backend_special_sections
20880 #define elf_backend_special_sections elf32_arm_symbian_special_sections
20881 #undef elf_backend_begin_write_processing
20882 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20883 #undef elf_backend_final_write_processing
20884 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20886 #undef elf_backend_modify_segment_map
20887 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20889 /* There is no .got section for BPABI objects, and hence no header. */
20890 #undef elf_backend_got_header_size
20891 #define elf_backend_got_header_size 0
20893 /* Similarly, there is no .got.plt section. */
20894 #undef elf_backend_want_got_plt
20895 #define elf_backend_want_got_plt 0
20897 #undef elf_backend_plt_sym_val
20898 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20900 #undef elf_backend_may_use_rel_p
20901 #define elf_backend_may_use_rel_p 1
20902 #undef elf_backend_may_use_rela_p
20903 #define elf_backend_may_use_rela_p 0
20904 #undef elf_backend_default_use_rela_p
20905 #define elf_backend_default_use_rela_p 0
20906 #undef elf_backend_want_plt_sym
20907 #define elf_backend_want_plt_sym 0
20908 #undef elf_backend_dtrel_excludes_plt
20909 #define elf_backend_dtrel_excludes_plt 0
20910 #undef ELF_MAXPAGESIZE
20911 #define ELF_MAXPAGESIZE 0x8000