opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2025 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #include <limits.h>
  23 #ifndef CHAR_BIT
  24 #define CHAR_BIT 8
  25 #endif
  26
  27 /* Position of cpu flags bitfiled.  */
  28
  29 enum i386_cpu
  30 {
  31   /* i186 or better required */
  32   Cpu186 = 0,
  33   /* i286 or better required */
  34   Cpu286,
  35   /* i386 or better required */
  36   Cpu386,
  37   /* i486 or better required */
  38   Cpu486,
  39   /* i585 or better required */
  40   Cpu586,
  41   /* i686 or better required */
  42   Cpu686,
  43   /* CMOV Instruction support required */
  44   CpuCMOV,
  45   /* FXSR Instruction support required */
  46   CpuFXSR,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i686 and floating point support required */
  56   Cpu687,
  57   /* SSE3 and floating point support required */
  58   CpuFISTTP,
  59   /* MMX support required */
  60   CpuMMX,
  61   /* SSE support required */
  62   CpuSSE,
  63   /* SSE2 support required */
  64   CpuSSE2,
  65   /* SSE3 support required */
  66   CpuSSE3,
  67   /* VIA PadLock required */
  68   CpuPadLock,
  69   /* ZHAOXIN GMI required */
  70   CpuGMI,
  71   /* AMD Secure Virtual Machine Ext-s required */
  72   CpuSVME,
  73   /* VMX Instructions required */
  74   CpuVMX,
  75   /* SMX Instructions required */
  76   CpuSMX,
  77   /* SSSE3 support required */
  78   CpuSSSE3,
  79   /* SSE4a support required */
  80   CpuSSE4a,
  81   /* LZCNT support required */
  82   CpuLZCNT,
  83   /* POPCNT support required */
  84   CpuPOPCNT,
  85   /* MONITOR support required */
  86   CpuMONITOR,
  87   /* SSE4.1 support required */
  88   CpuSSE4_1,
  89   /* SSE4.2 support required */
  90   CpuSSE4_2,
  91   /* AVX2 support required */
  92   CpuAVX2,
  93   /* Intel AVX-512 Conflict Detection Instructions support required */
  94   CpuAVX512CD,
  95   /* Intel AVX-512 Exponential and Reciprocal Instructions support
  96      required */
  97   CpuAVX512ER,
  98   /* Intel AVX-512 Prefetch Instructions support required */
  99   CpuAVX512PF,
 100   /* Intel AVX-512 DQ Instructions support required.  */
 101   CpuAVX512DQ,
 102   /* Intel AVX-512 BW Instructions support required.  */
 103   CpuAVX512BW,
 104   /* Intel IAMCU support required */
 105   CpuIAMCU,
 106   /* Xsave/xrstor New Instructions support required */
 107   CpuXsave,
 108   /* Xsaveopt New Instructions support required */
 109   CpuXsaveopt,
 110   /* AES support required */
 111   CpuAES,
 112   /* PCLMULQDQ support required */
 113   CpuPCLMULQDQ,
 114   /* FMA support required */
 115   CpuFMA,
 116   /* FMA4 support required */
 117   CpuFMA4,
 118   /* XOP support required */
 119   CpuXOP,
 120   /* LWP support required */
 121   CpuLWP,
 122   /* BMI support required */
 123   CpuBMI,
 124   /* TBM support required */
 125   CpuTBM,
 126   /* MOVBE Instruction support required */
 127   CpuMovbe,
 128   /* CMPXCHG16B instruction support required.  */
 129   CpuCX16,
 130   /* LAHF/SAHF instruction support required (in 64-bit mode).  */
 131   CpuLAHF_SAHF,
 132   /* EPT Instructions required */
 133   CpuEPT,
 134   /* RDTSCP Instruction support required */
 135   CpuRdtscp,
 136   /* FSGSBASE Instructions required */
 137   CpuFSGSBase,
 138   /* RDRND Instructions required */
 139   CpuRdRnd,
 140   /* F16C Instructions required */
 141   CpuF16C,
 142   /* Intel BMI2 support required */
 143   CpuBMI2,
 144   /* RTM support required */
 145   CpuRTM,
 146   /* INVPCID Instructions required */
 147   CpuINVPCID,
 148   /* VMFUNC Instruction required */
 149   CpuVMFUNC,
 150   /* Intel MPX Instructions required  */
 151   CpuMPX,
 152   /* RDRSEED instruction required.  */
 153   CpuRDSEED,
 154   /* Multi-presisionn add-carry instructions are required.  */
 155   CpuADX,
 156   /* Supports prefetchw and prefetch instructions.  */
 157   CpuPRFCHW,
 158   /* SMAP instructions required.  */
 159   CpuSMAP,
 160   /* SHA instructions required.  */
 161   CpuSHA,
 162   /* SHA512 instructions required.  */
 163   CpuSHA512,
 164   /* SM3 instructions required.  */
 165   CpuSM3,
 166   /* SM4 instructions required.  */
 167   CpuSM4,
 168   /* CLFLUSHOPT instruction required */
 169   CpuClflushOpt,
 170   /* XSAVES/XRSTORS instruction required */
 171   CpuXSAVES,
 172   /* XSAVEC instruction required */
 173   CpuXSAVEC,
 174   /* PREFETCHWT1 instruction required */
 175   CpuPREFETCHWT1,
 176   /* SE1 instruction required */
 177   CpuSE1,
 178   /* CLWB instruction required */
 179   CpuCLWB,
 180   /* Intel AVX-512 IFMA Instructions support required.  */
 181   CpuAVX512IFMA,
 182   /* Intel AVX-512 VBMI Instructions support required.  */
 183   CpuAVX512VBMI,
 184   /* Intel AVX-512 4FMAPS Instructions support required.  */
 185   CpuAVX512_4FMAPS,
 186   /* Intel AVX-512 4VNNIW Instructions support required.  */
 187   CpuAVX512_4VNNIW,
 188   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 189   CpuAVX512_VPOPCNTDQ,
 190   /* Intel AVX-512 VBMI2 Instructions support required.  */
 191   CpuAVX512_VBMI2,
 192   /* Intel AVX-512 VNNI Instructions support required.  */
 193   CpuAVX512_VNNI,
 194   /* Intel AVX-512 BITALG Instructions support required.  */
 195   CpuAVX512_BITALG,
 196   /* Intel AVX-512 BF16 Instructions support required.  */
 197   CpuAVX512_BF16,
 198   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 199   CpuAVX512_VP2INTERSECT,
 200   /* TDX Instructions support required.  */
 201   CpuTDX,
 202   /* Intel AVX VNNI Instructions support required.  */
 203   CpuAVX_VNNI,
 204   /* Intel AVX-512 FP16 Instructions support required.  */
 205   CpuAVX512_FP16,
 206   /* PREFETCHI instruction required */
 207   CpuPREFETCHI,
 208   /* Intel AVX IFMA Instructions support required.  */
 209   CpuAVX_IFMA,
 210   /* Intel AVX VNNI-INT8 Instructions support required.  */
 211   CpuAVX_VNNI_INT8,
 212   /* Intel AVX VNNI-INT16 Instructions support required.  */
 213   CpuAVX_VNNI_INT16,
 214   /* Intel CMPccXADD instructions support required.  */
 215   CpuCMPCCXADD,
 216   /* Intel WRMSRNS Instructions support required */
 217   CpuWRMSRNS,
 218   /* Intel MSRLIST Instructions support required.  */
 219   CpuMSRLIST,
 220   /* Intel AVX NE CONVERT Instructions support required.  */
 221   CpuAVX_NE_CONVERT,
 222   /* Intel RAO INT Instructions support required.  */
 223   CpuRAO_INT,
 224   /* fred instruction required */
 225   CpuFRED,
 226   /* lkgs instruction required */
 227   CpuLKGS,
 228   /* Intel USER_MSR Instruction support required.  */
 229   CpuUSER_MSR,
 230   /* Intel MSR_IMM Instructions support required.  */
 231   CpuMSR_IMM,
 232   /* mwaitx instruction required */
 233   CpuMWAITX,
 234   /* Clzero instruction required */
 235   CpuCLZERO,
 236   /* OSPKE instruction required */
 237   CpuOSPKE,
 238   /* RDPID instruction required */
 239   CpuRDPID,
 240   /* PTWRITE instruction required */
 241   CpuPTWRITE,
 242   /* CET instructions support required */
 243   CpuIBT,
 244   CpuSHSTK,
 245   /* AMX-INT8 instructions required */
 246   CpuAMX_INT8,
 247   /* AMX-BF16 instructions required */
 248   CpuAMX_BF16,
 249   /* AMX-FP16 instructions required */
 250   CpuAMX_FP16,
 251   /* AMX-COMPLEX instructions required.  */
 252   CpuAMX_COMPLEX,
 253   /* AMX-TF32 Instructions support required.  */
 254   CpuAMX_TF32,
 255   /* AMX-TILE instructions required */
 256   CpuAMX_TILE,
 257   /* GFNI instructions required */
 258   CpuGFNI,
 259   /* VAES instructions required */
 260   CpuVAES,
 261   /* VPCLMULQDQ instructions required */
 262   CpuVPCLMULQDQ,
 263   /* WBNOINVD instructions required */
 264   CpuWBNOINVD,
 265   /* PCONFIG instructions required */
 266   CpuPCONFIG,
 267   /* PBNDKB instructions required.  */
 268   CpuPBNDKB,
 269   /* WAITPKG instructions required */
 270   CpuWAITPKG,
 271   /* UINTR instructions required */
 272   CpuUINTR,
 273   /* CLDEMOTE instruction required */
 274   CpuCLDEMOTE,
 275   /* MOVDIRI instruction support required */
 276   CpuMOVDIRI,
 277   /* MOVDIRR64B instruction required */
 278   CpuMOVDIR64B,
 279   /* ENQCMD instruction required */
 280   CpuENQCMD,
 281   /* SERIALIZE instruction required */
 282   CpuSERIALIZE,
 283   /* RDPRU instruction required */
 284   CpuRDPRU,
 285   /* MCOMMIT instruction required */
 286   CpuMCOMMIT,
 287   /* SEV-ES instruction(s) required */
 288   CpuSEV_ES,
 289   /* TSXLDTRK instruction required */
 290   CpuTSXLDTRK,
 291   /* KL instruction support required */
 292   CpuKL,
 293   /* WideKL instruction support required */
 294   CpuWideKL,
 295   /* HRESET instruction required */
 296   CpuHRESET,
 297   /* INVLPGB instructions required */
 298   CpuINVLPGB,
 299   /* TLBSYNC instructions required */
 300   CpuTLBSYNC,
 301   /* SNP instructions required */
 302   CpuSNP,
 303   /* RMPQUERY instruction required */
 304   CpuRMPQUERY,
 305
 306   /* NOTE: These items, which can be combined with other ISA flags above, need
 307      to remain second to last and in sync with CPU_FLAGS_COMMON. */
 308
 309   /* i287 support required */
 310   Cpu287,
 311   CpuAttrEnums = Cpu287,
 312   /* i387 support required */
 313   Cpu387,
 314   /* 3dnow! support required */
 315   Cpu3dnow,
 316   /* 3dnow! Extensions support required */
 317   Cpu3dnowA,
 318   /* 64bit support required  */
 319   Cpu64,
 320   /* AVX support required */
 321   CpuAVX,
 322   /* HLE support required */
 323   CpuHLE,
 324   /* Intel AVX-512 Foundation Instructions support required */
 325   CpuAVX512F,
 326   /* Intel AVX-512 VL Instructions support required.  */
 327   CpuAVX512VL,
 328   /* Intel APX_F Instructions support required.  */
 329   CpuAPX_F,
 330   /* Intel AVX10.2 Instructions support required.  */
 331   CpuAVX10_2,
 332   /* Intel AMX-TRANSPOSE Instructions support required.  */
 333   CpuAMX_TRANSPOSE,
 334   /* Not supported in the 64bit mode  */
 335   CpuNo64,
 336
 337   /* NOTE: This item needs to remain last. */
 338
 339   /* The last bitfield in i386_cpu_flags.  */
 340   CpuMax = CpuNo64
 341 };
 342
 343 #define CpuNumOfUints \
 344   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 345 #define CpuNumOfBits \
 346   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 347
 348 #define CpuIsaBits 8
 349 #define CpuAttrNumOfUints \
 350   ((CpuIsaBits + CpuMax - CpuAttrEnums) / sizeof (unsigned int) / CHAR_BIT + 1)
 351 #define CpuAttrNumOfBits \
 352   (CpuAttrNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 353
 354 /* If you get a compiler error for zero width of an unused field,
 355    comment the respective one out.  */
 356 #define CpuUnused       (CpuMax + 1)
 357 #define CpuAttrUnused   (CpuIsaBits + CpuMax + 1 - CpuAttrEnums)
 358
 359 #define CPU_FLAGS_COMMON \
 360       unsigned int cpu287:1, \
 361                    cpu387:1, \
 362                    cpu3dnow:1, \
 363                    cpu3dnowa:1, \
 364                    cpu64:1, \
 365                    cpuavx:1, \
 366                    cpuhle:1, \
 367                    cpuavx512f:1, \
 368                    cpuavx512vl:1, \
 369                    cpuapx_f:1, \
 370                    cpuavx10_2:1, \
 371                    cpuamx_transpose:1, \
 372       /* NOTE: This field needs to remain last. */ \
 373                    cpuno64:1
 374
 375 typedef union i386_cpu_attr
 376 {
 377   struct
 378     {
 379       unsigned int isa:CpuIsaBits;
 380       CPU_FLAGS_COMMON;
 381 #ifdef CpuAttrUnused
 382       unsigned int unused:(CpuAttrNumOfBits - CpuAttrUnused);
 383 #endif
 384     } bitfield;
 385   unsigned int array[CpuAttrNumOfUints];
 386 } i386_cpu_attr;
 387
 388 /* We can check if an instruction is available with array instead
 389    of bitfield. */
 390 typedef union i386_cpu_flags
 391 {
 392   struct
 393     {
 394       unsigned int cpui186:1;
 395       unsigned int cpui286:1;
 396       unsigned int cpui386:1;
 397       unsigned int cpui486:1;
 398       unsigned int cpui586:1;
 399       unsigned int cpui686:1;
 400       unsigned int cpucmov:1;
 401       unsigned int cpufxsr:1;
 402       unsigned int cpuclflush:1;
 403       unsigned int cpunop:1;
 404       unsigned int cpusyscall:1;
 405       unsigned int cpu8087:1;
 406       unsigned int cpu687:1;
 407       unsigned int cpufisttp:1;
 408       unsigned int cpummx:1;
 409       unsigned int cpusse:1;
 410       unsigned int cpusse2:1;
 411       unsigned int cpusse3:1;
 412       unsigned int cpupadlock:1;
 413       unsigned int cpugmi:1;
 414       unsigned int cpusvme:1;
 415       unsigned int cpuvmx:1;
 416       unsigned int cpusmx:1;
 417       unsigned int cpussse3:1;
 418       unsigned int cpusse4a:1;
 419       unsigned int cpulzcnt:1;
 420       unsigned int cpupopcnt:1;
 421       unsigned int cpumonitor:1;
 422       unsigned int cpusse4_1:1;
 423       unsigned int cpusse4_2:1;
 424       unsigned int cpuavx2:1;
 425       unsigned int cpuavx512cd:1;
 426       unsigned int cpuavx512er:1;
 427       unsigned int cpuavx512pf:1;
 428       unsigned int cpuavx512dq:1;
 429       unsigned int cpuavx512bw:1;
 430       unsigned int cpuiamcu:1;
 431       unsigned int cpuxsave:1;
 432       unsigned int cpuxsaveopt:1;
 433       unsigned int cpuaes:1;
 434       unsigned int cpupclmulqdq:1;
 435       unsigned int cpufma:1;
 436       unsigned int cpufma4:1;
 437       unsigned int cpuxop:1;
 438       unsigned int cpulwp:1;
 439       unsigned int cpubmi:1;
 440       unsigned int cputbm:1;
 441       unsigned int cpumovbe:1;
 442       unsigned int cpucx16:1;
 443       unsigned int cpulahf_sahf:1;
 444       unsigned int cpuept:1;
 445       unsigned int cpurdtscp:1;
 446       unsigned int cpufsgsbase:1;
 447       unsigned int cpurdrnd:1;
 448       unsigned int cpuf16c:1;
 449       unsigned int cpubmi2:1;
 450       unsigned int cpurtm:1;
 451       unsigned int cpuinvpcid:1;
 452       unsigned int cpuvmfunc:1;
 453       unsigned int cpumpx:1;
 454       unsigned int cpurdseed:1;
 455       unsigned int cpuadx:1;
 456       unsigned int cpuprfchw:1;
 457       unsigned int cpusmap:1;
 458       unsigned int cpusha:1;
 459       unsigned int cpusha512:1;
 460       unsigned int cpusm3:1;
 461       unsigned int cpusm4:1;
 462       unsigned int cpuclflushopt:1;
 463       unsigned int cpuxsaves:1;
 464       unsigned int cpuxsavec:1;
 465       unsigned int cpuprefetchwt1:1;
 466       unsigned int cpuse1:1;
 467       unsigned int cpuclwb:1;
 468       unsigned int cpuavx512ifma:1;
 469       unsigned int cpuavx512vbmi:1;
 470       unsigned int cpuavx512_4fmaps:1;
 471       unsigned int cpuavx512_4vnniw:1;
 472       unsigned int cpuavx512_vpopcntdq:1;
 473       unsigned int cpuavx512_vbmi2:1;
 474       unsigned int cpuavx512_vnni:1;
 475       unsigned int cpuavx512_bitalg:1;
 476       unsigned int cpuavx512_bf16:1;
 477       unsigned int cpuavx512_vp2intersect:1;
 478       unsigned int cputdx:1;
 479       unsigned int cpuavx_vnni:1;
 480       unsigned int cpuavx512_fp16:1;
 481       unsigned int cpuprefetchi:1;
 482       unsigned int cpuavx_ifma:1;
 483       unsigned int cpuavx_vnni_int8:1;
 484       unsigned int cpuavx_vnni_int16:1;
 485       unsigned int cpucmpccxadd:1;
 486       unsigned int cpuwrmsrns:1;
 487       unsigned int cpumsrlist:1;
 488       unsigned int cpuavx_ne_convert:1;
 489       unsigned int cpurao_int:1;
 490       unsigned int cpufred:1;
 491       unsigned int cpulkgs:1;
 492       unsigned int cpuuser_msr:1;
 493       unsigned int cpumsr_imm:1;
 494       unsigned int cpumwaitx:1;
 495       unsigned int cpuclzero:1;
 496       unsigned int cpuospke:1;
 497       unsigned int cpurdpid:1;
 498       unsigned int cpuptwrite:1;
 499       unsigned int cpuibt:1;
 500       unsigned int cpushstk:1;
 501       unsigned int cpuamx_int8:1;
 502       unsigned int cpuamx_bf16:1;
 503       unsigned int cpuamx_fp16:1;
 504       unsigned int cpuamx_complex:1;
 505       unsigned int cpuamx_tf32:1;
 506       unsigned int cpuamx_tile:1;
 507       unsigned int cpugfni:1;
 508       unsigned int cpuvaes:1;
 509       unsigned int cpuvpclmulqdq:1;
 510       unsigned int cpuwbnoinvd:1;
 511       unsigned int cpupconfig:1;
 512       unsigned int cpupbndkb:1;
 513       unsigned int cpuwaitpkg:1;
 514       unsigned int cpuuintr:1;
 515       unsigned int cpucldemote:1;
 516       unsigned int cpumovdiri:1;
 517       unsigned int cpumovdir64b:1;
 518       unsigned int cpuenqcmd:1;
 519       unsigned int cpuserialize:1;
 520       unsigned int cpurdpru:1;
 521       unsigned int cpumcommit:1;
 522       unsigned int cpusev_es:1;
 523       unsigned int cputsxldtrk:1;
 524       unsigned int cpukl:1;
 525       unsigned int cpuwidekl:1;
 526       unsigned int cpuhreset:1;
 527       unsigned int cpuinvlpgb:1;
 528       unsigned int cputlbsync:1;
 529       unsigned int cpusnp:1;
 530       unsigned int cpurmpquery:1;
 531       CPU_FLAGS_COMMON;
 532 #ifdef CpuUnused
 533       unsigned int unused:(CpuNumOfBits - CpuUnused);
 534 #endif
 535     } bitfield;
 536   unsigned int array[CpuNumOfUints];
 537 } i386_cpu_flags;
 538
 539 /* Position of opcode_modifier bits.  */
 540
 541 enum
 542 {
 543   /* has direction bit. */
 544   D = 0,
 545   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 546      canonical way; the base_opcode field should hold the encoding for byte
 547      operands  */
 548   W,
 549   /* load form instruction. Must be placed before store form.  */
 550   Load,
 551   /* insn has a modrm byte. */
 552   Modrm,
 553   /* special case for jump insns; value has to be 1 */
 554 #define JUMP 1
 555   /* call and jump */
 556 #define JUMP_DWORD 2
 557   /* loop and jecxz */
 558 #define JUMP_BYTE 3
 559   /* special case for intersegment leaps/calls */
 560 #define JUMP_INTERSEGMENT 4
 561   /* absolute address for jump */
 562 #define JUMP_ABSOLUTE 5
 563   Jump,
 564   /* FP insn memory format bit, sized by 0x4 */
 565   FloatMF,
 566   /* needs size prefix if in 32-bit mode */
 567 #define SIZE16 1
 568   /* needs size prefix if in 16-bit mode */
 569 #define SIZE32 2
 570   /* needs size prefix if in 64-bit mode */
 571 #define SIZE64 3
 572   Size,
 573   /* Check that operand sizes match.  */
 574   CheckOperandSize,
 575   /* any memory size */
 576 #define ANY_SIZE 1
 577   /* fake an extra reg operand for clr, imul and special register
 578      processing for some instructions.  */
 579 #define REG_KLUDGE 2
 580   /* deprecated fp insn, gets a warning */
 581 #define UGH 3
 582   /* An implicit xmm0 as the first operand */
 583 #define IMPLICIT_1ST_XMM0 4
 584   /* One of the operands denotes a sequence of registers, with insn-dependent
 585      constraint on the first register number.  It implicitly denotes e.g. the
 586      register group of {x,y,z}mmN - {x,y,z}mm(N + 3), in which case N ought to
 587      be a multiple of 4.
 588    */
 589 #define IMPLICIT_GROUP 5
 590   /* Default mask isn't allowed.  */
 591 #define NO_DEFAULT_MASK 6
 592   /* Address prefix changes register operand */
 593 #define ADDR_PREFIX_OP_REG 7
 594   /* Instrucion requires that destination must be distinct from source
 595      registers.  */
 596 #define DISTINCT_DEST 8
 597   /* Instruction updates stack pointer implicitly.  */
 598 #define IMPLICIT_STACK_OP 9
 599   /* Instruction zeroes upper part of register.  */
 600 #define ZERO_UPPER 10
 601   /* Instruction support SCC.  */
 602 #define SCC 11
 603   /* Instruction requires EVEX.NF to be 1.  */
 604 #define EVEX_NF 12
 605   OperandConstraint,
 606   /* instruction ignores operand size prefix and in Intel mode ignores
 607      mnemonic size suffix check.  */
 608 #define IGNORESIZE      1
 609   /* default insn size depends on mode */
 610 #define DEFAULTSIZE     2
 611   MnemonicSize,
 612   /* b suffix on instruction illegal */
 613   No_bSuf,
 614   /* w suffix on instruction illegal */
 615   No_wSuf,
 616   /* l suffix on instruction illegal */
 617   No_lSuf,
 618   /* s suffix on instruction illegal */
 619   No_sSuf,
 620   /* q suffix on instruction illegal */
 621   No_qSuf,
 622   /* instruction needs FWAIT */
 623   FWait,
 624   /* IsString provides for a quick test for string instructions, and
 625      its actual value also indicates which of the operands (if any)
 626      requires use of the %es segment.  */
 627 #define IS_STRING_ES_OP0 2
 628 #define IS_STRING_ES_OP1 3
 629   IsString,
 630   /* RegMem is for instructions with a modrm byte where the register
 631      destination operand should be encoded in the mod and regmem fields.
 632      Normally, it will be encoded in the reg field. We add a RegMem
 633      flag to indicate that it should be encoded in the regmem field.  */
 634   RegMem,
 635   /* quick test if branch instruction is MPX supported */
 636   BNDPrefixOk,
 637 #define PrefixNone              0
 638 #define PrefixRep               1
 639 #define PrefixHLERelease        2 /* Okay with an XRELEASE (0xf3) prefix. */
 640 #define PrefixNoTrack           3
 641   /* Prefixes implying "LOCK okay" must come after Lock. All others have
 642      to come before.  */
 643 #define PrefixLock              4
 644 #define PrefixHLELock           5 /* Okay with a LOCK prefix.  */
 645 #define PrefixHLEAny            6 /* Okay with or without a LOCK prefix.  */
 646   PrefixOk,
 647   /* opcode is a prefix */
 648   IsPrefix,
 649   /* instruction has extension in 8 bit imm */
 650   ImmExt,
 651   /* instruction don't need Rex64 prefix.  */
 652   NoRex64,
 653   /* insn has VEX prefix:
 654         1: 128bit VEX prefix (or operand dependent).
 655         2: 256bit VEX prefix.
 656         3: Scalar VEX prefix.
 657    */
 658 #define VEX128          1
 659 #define VEX256          2
 660 #define VEXScalar       3
 661   Vex,
 662   /* How to encode VEX.vvvv:
 663      1: VEX.vvvv encodes the src1 register operand.
 664      2: VEX.vvvv encodes the src2 register operand.
 665      3: VEX.vvvv encodes the dest register operand.
 666    */
 667 #define VexVVVV_SRC1   1
 668 #define VexVVVV_SRC2   2
 669 #define VexVVVV_DST    3
 670
 671   VexVVVV,
 672   /* How the VEX.W bit is used:
 673      0: Set by the REX.W bit.
 674      1: VEX.W0.  Should always be 0.
 675      2: VEX.W1.  Should always be 1.
 676      3: VEX.WIG. The VEX.W bit is ignored.
 677    */
 678 #define VEXW0   1
 679 #define VEXW1   2
 680 #define VEXWIG  3
 681   VexW,
 682   /* Opcode prefix (values chosen to be usable directly in
 683      VEX/XOP/EVEX pp fields):
 684      0: None
 685      1: Add 0x66 opcode prefix.
 686      2: Add 0xf3 opcode prefix.
 687      3: Add 0xf2 opcode prefix.
 688    */
 689 #define PREFIX_NONE     0
 690 #define PREFIX_0X66     1
 691 #define PREFIX_0XF3     2
 692 #define PREFIX_0XF2     3
 693   OpcodePrefix,
 694   /* Instruction with a mandatory SIB byte:
 695         1: 128bit vector register.
 696         2: 256bit vector register.
 697         3: 512bit vector register.
 698    */
 699 #define VECSIB128       1
 700 #define VECSIB256       2
 701 #define VECSIB512       3
 702 #define SIBMEM          4
 703   SIB,
 704
 705   /* SSE to AVX support required */
 706   SSE2AVX,
 707
 708   /* insn has EVEX prefix:
 709         1: 512bit EVEX prefix.
 710         2: 128bit EVEX prefix.
 711         3: 256bit EVEX prefix.
 712         4: Length-ignored (LIG) EVEX prefix.
 713         5: Length determined from actual operands.
 714         6: L'L = 3 (reserved, .insn only)
 715    */
 716 #define EVEX512                1
 717 #define EVEX128                2
 718 #define EVEX256                3
 719 #define EVEXLIG                4
 720 #define EVEXDYN                5
 721 #define EVEX_L3                6
 722   EVex,
 723
 724   /* AVX512 masking support */
 725   Masking,
 726
 727   /* AVX512 broadcast support.  The number of bytes to broadcast is
 728      1 << (Broadcast - 1):
 729         1: Byte broadcast.
 730         2: Word broadcast.
 731         3: Dword broadcast.
 732         4: Qword broadcast.
 733    */
 734 #define BYTE_BROADCAST  1
 735 #define WORD_BROADCAST  2
 736 #define DWORD_BROADCAST 3
 737 #define QWORD_BROADCAST 4
 738   Broadcast,
 739
 740   /* Static rounding control is supported.  */
 741   StaticRounding,
 742
 743   /* Supress All Exceptions is supported.  */
 744   SAE,
 745
 746   /* Compressed Disp8*N attribute.  */
 747 #define DISP8_SHIFT_VL 7
 748   Disp8MemShift,
 749
 750   /* Support encoding optimization.  */
 751   Optimize,
 752
 753   /* Language dialect.  NOTE: Order matters!  */
 754 #define INTEL_SYNTAX 1
 755 #define ATT_SYNTAX   2
 756 #define ATT_MNEMONIC 3
 757   Dialect,
 758
 759   /* Mnemonic suffix permitted in Intel syntax.  */
 760   IntelSuffix,
 761
 762   /* ISA64: Don't change the order without other code adjustments.
 763         0: Common to AMD64 and Intel64.
 764         1: AMD64.
 765         2: Intel64.
 766         3: Only in Intel64.
 767    */
 768 #define AMD64           1
 769 #define INTEL64         2
 770 #define INTEL64ONLY     3
 771   ISA64,
 772
 773   /* egprs (r16-r31) on instruction illegal. We also use it to judge
 774      whether the instruction supports pseudo-prefix {rex2}.  */
 775   NoEgpr,
 776
 777   /* No CSPAZO flags update indication.  */
 778   NF,
 779
 780   /* Instrucion requires REX2 prefix.  */
 781   Rex2,
 782
 783   /* The last bitfield in i386_opcode_modifier.  */
 784   Opcode_Modifier_Num
 785 };
 786
 787 typedef struct i386_opcode_modifier
 788 {
 789   unsigned int d:1;
 790   unsigned int w:1;
 791   unsigned int load:1;
 792   unsigned int modrm:1;
 793   unsigned int jump:3;
 794   unsigned int floatmf:1;
 795   unsigned int size:2;
 796   unsigned int checkoperandsize:1;
 797   unsigned int operandconstraint:4;
 798   unsigned int mnemonicsize:2;
 799   unsigned int no_bsuf:1;
 800   unsigned int no_wsuf:1;
 801   unsigned int no_lsuf:1;
 802   unsigned int no_ssuf:1;
 803   unsigned int no_qsuf:1;
 804   unsigned int fwait:1;
 805   unsigned int isstring:2;
 806   unsigned int regmem:1;
 807   unsigned int bndprefixok:1;
 808   unsigned int prefixok:3;
 809   unsigned int isprefix:1;
 810   unsigned int immext:1;
 811   unsigned int norex64:1;
 812   unsigned int vex:2;
 813   unsigned int vexvvvv:2;
 814   unsigned int vexw:2;
 815   unsigned int opcodeprefix:2;
 816   unsigned int sib:3;
 817   unsigned int sse2avx:1;
 818   unsigned int evex:3;
 819   unsigned int masking:1;
 820   unsigned int broadcast:3;
 821   unsigned int staticrounding:1;
 822   unsigned int sae:1;
 823   unsigned int disp8memshift:3;
 824   unsigned int optimize:1;
 825   unsigned int dialect:2;
 826   unsigned int intelsuffix:1;
 827   unsigned int isa64:2;
 828   unsigned int noegpr:1;
 829   unsigned int nf:1;
 830   unsigned int rex2:1;
 831 } i386_opcode_modifier;
 832
 833 /* Operand classes.  */
 834
 835 #define CLASS_WIDTH 4
 836 enum operand_class
 837 {
 838   ClassNone,
 839   Reg, /* GPRs and FP regs, distinguished by operand size */
 840   SReg, /* Segment register */
 841   RegCR, /* Control register */
 842   RegDR, /* Debug register */
 843   RegTR, /* Test register */
 844   RegMMX, /* MMX register */
 845   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 846   RegMask, /* Vector Mask register */
 847   RegBND, /* Bound register */
 848 };
 849
 850 /* Special operand instances.  */
 851
 852 #define INSTANCE_WIDTH 3
 853 enum operand_instance
 854 {
 855   InstanceNone,
 856   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 857   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 858   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 859   RegB,  /* %bl / %bx / %ebx / %rbx */
 860 };
 861
 862 /* Position of operand_type bits.  */
 863
 864 enum
 865 {
 866   /* Class and Instance */
 867   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 868   /* 1 bit immediate */
 869   Imm1,
 870   /* 8 bit immediate */
 871   Imm8,
 872   /* 8 bit immediate sign extended */
 873   Imm8S,
 874   /* 16 bit immediate */
 875   Imm16,
 876   /* 32 bit immediate */
 877   Imm32,
 878   /* 32 bit immediate sign extended */
 879   Imm32S,
 880   /* 64 bit immediate */
 881   Imm64,
 882   /* 8bit/16bit/32bit displacements are used in different ways,
 883      depending on the instruction.  For jumps, they specify the
 884      size of the PC relative displacement, for instructions with
 885      memory operand, they specify the size of the offset relative
 886      to the base register, and for instructions with memory offset
 887      such as `mov 1234,%al' they specify the size of the offset
 888      relative to the segment base.  */
 889   /* 8 bit displacement */
 890   Disp8,
 891   /* 16 bit displacement */
 892   Disp16,
 893   /* 32 bit displacement (64-bit: sign-extended) */
 894   Disp32,
 895   /* 64 bit displacement */
 896   Disp64,
 897   /* Register which can be used for base or index in memory operand.  */
 898   BaseIndex,
 899   /* BYTE size. */
 900   Byte,
 901   /* WORD size. 2 byte */
 902   Word,
 903   /* DWORD size. 4 byte */
 904   Dword,
 905   /* FWORD size. 6 byte */
 906   Fword,
 907   /* QWORD size. 8 byte */
 908   Qword,
 909   /* TBYTE size. 10 byte */
 910   Tbyte,
 911   /* XMMWORD size. */
 912   Xmmword,
 913   /* YMMWORD size. */
 914   Ymmword,
 915   /* ZMMWORD size.  */
 916   Zmmword,
 917   /* TMMWORD size.  */
 918   Tmmword,
 919   /* Unspecified memory size.  */
 920   Unspecified,
 921
 922   /* The number of bits in i386_operand_type.  */
 923   OTNum
 924 };
 925
 926 #define OTNumOfUints \
 927   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 928 #define OTNumOfBits \
 929   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 930
 931 /* If you get a compiler error for zero width of the unused field,
 932    comment it out.  */
 933 #define OTUnused                OTNum
 934
 935 typedef union i386_operand_type
 936 {
 937   struct
 938     {
 939       unsigned int class:CLASS_WIDTH;
 940       unsigned int instance:INSTANCE_WIDTH;
 941       unsigned int imm1:1;
 942       unsigned int imm8:1;
 943       unsigned int imm8s:1;
 944       unsigned int imm16:1;
 945       unsigned int imm32:1;
 946       unsigned int imm32s:1;
 947       unsigned int imm64:1;
 948       unsigned int disp8:1;
 949       unsigned int disp16:1;
 950       unsigned int disp32:1;
 951       unsigned int disp64:1;
 952       unsigned int baseindex:1;
 953       unsigned int byte:1;
 954       unsigned int word:1;
 955       unsigned int dword:1;
 956       unsigned int fword:1;
 957       unsigned int qword:1;
 958       unsigned int tbyte:1;
 959       unsigned int xmmword:1;
 960       unsigned int ymmword:1;
 961       unsigned int zmmword:1;
 962       unsigned int tmmword:1;
 963       unsigned int unspecified:1;
 964 #ifdef OTUnused
 965       unsigned int unused:(OTNumOfBits - OTUnused);
 966 #endif
 967     } bitfield;
 968   unsigned int array[OTNumOfUints];
 969 } i386_operand_type;
 970
 971 typedef struct insn_template
 972 {
 973   /* instruction name sans width suffix ("mov" for movl insns) */
 974   unsigned int mnem_off;
 975
 976   /* Bitfield arrangement is such that individual fields can be easily
 977      extracted (in native builds at least) - either by at most a masking
 978      operation (base_opcode, operands), or by just a (signed) right shift
 979      (extension_opcode).  Please try to maintain this property.  */
 980
 981   /* base_opcode is the fundamental opcode byte without optional
 982      prefix(es).  */
 983   unsigned int base_opcode:16;
 984 #define Opcode_D        0x2 /* Direction bit:
 985                                set if Reg --> Regmem;
 986                                unset if Regmem --> Reg. */
 987 #define Opcode_FloatR   0x8 /* ModR/M bit to swap src/dest for float insns. */
 988 #define Opcode_FloatD   0x4 /* Direction bit for float insns. */
 989 #define Opcode_ExtD     0x1 /* Direction bit for extended opcode space insns. */
 990 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 991 /* The next value is arbitrary, as long as it's non-zero and distinct
 992    from all other values above.  */
 993 #define Opcode_VexW     0xf /* Operand order controlled by VEX.W. */
 994
 995   /* how many operands */
 996   unsigned int operands:3;
 997
 998   /* opcode space */
 999   unsigned int opcode_space:4;
1000   /* Opcode encoding space (values chosen to be usable directly in
1001      VEX/XOP mmmmm and EVEX mmm fields):
1002      0: Base opcode space.
1003      1: 0F opcode prefix / space.
1004      2: 0F38 opcode prefix / space.
1005      3: 0F3A opcode prefix / space.
1006      4: MAP4 opcode prefix / space.
1007      5: MAP5 opcode prefix / space.
1008      6: MAP6 opcode prefix / space.
1009      7: MAP7 opcode prefix / space.
1010      8: XOP 08 opcode space.
1011      9: XOP 09 opcode space.
1012      A: XOP 0A opcode space.
1013    */
1014 #define SPACE_BASE      0
1015 #define SPACE_0F        1
1016 #define SPACE_0F38      2
1017 #define SPACE_0F3A      3
1018 #define SPACE_MAP4      4
1019 #define SPACE_MAP5      5
1020 #define SPACE_MAP6      6
1021 #define SPACE_MAP7      7
1022 #define SPACE_XOP08     8
1023 #define SPACE_XOP09     9
1024 #define SPACE_XOP0A     0xA
1025
1026 /* (Fake) base opcode value for pseudo prefixes.  */
1027 #define PSEUDO_PREFIX 0
1028
1029   /* extension_opcode is the 3 bit extension for group <n> insns.
1030      This field is also used to store the 8-bit opcode suffix for the
1031      AMD 3DNow! instructions.
1032      If this template has no extension opcode (the usual case) use None
1033      Instructions */
1034   signed int extension_opcode:9;
1035 #define None (-1)               /* If no extension_opcode is possible.  */
1036
1037 /* Pseudo prefixes.  */
1038 #define Prefix_Disp8            0       /* {disp8} */
1039 #define Prefix_Disp16           1       /* {disp16} */
1040 #define Prefix_Disp32           2       /* {disp32} */
1041 #define Prefix_Load             3       /* {load} */
1042 #define Prefix_Store            4       /* {store} */
1043 #define Prefix_VEX              5       /* {vex} */
1044 #define Prefix_VEX3             6       /* {vex3} */
1045 #define Prefix_EVEX             7       /* {evex} */
1046 #define Prefix_REX              8       /* {rex} */
1047 #define Prefix_REX2             9       /* {rex2} */
1048 #define Prefix_NoOptimize       10      /* {nooptimize} */
1049 #define Prefix_NF               11      /* {nf} */
1050
1051   /* the bits in opcode_modifier are used to generate the final opcode from
1052      the base_opcode.  These bits also are used to detect alternate forms of
1053      the same instruction */
1054   i386_opcode_modifier opcode_modifier;
1055
1056   /* cpu feature attributes */
1057   i386_cpu_attr cpu, cpu_any;
1058
1059   /* operand_types[i] describes the type of operand i.  This is made
1060      by OR'ing together all of the possible type masks.  (e.g.
1061      'operand_types[i] = Reg|Imm' specifies that operand i can be
1062      either a register or an immediate operand.  */
1063   i386_operand_type operand_types[MAX_OPERANDS];
1064 }
1065 insn_template;
1066
1067 /* these are for register name --> number & type hash lookup */
1068 typedef struct
1069 {
1070   char reg_name[8];
1071   i386_operand_type reg_type;
1072   unsigned char reg_flags;
1073 #define RegRex      0x1  /* Extended register.  */
1074 #define RegRex64    0x2  /* Extended 8 bit register.  */
1075 #define RegVRex     0x4  /* Extended vector register.  */
1076 #define RegRex2     0x8  /* Extended GPRs R16–R31 register.  */
1077   unsigned char reg_num;
1078 #define RegIP   ((unsigned char ) ~0)
1079 /* EIZ and RIZ are fake index registers.  */
1080 #define RegIZ   (RegIP - 1)
1081 /* FLAT is a fake segment register (Intel mode).  */
1082 #define RegFlat     ((unsigned char) ~0)
1083   unsigned char dw2_regnum[2];
1084 #define Dw2Inval 0xff
1085 }
1086 reg_entry;