1 /* spu.c -- Assembler for the IBM Synergistic Processing Unit (SPU)
3 Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
25 #include "dwarf2dbg.h"
27 const struct spu_opcode spu_opcodes
[] = {
28 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
29 { MACFORMAT, (OPCODE) << (32-11), MNEMONIC, ASMFORMAT },
30 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
31 { MACFORMAT, ((OPCODE) << (32-11)) | ((FB) << (32-18)), MNEMONIC, ASMFORMAT },
32 #include "opcode/spu-insns.h"
37 static const int spu_num_opcodes
=
38 sizeof (spu_opcodes
) / sizeof (spu_opcodes
[0]);
45 expressionS exp
[MAX_RELOCS
];
46 int reloc_arg
[MAX_RELOCS
];
47 bfd_reloc_code_real_type reloc
[MAX_RELOCS
];
51 static const char *get_imm (const char *param
, struct spu_insn
*insn
, int arg
);
52 static const char *get_reg (const char *param
, struct spu_insn
*insn
, int arg
,
54 static int calcop (struct spu_opcode
*format
, const char *param
,
55 struct spu_insn
*insn
);
56 static void spu_brinfo (int);
57 static void spu_cons (int);
60 static struct hash_control
*op_hash
= NULL
;
62 /* These bits should be turned off in the first address of every segment */
65 /* These chars start a comment anywhere in a source file (except inside
67 const char comment_chars
[] = "#";
69 /* These chars only start a comment at the beginning of a line. */
70 const char line_comment_chars
[] = "#";
72 /* gods own line continuation char */
73 const char line_separator_chars
[] = ";";
75 /* Chars that can be used to separate mant from exp in floating point nums */
76 const char EXP_CHARS
[] = "eE";
78 /* Chars that mean this number is a floating point constant */
80 /* or 0H1.234E-12 (see exp chars above) */
81 const char FLT_CHARS
[] = "dDfF";
83 const pseudo_typeS md_pseudo_table
[] =
85 {"align", s_align_ptwo
, 4},
86 {"brinfo", spu_brinfo
, 0},
87 {"bss", s_lcomm_bytes
, 1},
89 {"dfloat", float_cons
, 'd'},
90 {"ffloat", float_cons
, 'f'},
91 {"global", s_globl
, 0},
94 {"long", spu_cons
, 4},
95 {"quad", spu_cons
, 8},
96 {"string", stringer
, 8 + 1},
97 {"word", spu_cons
, 4},
98 /* Force set to be treated as an instruction. */
101 /* Likewise for eqv. */
104 {"file", (void (*) (int)) dwarf2_directive_file
, 0 },
105 {"loc", dwarf2_directive_loc
, 0},
109 /* Bits plugged into branch instruction offset field. */
115 const char *retval
= NULL
;
118 /* initialize hash table */
120 op_hash
= hash_new ();
122 /* loop until you see the end of the list */
124 for (i
= 0; i
< spu_num_opcodes
; i
++)
126 /* hash each mnemonic and record its position */
128 retval
= hash_insert (op_hash
, spu_opcodes
[i
].mnemonic
,
129 (void *) &spu_opcodes
[i
]);
131 if (retval
!= NULL
&& strcmp (retval
, "exists") != 0)
132 as_fatal (_("Can't hash instruction '%s':%s"),
133 spu_opcodes
[i
].mnemonic
, retval
);
137 const char *md_shortopts
= "";
138 struct option md_longopts
[] = {
139 #define OPTION_APUASM (OPTION_MD_BASE)
140 {"apuasm", no_argument
, NULL
, OPTION_APUASM
},
141 #define OPTION_DD2 (OPTION_MD_BASE+1)
142 {"mdd2.0", no_argument
, NULL
, OPTION_DD2
},
143 #define OPTION_DD1 (OPTION_MD_BASE+2)
144 {"mdd1.0", no_argument
, NULL
, OPTION_DD1
},
145 #define OPTION_DD3 (OPTION_MD_BASE+3)
146 {"mdd3.0", no_argument
, NULL
, OPTION_DD3
},
147 { NULL
, no_argument
, NULL
, 0 }
149 size_t md_longopts_size
= sizeof (md_longopts
);
151 /* When set (by -apuasm) our assembler emulates the behaviour of apuasm.
152 * e.g. don't add bias to float conversion and don't right shift
153 * immediate values. */
154 static int emulate_apuasm
;
156 /* Use the dd2.0 instructions set. The only differences are some new
157 * register names and the orx insn */
158 static int use_dd2
= 1;
161 md_parse_option (int c
, char *arg ATTRIBUTE_UNUSED
)
184 md_show_usage (FILE *stream
)
188 --apuasm emulate behaviour of apuasm\n"),
199 bfd_reloc_code_real_type reloc
;
202 static struct arg_encode arg_encode
[A_MAX
] = {
203 { 7, 0, 0, 0, 127, 0, -1, 0 }, /* A_T */
204 { 7, 7, 0, 0, 127, 0, -1, 0 }, /* A_A */
205 { 7, 14, 0, 0, 127, 0, -1, 0 }, /* A_B */
206 { 7, 21, 0, 0, 127, 0, -1, 0 }, /* A_C */
207 { 7, 7, 0, 0, 127, 0, -1, 0 }, /* A_S */
208 { 7, 7, 0, 0, 127, 0, -1, 0 }, /* A_H */
209 { 0, 0, 0, 0, -1, 0, -1, 0 }, /* A_P */
210 { 7, 14, 0, 0, -1, 0, -1, BFD_RELOC_SPU_IMM7
}, /* A_S3 */
211 { 7, 14, 0, -32, 31, -31, 0, BFD_RELOC_SPU_IMM7
}, /* A_S6 */
212 { 7, 14, 0, 0, -1, 0, -1, BFD_RELOC_SPU_IMM7
}, /* A_S7N */
213 { 7, 14, 0, -64, 63, -63, 0, BFD_RELOC_SPU_IMM7
}, /* A_S7 */
214 { 8, 14, 0, 0, 127, 0, -1, BFD_RELOC_SPU_IMM8
}, /* A_U7A */
215 { 8, 14, 0, 0, 127, 0, -1, BFD_RELOC_SPU_IMM8
}, /* A_U7B */
216 { 10, 14, 0, -512, 511, -128, 255, BFD_RELOC_SPU_IMM10
}, /* A_S10B */
217 { 10, 14, 0, -512, 511, 0, -1, BFD_RELOC_SPU_IMM10
}, /* A_S10 */
218 { 2, 23, 9, -1024, 1023, 0, -1, BFD_RELOC_SPU_PCREL9a
}, /* A_S11 */
219 { 2, 14, 9, -1024, 1023, 0, -1, BFD_RELOC_SPU_PCREL9b
}, /* A_S11I */
220 { 10, 14, 4, -8192, 8191, 0, -1, BFD_RELOC_SPU_IMM10W
}, /* A_S14 */
221 { 16, 7, 0, -32768, 32767, 0, -1, BFD_RELOC_SPU_IMM16
}, /* A_S16 */
222 { 16, 7, 2, -131072, 262143, 0, -1, BFD_RELOC_SPU_IMM16W
}, /* A_S18 */
223 { 16, 7, 2, -262144, 262143, 0, -1, BFD_RELOC_SPU_PCREL16
}, /* A_R18 */
224 { 7, 14, 0, 0, -1, 0, -1, BFD_RELOC_SPU_IMM7
}, /* A_U3 */
225 { 7, 14, 0, 0, 127, 0, 31, BFD_RELOC_SPU_IMM7
}, /* A_U5 */
226 { 7, 14, 0, 0, 127, 0, 63, BFD_RELOC_SPU_IMM7
}, /* A_U6 */
227 { 7, 14, 0, 0, -1, 0, -1, BFD_RELOC_SPU_IMM7
}, /* A_U7 */
228 { 14, 0, 0, 0, 16383, 0, -1, 0 }, /* A_U14 */
229 { 16, 7, 0, -32768, 65535, 0, -1, BFD_RELOC_SPU_IMM16
}, /* A_X16 */
230 { 18, 7, 0, 0, 262143, 0, -1, BFD_RELOC_SPU_IMM18
}, /* A_U18 */
233 /* Some flags for handling errors. This is very hackish and added after
235 static int syntax_error_arg
;
236 static const char *syntax_error_param
;
237 static int syntax_reg
;
240 insn_fmt_string (struct spu_opcode
*format
)
246 len
+= sprintf (&buf
[len
], "%s\t", format
->mnemonic
);
247 for (i
= 1; i
<= format
->arg
[0]; i
++)
249 int arg
= format
->arg
[i
];
251 if (i
> 1 && arg
!= A_P
&& format
->arg
[i
-1] != A_P
)
256 exp
= i
== syntax_error_arg
? "REG" : "reg";
258 exp
= i
== syntax_error_arg
? "IMM" : "imm";
259 len
+= sprintf (&buf
[len
], "%s", exp
);
260 if (i
> 1 && format
->arg
[i
-1] == A_P
)
268 md_assemble (char *op
)
270 char *param
, *thisfrag
;
272 struct spu_opcode
*format
;
273 struct spu_insn insn
;
278 /* skip over instruction to find parameters */
280 for (param
= op
; *param
!= 0 && !ISSPACE (*param
); param
++)
285 if (c
!= 0 && c
!= '\n')
288 /* try to find the instruction in the hash table */
290 if ((format
= (struct spu_opcode
*) hash_find (op_hash
, op
)) == NULL
)
292 as_bad (_("Invalid mnemonic '%s'"), op
);
296 if (!use_dd2
&& strcmp (format
->mnemonic
, "orx") == 0)
298 as_bad (_("'%s' is only available in DD2.0 or higher."), op
);
304 /* try parsing this instruction into insn */
305 for (i
= 0; i
< MAX_RELOCS
; i
++)
307 insn
.exp
[i
].X_add_symbol
= 0;
308 insn
.exp
[i
].X_op_symbol
= 0;
309 insn
.exp
[i
].X_add_number
= 0;
310 insn
.exp
[i
].X_op
= O_illegal
;
311 insn
.reloc_arg
[i
] = -1;
312 insn
.reloc
[i
] = BFD_RELOC_NONE
;
314 insn
.opcode
= format
->opcode
;
315 insn
.tag
= (enum spu_insns
) (format
- spu_opcodes
);
317 syntax_error_arg
= 0;
318 syntax_error_param
= 0;
320 if (calcop (format
, param
, &insn
))
323 /* if it doesn't parse try the next instruction */
324 if (!strcmp (format
[0].mnemonic
, format
[1].mnemonic
))
328 int parg
= format
[0].arg
[syntax_error_arg
-1];
330 as_fatal (_("Error in argument %d. Expecting: \"%s\""),
331 syntax_error_arg
- (parg
== A_P
),
332 insn_fmt_string (format
));
338 && ! (insn
.tag
== M_RDCH
339 || insn
.tag
== M_RCHCNT
340 || insn
.tag
== M_WRCH
))
341 as_warn (_("Mixing register syntax, with and without '$'."));
342 if (syntax_error_param
)
344 const char *d
= syntax_error_param
;
347 as_warn (_("Treating '%-*s' as a symbol."), (int)(syntax_error_param
- d
), d
);
351 && (insn
.tag
<= M_BRASL
352 || (insn
.tag
>= M_BRZ
&& insn
.tag
<= M_BRHNZ
))
353 && (insn
.opcode
& 0x7ff80) == 0
354 && (insn
.reloc_arg
[0] == A_R18
355 || insn
.reloc_arg
[0] == A_S18
356 || insn
.reloc_arg
[1] == A_R18
357 || insn
.reloc_arg
[1] == A_S18
))
358 insn
.opcode
|= brinfo
<< 7;
360 /* grow the current frag and plop in the opcode */
362 thisfrag
= frag_more (4);
363 md_number_to_chars (thisfrag
, insn
.opcode
, 4);
365 /* if this instruction requires labels mark it for later */
367 for (i
= 0; i
< MAX_RELOCS
; i
++)
368 if (insn
.reloc_arg
[i
] >= 0)
371 bfd_reloc_code_real_type reloc
= insn
.reloc
[i
];
374 if (reloc
== BFD_RELOC_SPU_PCREL9a
375 || reloc
== BFD_RELOC_SPU_PCREL9b
376 || reloc
== BFD_RELOC_SPU_PCREL16
)
378 fixP
= fix_new_exp (frag_now
,
379 thisfrag
- frag_now
->fr_literal
,
384 fixP
->tc_fix_data
.arg_format
= insn
.reloc_arg
[i
];
385 fixP
->tc_fix_data
.insn_tag
= insn
.tag
;
387 dwarf2_emit_insn (4);
389 /* .brinfo lasts exactly one instruction. */
394 calcop (struct spu_opcode
*format
, const char *param
, struct spu_insn
*insn
)
400 for (i
= 1; i
<= format
->arg
[0]; i
++)
402 arg
= format
->arg
[i
];
403 syntax_error_arg
= i
;
405 while (ISSPACE (*param
))
407 if (*param
== 0 || *param
== ',')
410 param
= get_reg (param
, insn
, arg
, 1);
412 param
= get_imm (param
, insn
, arg
);
423 while (ISSPACE (*param
))
426 if (arg
!= A_P
&& paren
)
432 else if (i
< format
->arg
[0]
433 && format
->arg
[i
] != A_P
434 && format
->arg
[i
+1] != A_P
)
443 while (ISSPACE (*param
))
445 return !paren
&& (*param
== 0 || *param
== '\n');
454 #define REG_NAME(NO,NM) { NO, sizeof (NM) - 1, NM }
456 static struct reg_name reg_name
[] = {
457 REG_NAME (0, "lr"), /* link register */
458 REG_NAME (1, "sp"), /* stack pointer */
459 REG_NAME (0, "rp"), /* link register */
460 REG_NAME (127, "fp"), /* frame pointer */
463 static struct reg_name sp_reg_name
[] = {
466 static struct reg_name ch_reg_name
[] = {
467 REG_NAME ( 0, "SPU_RdEventStat"),
468 REG_NAME ( 1, "SPU_WrEventMask"),
469 REG_NAME ( 2, "SPU_WrEventAck"),
470 REG_NAME ( 3, "SPU_RdSigNotify1"),
471 REG_NAME ( 4, "SPU_RdSigNotify2"),
472 REG_NAME ( 7, "SPU_WrDec"),
473 REG_NAME ( 8, "SPU_RdDec"),
474 REG_NAME ( 11, "SPU_RdEventMask"), /* DD2.0 only */
475 REG_NAME ( 13, "SPU_RdMachStat"),
476 REG_NAME ( 14, "SPU_WrSRR0"),
477 REG_NAME ( 15, "SPU_RdSRR0"),
478 REG_NAME ( 28, "SPU_WrOutMbox"),
479 REG_NAME ( 29, "SPU_RdInMbox"),
480 REG_NAME ( 30, "SPU_WrOutIntrMbox"),
481 REG_NAME ( 9, "MFC_WrMSSyncReq"),
482 REG_NAME ( 12, "MFC_RdTagMask"), /* DD2.0 only */
483 REG_NAME ( 16, "MFC_LSA"),
484 REG_NAME ( 17, "MFC_EAH"),
485 REG_NAME ( 18, "MFC_EAL"),
486 REG_NAME ( 19, "MFC_Size"),
487 REG_NAME ( 20, "MFC_TagID"),
488 REG_NAME ( 21, "MFC_Cmd"),
489 REG_NAME ( 22, "MFC_WrTagMask"),
490 REG_NAME ( 23, "MFC_WrTagUpdate"),
491 REG_NAME ( 24, "MFC_RdTagStat"),
492 REG_NAME ( 25, "MFC_RdListStallStat"),
493 REG_NAME ( 26, "MFC_WrListStallAck"),
494 REG_NAME ( 27, "MFC_RdAtomicStat"),
499 get_reg (const char *param
, struct spu_insn
*insn
, int arg
, int accept_expr
)
510 if (arg
== A_H
) /* Channel */
512 if ((param
[0] == 'c' || param
[0] == 'C')
513 && (param
[1] == 'h' || param
[1] == 'H')
514 && ISDIGIT (param
[2]))
517 else if (arg
== A_S
) /* Special purpose register */
519 if ((param
[0] == 's' || param
[0] == 'S')
520 && (param
[1] == 'p' || param
[1] == 'P')
521 && ISDIGIT (param
[2]))
525 if (ISDIGIT (*param
))
528 while (ISDIGIT (*param
))
529 regno
= regno
* 10 + *param
++ - '0';
534 unsigned int i
, n
, l
= 0;
536 if (arg
== A_H
) /* Channel */
539 n
= sizeof (ch_reg_name
) / sizeof (*ch_reg_name
);
541 else if (arg
== A_S
) /* Special purpose register */
544 n
= sizeof (sp_reg_name
) / sizeof (*sp_reg_name
);
549 n
= sizeof (reg_name
) / sizeof (*reg_name
);
552 for (i
= 0; i
< n
; i
++)
554 && 0 == strncasecmp (param
, rn
[i
].name
, rn
[i
].length
))
566 as_bad (_("'SPU_RdEventMask' (channel 11) is only available in DD2.0 or higher."));
567 else if (regno
== 12)
568 as_bad (_("'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher."));
573 insn
->opcode
|= regno
<< arg_encode
[arg
].pos
;
574 if ((!saw_prefix
&& syntax_reg
== 1)
575 || (saw_prefix
&& syntax_reg
== 2))
577 syntax_reg
|= saw_prefix
? 1 : 2;
585 save_ptr
= input_line_pointer
;
586 input_line_pointer
= (char *)param
;
588 param
= input_line_pointer
;
589 input_line_pointer
= save_ptr
;
590 if (ex
.X_op
== O_register
|| ex
.X_op
== O_constant
)
592 insn
->opcode
|= ex
.X_add_number
<< arg_encode
[arg
].pos
;
600 get_imm (const char *param
, struct spu_insn
*insn
, int arg
)
604 int low
= 0, high
= 0;
605 int reloc_i
= insn
->reloc_arg
[0] >= 0 ? 1 : 0;
607 if (strncasecmp (param
, "%lo(", 4) == 0)
611 as_warn (_("Using old style, %%lo(expr), please change to PPC style, expr@l."));
613 else if (strncasecmp (param
, "%hi(", 4) == 0)
617 as_warn (_("Using old style, %%hi(expr), please change to PPC style, expr@h."));
619 else if (strncasecmp (param
, "%pic(", 5) == 0)
621 /* Currently we expect %pic(expr) == expr, so do nothing here.
622 i.e. for code loaded at address 0 $toc will be 0. */
628 /* Symbols can start with $, but if this symbol matches a register
629 name, it's probably a mistake. The only way to avoid this
630 warning is to rename the symbol. */
631 struct spu_insn tmp_insn
;
632 const char *np
= get_reg (param
, &tmp_insn
, arg
, 0);
635 syntax_error_param
= np
;
638 save_ptr
= input_line_pointer
;
639 input_line_pointer
= (char *) param
;
640 expression (&insn
->exp
[reloc_i
]);
641 param
= input_line_pointer
;
642 input_line_pointer
= save_ptr
;
644 /* Similar to ppc_elf_suffix in tc-ppc.c. We have so few cases to
645 handle we do it inlined here. */
646 if (param
[0] == '@' && !ISALNUM (param
[2]) && param
[2] != '@')
648 if (param
[1] == 'h' || param
[1] == 'H')
653 else if (param
[1] == 'l' || param
[1] == 'L')
660 if (insn
->exp
[reloc_i
].X_op
== O_constant
)
662 val
= insn
->exp
[reloc_i
].X_add_number
;
666 /* Convert the value to a format we expect. */
667 val
<<= arg_encode
[arg
].rshift
;
670 else if (arg
== A_U7B
)
679 /* Warn about out of range expressions. */
681 int hi
= arg_encode
[arg
].hi
;
682 int lo
= arg_encode
[arg
].lo
;
683 int whi
= arg_encode
[arg
].whi
;
684 int wlo
= arg_encode
[arg
].wlo
;
686 if (hi
> lo
&& (val
< lo
|| val
> hi
))
687 as_fatal (_("Constant expression %d out of range, [%d, %d]."),
689 else if (whi
> wlo
&& (val
< wlo
|| val
> whi
))
690 as_warn (_("Constant expression %d out of range, [%d, %d]."),
696 else if (arg
== A_U7B
)
699 /* Branch hints have a split encoding. Do the bottom part. */
700 if (arg
== A_S11
|| arg
== A_S11I
)
701 insn
->opcode
|= ((val
>> 2) & 0x7f);
703 insn
->opcode
|= (((val
>> arg_encode
[arg
].rshift
)
704 & ((1 << arg_encode
[arg
].size
) - 1))
705 << arg_encode
[arg
].pos
);
709 insn
->reloc_arg
[reloc_i
] = arg
;
711 insn
->reloc
[reloc_i
] = BFD_RELOC_SPU_HI16
;
713 insn
->reloc
[reloc_i
] = BFD_RELOC_SPU_LO16
;
715 insn
->reloc
[reloc_i
] = arg_encode
[arg
].reloc
;
722 md_atof (int type
, char *litP
, int *sizeP
)
724 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
727 #ifndef WORKING_DOT_WORD
728 int md_short_jump_size
= 4;
731 md_create_short_jump (char *ptr
,
732 addressT from_addr ATTRIBUTE_UNUSED
,
733 addressT to_addr ATTRIBUTE_UNUSED
,
737 ptr
[0] = (char) 0xc0;
742 ptr
- frag
->fr_literal
,
747 BFD_RELOC_SPU_PCREL16
);
750 int md_long_jump_size
= 4;
753 md_create_long_jump (char *ptr
,
754 addressT from_addr ATTRIBUTE_UNUSED
,
755 addressT to_addr ATTRIBUTE_UNUSED
,
759 ptr
[0] = (char) 0xc0;
764 ptr
- frag
->fr_literal
,
769 BFD_RELOC_SPU_PCREL16
);
773 /* Handle .brinfo <priority>,<lrlive>. */
775 spu_brinfo (int ignore ATTRIBUTE_UNUSED
)
780 priority
= get_absolute_expression ();
784 if (*input_line_pointer
== ',')
786 ++input_line_pointer
;
787 lrlive
= get_absolute_expression ();
790 if (priority
> 0x1fff)
792 as_bad (_("invalid priority '%lu'"), (unsigned long) priority
);
798 as_bad (_("invalid lrlive '%lu'"), (unsigned long) lrlive
);
802 brinfo
= (lrlive
<< 13) | priority
;
803 demand_empty_rest_of_line ();
806 /* Support @ppu on symbols referenced in .int/.long/.word/.quad. */
808 spu_cons (int nbytes
)
812 if (is_it_end_of_statement ())
814 demand_empty_rest_of_line ();
820 deferred_expression (&exp
);
821 if ((exp
.X_op
== O_symbol
822 || exp
.X_op
== O_constant
)
823 && strncasecmp (input_line_pointer
, "@ppu", 4) == 0)
825 char *p
= frag_more (nbytes
);
826 enum bfd_reloc_code_real reloc
;
828 /* Check for identifier@suffix+constant. */
829 input_line_pointer
+= 4;
830 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
834 expression (&new_exp
);
835 if (new_exp
.X_op
== O_constant
)
836 exp
.X_add_number
+= new_exp
.X_add_number
;
839 reloc
= nbytes
== 4 ? BFD_RELOC_SPU_PPU32
: BFD_RELOC_SPU_PPU64
;
840 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, nbytes
,
844 emit_expr (&exp
, nbytes
);
846 while (*input_line_pointer
++ == ',');
848 /* Put terminator back into stream. */
849 input_line_pointer
--;
850 demand_empty_rest_of_line ();
854 md_estimate_size_before_relax (fragS
*fragP ATTRIBUTE_UNUSED
,
855 segT segment_type ATTRIBUTE_UNUSED
)
857 as_fatal (_("Relaxation should never occur"));
861 /* If while processing a fixup, a reloc really needs to be created,
862 then it is done here. */
865 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
868 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
869 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
871 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
872 else if (fixp
->fx_subsy
)
873 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_subsy
);
876 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
877 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
878 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
880 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
881 _("reloc %d not supported by object file format"),
882 (int) fixp
->fx_r_type
);
885 reloc
->addend
= fixp
->fx_addnumber
;
889 /* Round up a section's size to the appropriate boundary. */
892 md_section_align (segT seg
, valueT size
)
894 int align
= bfd_get_section_alignment (stdoutput
, seg
);
895 valueT mask
= ((valueT
) 1 << align
) - 1;
897 return (size
+ mask
) & ~mask
;
900 /* Where a PC relative offset is calculated from. On the spu they
901 are calculated from the beginning of the branch instruction. */
904 md_pcrel_from (fixS
*fixp
)
906 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
909 /* Fill in rs_align_code fragments. */
912 spu_handle_align (fragS
*fragp
)
914 static const unsigned char nop_pattern
[8] = {
915 0x40, 0x20, 0x00, 0x00, /* even nop */
916 0x00, 0x20, 0x00, 0x00, /* odd nop */
922 if (fragp
->fr_type
!= rs_align_code
)
925 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
926 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
934 fragp
->fr_fix
+= fix
;
938 memcpy (p
, &nop_pattern
[4], 4);
944 memcpy (p
, nop_pattern
, 8);
949 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
954 char *place
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
956 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
958 /* We can't actually support subtracting a symbol. */
959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
962 if (fixP
->fx_addsy
!= NULL
)
966 /* Hack around bfd_install_relocation brain damage. */
967 val
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
969 switch (fixP
->fx_r_type
)
972 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
975 case BFD_RELOC_SPU_PCREL16
:
976 case BFD_RELOC_SPU_PCREL9a
:
977 case BFD_RELOC_SPU_PCREL9b
:
978 case BFD_RELOC_32_PCREL
:
982 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
983 _("expression too complex"));
989 fixP
->fx_addnumber
= val
;
991 if (fixP
->fx_r_type
== BFD_RELOC_SPU_PPU32
992 || fixP
->fx_r_type
== BFD_RELOC_SPU_PPU64
)
995 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
1000 if (fixP
->tc_fix_data
.arg_format
> A_P
)
1002 int hi
= arg_encode
[fixP
->tc_fix_data
.arg_format
].hi
;
1003 int lo
= arg_encode
[fixP
->tc_fix_data
.arg_format
].lo
;
1004 if (hi
> lo
&& ((offsetT
) val
< lo
|| (offsetT
) val
> hi
))
1005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1006 "Relocation doesn't fit. (relocation value = 0x%lx)",
1010 switch (fixP
->fx_r_type
)
1013 md_number_to_chars (place
, val
, 1);
1017 md_number_to_chars (place
, val
, 2);
1021 case BFD_RELOC_32_PCREL
:
1022 md_number_to_chars (place
, val
, 4);
1026 md_number_to_chars (place
, val
, 8);
1029 case BFD_RELOC_SPU_IMM7
:
1034 case BFD_RELOC_SPU_IMM8
:
1039 case BFD_RELOC_SPU_IMM10
:
1044 case BFD_RELOC_SPU_IMM10W
:
1046 mask
= 0x3ff0 << 10;
1049 case BFD_RELOC_SPU_IMM16
:
1054 case BFD_RELOC_SPU_IMM16W
:
1056 mask
= 0x3fffc << 5;
1059 case BFD_RELOC_SPU_IMM18
:
1061 mask
= 0x3ffff << 7;
1064 case BFD_RELOC_SPU_PCREL9a
:
1065 res
= ((val
& 0x1fc) >> 2) | ((val
& 0x600) << 14);
1066 mask
= (0x1fc >> 2) | (0x600 << 14);
1069 case BFD_RELOC_SPU_PCREL9b
:
1070 res
= ((val
& 0x1fc) >> 2) | ((val
& 0x600) << 5);
1071 mask
= (0x1fc >> 2) | (0x600 << 5);
1074 case BFD_RELOC_SPU_PCREL16
:
1076 mask
= 0x3fffc << 5;
1079 case BFD_RELOC_SPU_HI16
:
1084 case BFD_RELOC_SPU_LO16
:
1090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1091 _("reloc %d not supported by object file format"),
1092 (int) fixP
->fx_r_type
);
1096 place
[0] = (place
[0] & (~mask
>> 24)) | ((res
>> 24) & 0xff);
1097 place
[1] = (place
[1] & (~mask
>> 16)) | ((res
>> 16) & 0xff);
1098 place
[2] = (place
[2] & (~mask
>> 8)) | ((res
>> 8) & 0xff);
1099 place
[3] = (place
[3] & ~mask
) | (res
& 0xff);