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Updated translations for the bfd, binutils, gas, ld and opcodes directories
[binutils-gdb.git] / opcodes / i386-dis.c
blob59ec771369ab68de93f4cc622b6488824037f7c1
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2024 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 typedef struct instr_info instr_info;
43
44 static bool dofloat (instr_info *, int);
45 static int putop (instr_info *, const char *, int);
46 static void oappend_with_style (instr_info *, const char *,
47 enum disassembler_style);
48
49 static bool OP_E (instr_info *, int, int);
50 static bool OP_E_memory (instr_info *, int, int);
51 static bool OP_indirE (instr_info *, int, int);
52 static bool OP_G (instr_info *, int, int);
53 static bool OP_ST (instr_info *, int, int);
54 static bool OP_STi (instr_info *, int, int);
55 static bool OP_Skip_MODRM (instr_info *, int, int);
56 static bool OP_REG (instr_info *, int, int);
57 static bool OP_IMREG (instr_info *, int, int);
58 static bool OP_I (instr_info *, int, int);
59 static bool OP_I64 (instr_info *, int, int);
60 static bool OP_sI (instr_info *, int, int);
61 static bool OP_J (instr_info *, int, int);
62 static bool OP_SEG (instr_info *, int, int);
63 static bool OP_DIR (instr_info *, int, int);
64 static bool OP_OFF (instr_info *, int, int);
65 static bool OP_OFF64 (instr_info *, int, int);
66 static bool OP_ESreg (instr_info *, int, int);
67 static bool OP_DSreg (instr_info *, int, int);
68 static bool OP_C (instr_info *, int, int);
69 static bool OP_D (instr_info *, int, int);
70 static bool OP_T (instr_info *, int, int);
71 static bool OP_MMX (instr_info *, int, int);
72 static bool OP_XMM (instr_info *, int, int);
73 static bool OP_EM (instr_info *, int, int);
74 static bool OP_EX (instr_info *, int, int);
75 static bool OP_EMC (instr_info *, int,int);
76 static bool OP_MXC (instr_info *, int,int);
77 static bool OP_R (instr_info *, int, int);
78 static bool OP_M (instr_info *, int, int);
79 static bool OP_VEX (instr_info *, int, int);
80 static bool OP_VexR (instr_info *, int, int);
81 static bool OP_VexW (instr_info *, int, int);
82 static bool OP_Rounding (instr_info *, int, int);
83 static bool OP_REG_VexI4 (instr_info *, int, int);
84 static bool OP_VexI4 (instr_info *, int, int);
85 static bool OP_0f07 (instr_info *, int, int);
86 static bool OP_Monitor (instr_info *, int, int);
87 static bool OP_Mwait (instr_info *, int, int);
88
89 static bool PCLMUL_Fixup (instr_info *, int, int);
90 static bool VPCMP_Fixup (instr_info *, int, int);
91 static bool VPCOM_Fixup (instr_info *, int, int);
92 static bool NOP_Fixup (instr_info *, int, int);
93 static bool OP_3DNowSuffix (instr_info *, int, int);
94 static bool CMP_Fixup (instr_info *, int, int);
95 static bool REP_Fixup (instr_info *, int, int);
96 static bool SEP_Fixup (instr_info *, int, int);
97 static bool BND_Fixup (instr_info *, int, int);
98 static bool NOTRACK_Fixup (instr_info *, int, int);
99 static bool HLE_Fixup1 (instr_info *, int, int);
100 static bool HLE_Fixup2 (instr_info *, int, int);
101 static bool HLE_Fixup3 (instr_info *, int, int);
102 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
103 static bool XMM_Fixup (instr_info *, int, int);
104 static bool FXSAVE_Fixup (instr_info *, int, int);
105 static bool MOVSXD_Fixup (instr_info *, int, int);
106 static bool DistinctDest_Fixup (instr_info *, int, int);
107 static bool PREFETCHI_Fixup (instr_info *, int, int);
108 static bool PUSH2_POP2_Fixup (instr_info *, int, int);
109 static bool JMPABS_Fixup (instr_info *, int, int);
110 static bool CFCMOV_Fixup (instr_info *, int, int);
111
112 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
113 enum disassembler_style,
114 const char *, ...);
115
116 /* This character is used to encode style information within the output
117 buffers. See oappend_insert_style for more details. */
118 #define STYLE_MARKER_CHAR '\002'
119
120 /* The maximum operand buffer size. */
121 #define MAX_OPERAND_BUFFER_SIZE 128
122
123 enum address_mode
124 {
125 mode_16bit,
126 mode_32bit,
127 mode_64bit
128 };
129
130 static const char *prefix_name (enum address_mode, uint8_t, int);
131
132 enum x86_64_isa
133 {
134 amd64 = 1,
135 intel64
136 };
137
138 enum evex_type
139 {
140 evex_default = 0,
141 evex_from_legacy,
142 evex_from_vex,
143 };
144
145 struct instr_info
146 {
147 enum address_mode address_mode;
148
149 /* Flags for the prefixes for the current instruction. See below. */
150 int prefixes;
151
152 /* REX prefix the current instruction. See below. */
153 uint8_t rex;
154 /* Bits of REX we've already used. */
155 uint8_t rex_used;
156
157 /* Record W R4 X4 B4 bits for rex2. */
158 unsigned char rex2;
159 /* Bits of rex2 we've already used. */
160 unsigned char rex2_used;
161 unsigned char rex2_payload;
162
163 bool need_modrm;
164 unsigned char condition_code;
165 unsigned char need_vex;
166 bool has_sib;
167
168 /* Flags for ins->prefixes which we somehow handled when printing the
169 current instruction. */
170 int used_prefixes;
171
172 /* Flags for EVEX bits which we somehow handled when printing the
173 current instruction. */
174 int evex_used;
175
176 char obuf[MAX_OPERAND_BUFFER_SIZE];
177 char *obufp;
178 char *mnemonicendp;
179 const uint8_t *start_codep;
180 uint8_t *codep;
181 const uint8_t *end_codep;
182 unsigned char nr_prefixes;
183 signed char last_lock_prefix;
184 signed char last_repz_prefix;
185 signed char last_repnz_prefix;
186 signed char last_data_prefix;
187 signed char last_addr_prefix;
188 signed char last_rex_prefix;
189 signed char last_rex2_prefix;
190 signed char last_seg_prefix;
191 signed char fwait_prefix;
192 /* The active segment register prefix. */
193 unsigned char active_seg_prefix;
194
195 #define MAX_CODE_LENGTH 15
196 /* We can up to 14 ins->prefixes since the maximum instruction length is
197 15bytes. */
198 uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
199 disassemble_info *info;
200
201 struct
202 {
203 int mod;
204 int reg;
205 int rm;
206 }
207 modrm;
208
209 struct
210 {
211 int scale;
212 int index;
213 int base;
214 }
215 sib;
216
217 struct
218 {
219 int register_specifier;
220 int length;
221 int prefix;
222 int mask_register_specifier;
223 int scc;
224 int ll;
225 bool w;
226 bool evex;
227 bool v;
228 bool zeroing;
229 bool b;
230 bool no_broadcast;
231 bool nf;
232 }
233 vex;
234
235 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */
236 #define nd b
237
238 enum evex_type evex_type;
239
240 /* Remember if the current op is a jump instruction. */
241 bool op_is_jump;
242
243 bool two_source_ops;
244
245 /* Record whether EVEX masking is used incorrectly. */
246 bool illegal_masking;
247
248 /* Record whether the modrm byte has been skipped. */
249 bool has_skipped_modrm;
250
251 unsigned char op_ad;
252 signed char op_index[MAX_OPERANDS];
253 bool op_riprel[MAX_OPERANDS];
254 char *op_out[MAX_OPERANDS];
255 bfd_vma op_address[MAX_OPERANDS];
256 bfd_vma start_pc;
257
258 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
259 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
260 * section of the "Virtual 8086 Mode" chapter.)
261 * 'pc' should be the address of this instruction, it will
262 * be used to print the target address if this is a relative jump or call
263 * The function returns the length of this instruction in bytes.
264 */
265 char intel_syntax;
266 bool intel_mnemonic;
267 char open_char;
268 char close_char;
269 char separator_char;
270 char scale_char;
271
272 enum x86_64_isa isa64;
273 };
274
275 struct dis_private {
276 bfd_vma insn_start;
277 int orig_sizeflag;
278
279 /* Indexes first byte not fetched. */
280 unsigned int fetched;
281 uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
282 };
283
284 /* Mark parts used in the REX prefix. When we are testing for
285 empty prefix (for 8bit register REX extension), just mask it
286 out. Otherwise test for REX bit is excuse for existence of REX
287 only in case value is nonzero. */
288 #define USED_REX(value) \
289 { \
290 if (value) \
291 { \
292 if (ins->rex & value) \
293 ins->rex_used |= (value) | REX_OPCODE; \
294 if (ins->rex2 & value) \
295 { \
296 ins->rex2_used |= (value); \
297 ins->rex_used |= REX_OPCODE; \
298 } \
299 } \
300 else \
301 ins->rex_used |= REX_OPCODE; \
302 }
303
304
305 #define EVEX_b_used 1
306 #define EVEX_len_used 2
307
308
309 /* {rex2} is not printed when the REX2_SPECIAL is set. */
310 #define REX2_SPECIAL 16
311
312 /* Flags stored in PREFIXES. */
313 #define PREFIX_REPZ 1
314 #define PREFIX_REPNZ 2
315 #define PREFIX_CS 4
316 #define PREFIX_SS 8
317 #define PREFIX_DS 0x10
318 #define PREFIX_ES 0x20
319 #define PREFIX_FS 0x40
320 #define PREFIX_GS 0x80
321 #define PREFIX_LOCK 0x100
322 #define PREFIX_DATA 0x200
323 #define PREFIX_ADDR 0x400
324 #define PREFIX_FWAIT 0x800
325 #define PREFIX_REX2 0x1000
326 #define PREFIX_NP_OR_DATA 0x2000
327 #define NO_PREFIX 0x4000
328
329 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
330 to ADDR (exclusive) are valid. Returns true for success, false
331 on error. */
332 static bool
333 fetch_code (struct disassemble_info *info, const uint8_t *until)
334 {
335 int status = -1;
336 struct dis_private *priv = info->private_data;
337 bfd_vma start = priv->insn_start + priv->fetched;
338 uint8_t *fetch_end = priv->the_buffer + priv->fetched;
339 ptrdiff_t needed = until - fetch_end;
340
341 if (needed <= 0)
342 return true;
343
344 if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
345 status = (*info->read_memory_func) (start, fetch_end, needed, info);
346 if (status != 0)
347 {
348 /* If we did manage to read at least one byte, then
349 print_insn_i386 will do something sensible. Otherwise, print
350 an error. We do that here because this is where we know
351 STATUS. */
352 if (!priv->fetched)
353 (*info->memory_error_func) (status, start, info);
354 return false;
355 }
356
357 priv->fetched += needed;
358 return true;
359 }
360
361 static bool
362 fetch_modrm (instr_info *ins)
363 {
364 if (!fetch_code (ins->info, ins->codep + 1))
365 return false;
366
367 ins->modrm.mod = (*ins->codep >> 6) & 3;
368 ins->modrm.reg = (*ins->codep >> 3) & 7;
369 ins->modrm.rm = *ins->codep & 7;
370
371 return true;
372 }
373
374 static int
375 fetch_error (const instr_info *ins)
376 {
377 /* Getting here means we tried for data but didn't get it. That
378 means we have an incomplete instruction of some sort. Just
379 print the first byte as a prefix or a .byte pseudo-op. */
380 const struct dis_private *priv = ins->info->private_data;
381 const char *name = NULL;
382
383 if (ins->codep <= priv->the_buffer)
384 return -1;
385
386 if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
387 name = prefix_name (ins->address_mode, priv->the_buffer[0],
388 priv->orig_sizeflag);
389 if (name != NULL)
390 i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
391 else
392 {
393 /* Just print the first byte as a .byte instruction. */
394 i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
395 i386_dis_printf (ins->info, dis_style_immediate, "%#x",
396 (unsigned int) priv->the_buffer[0]);
397 }
398
399 return 1;
400 }
401
402 /* Possible values for prefix requirement. */
403 #define PREFIX_IGNORED_SHIFT 16
404 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
405 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
406 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
407 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
408 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
409 #define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
410
411 /* Opcode prefixes. */
412 #define PREFIX_OPCODE (PREFIX_REPZ \
413 | PREFIX_REPNZ \
414 | PREFIX_DATA)
415
416 /* Prefixes ignored. */
417 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
418 | PREFIX_IGNORED_REPNZ \
419 | PREFIX_IGNORED_DATA)
420
421 #define XX { NULL, 0 }
422 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
423
424 #define Eb { OP_E, b_mode }
425 #define Ebnd { OP_E, bnd_mode }
426 #define EbS { OP_E, b_swap_mode }
427 #define EbndS { OP_E, bnd_swap_mode }
428 #define Ev { OP_E, v_mode }
429 #define Eva { OP_E, va_mode }
430 #define Ev_bnd { OP_E, v_bnd_mode }
431 #define EvS { OP_E, v_swap_mode }
432 #define Ed { OP_E, d_mode }
433 #define Edq { OP_E, dq_mode }
434 #define Edb { OP_E, db_mode }
435 #define Edw { OP_E, dw_mode }
436 #define Eq { OP_E, q_mode }
437 #define indirEv { OP_indirE, indir_v_mode }
438 #define indirEp { OP_indirE, f_mode }
439 #define stackEv { OP_E, stack_v_mode }
440 #define Em { OP_E, m_mode }
441 #define Ew { OP_E, w_mode }
442 #define M { OP_M, 0 } /* lea, lgdt, etc. */
443 #define Ma { OP_M, a_mode }
444 #define Mb { OP_M, b_mode }
445 #define Md { OP_M, d_mode }
446 #define Mdq { OP_M, dq_mode }
447 #define Mo { OP_M, o_mode }
448 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
449 #define Mq { OP_M, q_mode }
450 #define Mv { OP_M, v_mode }
451 #define Mv_bnd { OP_M, v_bndmk_mode }
452 #define Mw { OP_M, w_mode }
453 #define Mx { OP_M, x_mode }
454 #define Mxmm { OP_M, xmm_mode }
455 #define Mymm { OP_M, ymm_mode }
456 #define Gb { OP_G, b_mode }
457 #define Gbnd { OP_G, bnd_mode }
458 #define Gv { OP_G, v_mode }
459 #define Gd { OP_G, d_mode }
460 #define Gdq { OP_G, dq_mode }
461 #define Gq { OP_G, q_mode }
462 #define Gm { OP_G, m_mode }
463 #define Gva { OP_G, va_mode }
464 #define Gw { OP_G, w_mode }
465 #define Ib { OP_I, b_mode }
466 #define sIb { OP_sI, b_mode } /* sign extened byte */
467 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
468 #define Iv { OP_I, v_mode }
469 #define sIv { OP_sI, v_mode }
470 #define Iv64 { OP_I64, v_mode }
471 #define Id { OP_I, d_mode }
472 #define Iw { OP_I, w_mode }
473 #define I1 { OP_I, const_1_mode }
474 #define Jb { OP_J, b_mode }
475 #define Jv { OP_J, v_mode }
476 #define Jdqw { OP_J, dqw_mode }
477 #define Cm { OP_C, m_mode }
478 #define Dm { OP_D, m_mode }
479 #define Td { OP_T, d_mode }
480 #define Skip_MODRM { OP_Skip_MODRM, 0 }
481
482 #define RMeAX { OP_REG, eAX_reg }
483 #define RMeBX { OP_REG, eBX_reg }
484 #define RMeCX { OP_REG, eCX_reg }
485 #define RMeDX { OP_REG, eDX_reg }
486 #define RMeSP { OP_REG, eSP_reg }
487 #define RMeBP { OP_REG, eBP_reg }
488 #define RMeSI { OP_REG, eSI_reg }
489 #define RMeDI { OP_REG, eDI_reg }
490 #define RMrAX { OP_REG, rAX_reg }
491 #define RMrBX { OP_REG, rBX_reg }
492 #define RMrCX { OP_REG, rCX_reg }
493 #define RMrDX { OP_REG, rDX_reg }
494 #define RMrSP { OP_REG, rSP_reg }
495 #define RMrBP { OP_REG, rBP_reg }
496 #define RMrSI { OP_REG, rSI_reg }
497 #define RMrDI { OP_REG, rDI_reg }
498 #define RMAL { OP_REG, al_reg }
499 #define RMCL { OP_REG, cl_reg }
500 #define RMDL { OP_REG, dl_reg }
501 #define RMBL { OP_REG, bl_reg }
502 #define RMAH { OP_REG, ah_reg }
503 #define RMCH { OP_REG, ch_reg }
504 #define RMDH { OP_REG, dh_reg }
505 #define RMBH { OP_REG, bh_reg }
506 #define RMAX { OP_REG, ax_reg }
507 #define RMDX { OP_REG, dx_reg }
508
509 #define eAX { OP_IMREG, eAX_reg }
510 #define AL { OP_IMREG, al_reg }
511 #define CL { OP_IMREG, cl_reg }
512 #define zAX { OP_IMREG, z_mode_ax_reg }
513 #define indirDX { OP_IMREG, indir_dx_reg }
514
515 #define Sw { OP_SEG, w_mode }
516 #define Sv { OP_SEG, v_mode }
517 #define Ap { OP_DIR, 0 }
518 #define Ob { OP_OFF64, b_mode }
519 #define Ov { OP_OFF64, v_mode }
520 #define Xb { OP_DSreg, eSI_reg }
521 #define Xv { OP_DSreg, eSI_reg }
522 #define Xz { OP_DSreg, eSI_reg }
523 #define Yb { OP_ESreg, eDI_reg }
524 #define Yv { OP_ESreg, eDI_reg }
525 #define DSBX { OP_DSreg, eBX_reg }
526
527 #define es { OP_REG, es_reg }
528 #define ss { OP_REG, ss_reg }
529 #define cs { OP_REG, cs_reg }
530 #define ds { OP_REG, ds_reg }
531 #define fs { OP_REG, fs_reg }
532 #define gs { OP_REG, gs_reg }
533
534 #define MX { OP_MMX, 0 }
535 #define XM { OP_XMM, 0 }
536 #define XMScalar { OP_XMM, scalar_mode }
537 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
538 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
539 #define XMM { OP_XMM, xmm_mode }
540 #define TMM { OP_XMM, tmm_mode }
541 #define XMxmmq { OP_XMM, xmmq_mode }
542 #define EM { OP_EM, v_mode }
543 #define EMS { OP_EM, v_swap_mode }
544 #define EMd { OP_EM, d_mode }
545 #define EMx { OP_EM, x_mode }
546 #define EXbwUnit { OP_EX, bw_unit_mode }
547 #define EXb { OP_EX, b_mode }
548 #define EXw { OP_EX, w_mode }
549 #define EXd { OP_EX, d_mode }
550 #define EXdS { OP_EX, d_swap_mode }
551 #define EXwS { OP_EX, w_swap_mode }
552 #define EXq { OP_EX, q_mode }
553 #define EXqS { OP_EX, q_swap_mode }
554 #define EXdq { OP_EX, dq_mode }
555 #define EXx { OP_EX, x_mode }
556 #define EXxh { OP_EX, xh_mode }
557 #define EXxS { OP_EX, x_swap_mode }
558 #define EXxmm { OP_EX, xmm_mode }
559 #define EXymm { OP_EX, ymm_mode }
560 #define EXxmmq { OP_EX, xmmq_mode }
561 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
562 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
563 #define EXxmmdw { OP_EX, xmmdw_mode }
564 #define EXxmmqd { OP_EX, xmmqd_mode }
565 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
566 #define EXymmq { OP_EX, ymmq_mode }
567 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
568 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
569 #define Rd { OP_R, d_mode }
570 #define Rdq { OP_R, dq_mode }
571 #define Rq { OP_R, q_mode }
572 #define Nq { OP_R, q_mm_mode }
573 #define Ux { OP_R, x_mode }
574 #define Uxmm { OP_R, xmm_mode }
575 #define Rxmmq { OP_R, xmmq_mode }
576 #define Rymm { OP_R, ymm_mode }
577 #define Rtmm { OP_R, tmm_mode }
578 #define EMCq { OP_EMC, q_mode }
579 #define MXC { OP_MXC, 0 }
580 #define OPSUF { OP_3DNowSuffix, 0 }
581 #define SEP { SEP_Fixup, 0 }
582 #define CMP { CMP_Fixup, 0 }
583 #define XMM0 { XMM_Fixup, 0 }
584 #define FXSAVE { FXSAVE_Fixup, 0 }
585
586 #define Vex { OP_VEX, x_mode }
587 #define VexW { OP_VexW, x_mode }
588 #define VexScalar { OP_VEX, scalar_mode }
589 #define VexScalarR { OP_VexR, scalar_mode }
590 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
591 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
592 #define VexGdq { OP_VEX, dq_mode }
593 #define VexGb { OP_VEX, b_mode }
594 #define VexGv { OP_VEX, v_mode }
595 #define VexTmm { OP_VEX, tmm_mode }
596 #define XMVexI4 { OP_REG_VexI4, x_mode }
597 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
598 #define VexI4 { OP_VexI4, 0 }
599 #define PCLMUL { PCLMUL_Fixup, 0 }
600 #define VPCMP { VPCMP_Fixup, 0 }
601 #define VPCOM { VPCOM_Fixup, 0 }
602
603 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
604 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
605 #define EXxEVexS { OP_Rounding, evex_sae_mode }
606
607 #define MaskG { OP_G, mask_mode }
608 #define MaskE { OP_E, mask_mode }
609 #define MaskR { OP_R, mask_mode }
610 #define MaskBDE { OP_E, mask_bd_mode }
611 #define MaskVex { OP_VEX, mask_mode }
612
613 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
614 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
615
616 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
617
618 /* Used handle "rep" prefix for string instructions. */
619 #define Xbr { REP_Fixup, eSI_reg }
620 #define Xvr { REP_Fixup, eSI_reg }
621 #define Ybr { REP_Fixup, eDI_reg }
622 #define Yvr { REP_Fixup, eDI_reg }
623 #define Yzr { REP_Fixup, eDI_reg }
624 #define indirDXr { REP_Fixup, indir_dx_reg }
625 #define ALr { REP_Fixup, al_reg }
626 #define eAXr { REP_Fixup, eAX_reg }
627
628 /* Used handle HLE prefix for lockable instructions. */
629 #define Ebh1 { HLE_Fixup1, b_mode }
630 #define Evh1 { HLE_Fixup1, v_mode }
631 #define Ebh2 { HLE_Fixup2, b_mode }
632 #define Evh2 { HLE_Fixup2, v_mode }
633 #define Ebh3 { HLE_Fixup3, b_mode }
634 #define Evh3 { HLE_Fixup3, v_mode }
635
636 #define BND { BND_Fixup, 0 }
637 #define NOTRACK { NOTRACK_Fixup, 0 }
638
639 #define cond_jump_flag { NULL, cond_jump_mode }
640 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
641
642 /* bits in sizeflag */
643 #define SUFFIX_ALWAYS 4
644 #define AFLAG 2
645 #define DFLAG 1
646
647 enum
648 {
649 /* byte operand */
650 b_mode = 1,
651 /* byte operand with operand swapped */
652 b_swap_mode,
653 /* byte operand, sign extend like 'T' suffix */
654 b_T_mode,
655 /* operand size depends on prefixes */
656 v_mode,
657 /* operand size depends on prefixes with operand swapped */
658 v_swap_mode,
659 /* operand size depends on address prefix */
660 va_mode,
661 /* word operand */
662 w_mode,
663 /* double word operand */
664 d_mode,
665 /* word operand with operand swapped */
666 w_swap_mode,
667 /* double word operand with operand swapped */
668 d_swap_mode,
669 /* quad word operand */
670 q_mode,
671 /* 8-byte MM operand */
672 q_mm_mode,
673 /* quad word operand with operand swapped */
674 q_swap_mode,
675 /* ten-byte operand */
676 t_mode,
677 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
678 broadcast enabled. */
679 x_mode,
680 /* Similar to x_mode, but with different EVEX mem shifts. */
681 evex_x_gscat_mode,
682 /* Similar to x_mode, but with yet different EVEX mem shifts. */
683 bw_unit_mode,
684 /* Similar to x_mode, but with disabled broadcast. */
685 evex_x_nobcst_mode,
686 /* Similar to x_mode, but with operands swapped and disabled broadcast
687 in EVEX. */
688 x_swap_mode,
689 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
690 broadcast of 16bit enabled. */
691 xh_mode,
692 /* 16-byte XMM operand */
693 xmm_mode,
694 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
695 memory operand (depending on vector length). Broadcast isn't
696 allowed. */
697 xmmq_mode,
698 /* Same as xmmq_mode, but broadcast is allowed. */
699 evex_half_bcst_xmmq_mode,
700 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
701 memory operand (depending on vector length). 16bit broadcast. */
702 evex_half_bcst_xmmqh_mode,
703 /* 16-byte XMM, word, double word or quad word operand. */
704 xmmdw_mode,
705 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
706 xmmqd_mode,
707 /* 16-byte XMM, double word, quad word operand or xmm word operand.
708 16bit broadcast. */
709 evex_half_bcst_xmmqdh_mode,
710 /* 32-byte YMM operand */
711 ymm_mode,
712 /* quad word, ymmword or zmmword memory operand. */
713 ymmq_mode,
714 /* TMM operand */
715 tmm_mode,
716 /* d_mode in 32bit, q_mode in 64bit mode. */
717 m_mode,
718 /* pair of v_mode operands */
719 a_mode,
720 cond_jump_mode,
721 loop_jcxz_mode,
722 movsxd_mode,
723 v_bnd_mode,
724 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
725 v_bndmk_mode,
726 /* operand size depends on REX.W / VEX.W. */
727 dq_mode,
728 /* Displacements like v_mode without considering Intel64 ISA. */
729 dqw_mode,
730 /* bounds operand */
731 bnd_mode,
732 /* bounds operand with operand swapped */
733 bnd_swap_mode,
734 /* 4- or 6-byte pointer operand */
735 f_mode,
736 const_1_mode,
737 /* v_mode for indirect branch opcodes. */
738 indir_v_mode,
739 /* v_mode for stack-related opcodes. */
740 stack_v_mode,
741 /* non-quad operand size depends on prefixes */
742 z_mode,
743 /* 16-byte operand */
744 o_mode,
745 /* registers like d_mode, memory like b_mode. */
746 db_mode,
747 /* registers like d_mode, memory like w_mode. */
748 dw_mode,
749
750 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
751 vex_vsib_d_w_dq_mode,
752 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
753 vex_vsib_q_w_dq_mode,
754 /* mandatory non-vector SIB. */
755 vex_sibmem_mode,
756
757 /* scalar, ignore vector length. */
758 scalar_mode,
759
760 /* Static rounding. */
761 evex_rounding_mode,
762 /* Static rounding, 64-bit mode only. */
763 evex_rounding_64_mode,
764 /* Supress all exceptions. */
765 evex_sae_mode,
766
767 /* Mask register operand. */
768 mask_mode,
769 /* Mask register operand. */
770 mask_bd_mode,
771
772 es_reg,
773 cs_reg,
774 ss_reg,
775 ds_reg,
776 fs_reg,
777 gs_reg,
778
779 eAX_reg,
780 eCX_reg,
781 eDX_reg,
782 eBX_reg,
783 eSP_reg,
784 eBP_reg,
785 eSI_reg,
786 eDI_reg,
787
788 al_reg,
789 cl_reg,
790 dl_reg,
791 bl_reg,
792 ah_reg,
793 ch_reg,
794 dh_reg,
795 bh_reg,
796
797 ax_reg,
798 cx_reg,
799 dx_reg,
800 bx_reg,
801 sp_reg,
802 bp_reg,
803 si_reg,
804 di_reg,
805
806 rAX_reg,
807 rCX_reg,
808 rDX_reg,
809 rBX_reg,
810 rSP_reg,
811 rBP_reg,
812 rSI_reg,
813 rDI_reg,
814
815 z_mode_ax_reg,
816 indir_dx_reg
817 };
818
819 enum
820 {
821 FLOATCODE = 1,
822 USE_REG_TABLE,
823 USE_MOD_TABLE,
824 USE_RM_TABLE,
825 USE_PREFIX_TABLE,
826 USE_X86_64_TABLE,
827 USE_X86_64_EVEX_FROM_VEX_TABLE,
828 USE_X86_64_EVEX_PFX_TABLE,
829 USE_X86_64_EVEX_W_TABLE,
830 USE_X86_64_EVEX_MEM_W_TABLE,
831 USE_3BYTE_TABLE,
832 USE_XOP_8F_TABLE,
833 USE_VEX_C4_TABLE,
834 USE_VEX_C5_TABLE,
835 USE_VEX_LEN_TABLE,
836 USE_VEX_W_TABLE,
837 USE_EVEX_TABLE,
838 USE_EVEX_LEN_TABLE
839 };
840
841 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
842
843 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
844 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
845 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
846 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
847 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
848 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
849 #define X86_64_EVEX_FROM_VEX_TABLE(I) \
850 DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
851 #define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I))
852 #define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I))
853 #define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I))
854 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
855 #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0)
856 #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0)
857 #define VEX_C5_TABLE() DIS386 (USE_VEX_C5_TABLE, 0)
858 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
859 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
860 #define EVEX_TABLE() DIS386 (USE_EVEX_TABLE, 0)
861 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
862
863 enum
864 {
865 REG_80 = 0,
866 REG_81,
867 REG_83,
868 REG_8F,
869 REG_C0,
870 REG_C1,
871 REG_C6,
872 REG_C7,
873 REG_D0,
874 REG_D1,
875 REG_D2,
876 REG_D3,
877 REG_F6,
878 REG_F7,
879 REG_FE,
880 REG_FF,
881 REG_0F00,
882 REG_0F01,
883 REG_0F0D,
884 REG_0F18,
885 REG_0F1C_P_0_MOD_0,
886 REG_0F1E_P_1_MOD_3,
887 REG_0F38D8_PREFIX_1,
888 REG_0F3A0F_P_1,
889 REG_0F71,
890 REG_0F72,
891 REG_0F73,
892 REG_0FA6,
893 REG_0FA7,
894 REG_0FAE,
895 REG_0FBA,
896 REG_0FC7,
897 REG_VEX_0F71,
898 REG_VEX_0F72,
899 REG_VEX_0F73,
900 REG_VEX_0FAE,
901 REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
902 REG_VEX_0F38F3_L_0_P_0,
903 REG_VEX_MAP7_F8_L_0_W_0,
904
905 REG_XOP_09_01_L_0,
906 REG_XOP_09_02_L_0,
907 REG_XOP_09_12_L_0,
908 REG_XOP_0A_12_L_0,
909
910 REG_EVEX_0F71,
911 REG_EVEX_0F72,
912 REG_EVEX_0F73,
913 REG_EVEX_0F38C6_L_2,
914 REG_EVEX_0F38C7_L_2,
915 REG_EVEX_MAP4_80,
916 REG_EVEX_MAP4_81,
917 REG_EVEX_MAP4_83,
918 REG_EVEX_MAP4_8F,
919 REG_EVEX_MAP4_F6,
920 REG_EVEX_MAP4_F7,
921 REG_EVEX_MAP4_FE,
922 REG_EVEX_MAP4_FF,
923 };
924
925 enum
926 {
927 MOD_62_32BIT = 0,
928 MOD_C4_32BIT,
929 MOD_C5_32BIT,
930 MOD_0F01_REG_0,
931 MOD_0F01_REG_1,
932 MOD_0F01_REG_2,
933 MOD_0F01_REG_3,
934 MOD_0F01_REG_5,
935 MOD_0F01_REG_7,
936 MOD_0F12_PREFIX_0,
937 MOD_0F16_PREFIX_0,
938 MOD_0F18_REG_0,
939 MOD_0F18_REG_1,
940 MOD_0F18_REG_2,
941 MOD_0F18_REG_3,
942 MOD_0F18_REG_6,
943 MOD_0F18_REG_7,
944 MOD_0F1A_PREFIX_0,
945 MOD_0F1B_PREFIX_0,
946 MOD_0F1B_PREFIX_1,
947 MOD_0F1C_PREFIX_0,
948 MOD_0F1E_PREFIX_1,
949 MOD_0FAE_REG_0,
950 MOD_0FAE_REG_1,
951 MOD_0FAE_REG_2,
952 MOD_0FAE_REG_3,
953 MOD_0FAE_REG_4,
954 MOD_0FAE_REG_5,
955 MOD_0FAE_REG_6,
956 MOD_0FAE_REG_7,
957 MOD_0FC7_REG_6,
958 MOD_0FC7_REG_7,
959 MOD_0F38DC_PREFIX_1,
960 MOD_0F38F8,
961
962 MOD_VEX_0F3849_X86_64_L_0_W_0,
963
964 MOD_EVEX_MAP4_60,
965 MOD_EVEX_MAP4_61,
966 MOD_EVEX_MAP4_F8_P_1,
967 MOD_EVEX_MAP4_F8_P_3,
968 };
969
970 enum
971 {
972 RM_C6_REG_7 = 0,
973 RM_C7_REG_7,
974 RM_0F01_REG_0,
975 RM_0F01_REG_1,
976 RM_0F01_REG_2,
977 RM_0F01_REG_3,
978 RM_0F01_REG_5_MOD_3,
979 RM_0F01_REG_7_MOD_3,
980 RM_0F1E_P_1_MOD_3_REG_7,
981 RM_0FAE_REG_6_MOD_3_P_0,
982 RM_0FAE_REG_7_MOD_3,
983 RM_0F3A0F_P_1_R_0,
984
985 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
986 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
987 };
988
989 enum
990 {
991 PREFIX_90 = 0,
992 PREFIX_0F00_REG_6_X86_64,
993 PREFIX_0F01_REG_0_MOD_3_RM_6,
994 PREFIX_0F01_REG_0_MOD_3_RM_7,
995 PREFIX_0F01_REG_1_RM_2,
996 PREFIX_0F01_REG_1_RM_4,
997 PREFIX_0F01_REG_1_RM_5,
998 PREFIX_0F01_REG_1_RM_6,
999 PREFIX_0F01_REG_1_RM_7,
1000 PREFIX_0F01_REG_3_RM_1,
1001 PREFIX_0F01_REG_5_MOD_0,
1002 PREFIX_0F01_REG_5_MOD_3_RM_0,
1003 PREFIX_0F01_REG_5_MOD_3_RM_1,
1004 PREFIX_0F01_REG_5_MOD_3_RM_2,
1005 PREFIX_0F01_REG_5_MOD_3_RM_4,
1006 PREFIX_0F01_REG_5_MOD_3_RM_5,
1007 PREFIX_0F01_REG_5_MOD_3_RM_6,
1008 PREFIX_0F01_REG_5_MOD_3_RM_7,
1009 PREFIX_0F01_REG_7_MOD_3_RM_2,
1010 PREFIX_0F01_REG_7_MOD_3_RM_5,
1011 PREFIX_0F01_REG_7_MOD_3_RM_6,
1012 PREFIX_0F01_REG_7_MOD_3_RM_7,
1013 PREFIX_0F09,
1014 PREFIX_0F10,
1015 PREFIX_0F11,
1016 PREFIX_0F12,
1017 PREFIX_0F16,
1018 PREFIX_0F18_REG_6_MOD_0_X86_64,
1019 PREFIX_0F18_REG_7_MOD_0_X86_64,
1020 PREFIX_0F1A,
1021 PREFIX_0F1B,
1022 PREFIX_0F1C,
1023 PREFIX_0F1E,
1024 PREFIX_0F2A,
1025 PREFIX_0F2B,
1026 PREFIX_0F2C,
1027 PREFIX_0F2D,
1028 PREFIX_0F2E,
1029 PREFIX_0F2F,
1030 PREFIX_0F51,
1031 PREFIX_0F52,
1032 PREFIX_0F53,
1033 PREFIX_0F58,
1034 PREFIX_0F59,
1035 PREFIX_0F5A,
1036 PREFIX_0F5B,
1037 PREFIX_0F5C,
1038 PREFIX_0F5D,
1039 PREFIX_0F5E,
1040 PREFIX_0F5F,
1041 PREFIX_0F60,
1042 PREFIX_0F61,
1043 PREFIX_0F62,
1044 PREFIX_0F6F,
1045 PREFIX_0F70,
1046 PREFIX_0F78,
1047 PREFIX_0F79,
1048 PREFIX_0F7C,
1049 PREFIX_0F7D,
1050 PREFIX_0F7E,
1051 PREFIX_0F7F,
1052 PREFIX_0FAE_REG_0_MOD_3,
1053 PREFIX_0FAE_REG_1_MOD_3,
1054 PREFIX_0FAE_REG_2_MOD_3,
1055 PREFIX_0FAE_REG_3_MOD_3,
1056 PREFIX_0FAE_REG_4_MOD_0,
1057 PREFIX_0FAE_REG_4_MOD_3,
1058 PREFIX_0FAE_REG_5_MOD_3,
1059 PREFIX_0FAE_REG_6_MOD_0,
1060 PREFIX_0FAE_REG_6_MOD_3,
1061 PREFIX_0FAE_REG_7_MOD_0,
1062 PREFIX_0FB8,
1063 PREFIX_0FBC,
1064 PREFIX_0FBD,
1065 PREFIX_0FC2,
1066 PREFIX_0FC7_REG_6_MOD_0,
1067 PREFIX_0FC7_REG_6_MOD_3,
1068 PREFIX_0FC7_REG_7_MOD_3,
1069 PREFIX_0FD0,
1070 PREFIX_0FD6,
1071 PREFIX_0FE6,
1072 PREFIX_0FE7,
1073 PREFIX_0FF0,
1074 PREFIX_0FF7,
1075 PREFIX_0F38D8,
1076 PREFIX_0F38DC,
1077 PREFIX_0F38DD,
1078 PREFIX_0F38DE,
1079 PREFIX_0F38DF,
1080 PREFIX_0F38F0,
1081 PREFIX_0F38F1,
1082 PREFIX_0F38F6,
1083 PREFIX_0F38F8_M_0,
1084 PREFIX_0F38F8_M_1_X86_64,
1085 PREFIX_0F38FA,
1086 PREFIX_0F38FB,
1087 PREFIX_0F38FC,
1088 PREFIX_0F3A0F,
1089 PREFIX_VEX_0F12,
1090 PREFIX_VEX_0F16,
1091 PREFIX_VEX_0F2A,
1092 PREFIX_VEX_0F2C,
1093 PREFIX_VEX_0F2D,
1094 PREFIX_VEX_0F41_L_1_W_0,
1095 PREFIX_VEX_0F41_L_1_W_1,
1096 PREFIX_VEX_0F42_L_1_W_0,
1097 PREFIX_VEX_0F42_L_1_W_1,
1098 PREFIX_VEX_0F44_L_0_W_0,
1099 PREFIX_VEX_0F44_L_0_W_1,
1100 PREFIX_VEX_0F45_L_1_W_0,
1101 PREFIX_VEX_0F45_L_1_W_1,
1102 PREFIX_VEX_0F46_L_1_W_0,
1103 PREFIX_VEX_0F46_L_1_W_1,
1104 PREFIX_VEX_0F47_L_1_W_0,
1105 PREFIX_VEX_0F47_L_1_W_1,
1106 PREFIX_VEX_0F4A_L_1_W_0,
1107 PREFIX_VEX_0F4A_L_1_W_1,
1108 PREFIX_VEX_0F4B_L_1_W_0,
1109 PREFIX_VEX_0F4B_L_1_W_1,
1110 PREFIX_VEX_0F6F,
1111 PREFIX_VEX_0F70,
1112 PREFIX_VEX_0F7E,
1113 PREFIX_VEX_0F7F,
1114 PREFIX_VEX_0F90_L_0_W_0,
1115 PREFIX_VEX_0F90_L_0_W_1,
1116 PREFIX_VEX_0F91_L_0_W_0,
1117 PREFIX_VEX_0F91_L_0_W_1,
1118 PREFIX_VEX_0F92_L_0_W_0,
1119 PREFIX_VEX_0F92_L_0_W_1,
1120 PREFIX_VEX_0F93_L_0_W_0,
1121 PREFIX_VEX_0F93_L_0_W_1,
1122 PREFIX_VEX_0F98_L_0_W_0,
1123 PREFIX_VEX_0F98_L_0_W_1,
1124 PREFIX_VEX_0F99_L_0_W_0,
1125 PREFIX_VEX_0F99_L_0_W_1,
1126 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1127 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1128 PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1129 PREFIX_VEX_0F3850_W_0,
1130 PREFIX_VEX_0F3851_W_0,
1131 PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1132 PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1133 PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1134 PREFIX_VEX_0F3872,
1135 PREFIX_VEX_0F38B0_W_0,
1136 PREFIX_VEX_0F38B1_W_0,
1137 PREFIX_VEX_0F38D2_W_0,
1138 PREFIX_VEX_0F38D3_W_0,
1139 PREFIX_VEX_0F38CB,
1140 PREFIX_VEX_0F38CC,
1141 PREFIX_VEX_0F38CD,
1142 PREFIX_VEX_0F38DA_W_0,
1143 PREFIX_VEX_0F38F2_L_0,
1144 PREFIX_VEX_0F38F3_L_0,
1145 PREFIX_VEX_0F38F5_L_0,
1146 PREFIX_VEX_0F38F6_L_0,
1147 PREFIX_VEX_0F38F7_L_0,
1148 PREFIX_VEX_0F3AF0_L_0,
1149 PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1150
1151 PREFIX_EVEX_0F5B,
1152 PREFIX_EVEX_0F6F,
1153 PREFIX_EVEX_0F70,
1154 PREFIX_EVEX_0F78,
1155 PREFIX_EVEX_0F79,
1156 PREFIX_EVEX_0F7A,
1157 PREFIX_EVEX_0F7B,
1158 PREFIX_EVEX_0F7E,
1159 PREFIX_EVEX_0F7F,
1160 PREFIX_EVEX_0FC2,
1161 PREFIX_EVEX_0FE6,
1162 PREFIX_EVEX_0F3810,
1163 PREFIX_EVEX_0F3811,
1164 PREFIX_EVEX_0F3812,
1165 PREFIX_EVEX_0F3813,
1166 PREFIX_EVEX_0F3814,
1167 PREFIX_EVEX_0F3815,
1168 PREFIX_EVEX_0F3820,
1169 PREFIX_EVEX_0F3821,
1170 PREFIX_EVEX_0F3822,
1171 PREFIX_EVEX_0F3823,
1172 PREFIX_EVEX_0F3824,
1173 PREFIX_EVEX_0F3825,
1174 PREFIX_EVEX_0F3826,
1175 PREFIX_EVEX_0F3827,
1176 PREFIX_EVEX_0F3828,
1177 PREFIX_EVEX_0F3829,
1178 PREFIX_EVEX_0F382A,
1179 PREFIX_EVEX_0F3830,
1180 PREFIX_EVEX_0F3831,
1181 PREFIX_EVEX_0F3832,
1182 PREFIX_EVEX_0F3833,
1183 PREFIX_EVEX_0F3834,
1184 PREFIX_EVEX_0F3835,
1185 PREFIX_EVEX_0F3838,
1186 PREFIX_EVEX_0F3839,
1187 PREFIX_EVEX_0F383A,
1188 PREFIX_EVEX_0F3852,
1189 PREFIX_EVEX_0F3853,
1190 PREFIX_EVEX_0F3868,
1191 PREFIX_EVEX_0F3872,
1192 PREFIX_EVEX_0F389A,
1193 PREFIX_EVEX_0F389B,
1194 PREFIX_EVEX_0F38AA,
1195 PREFIX_EVEX_0F38AB,
1196
1197 PREFIX_EVEX_0F3A08,
1198 PREFIX_EVEX_0F3A0A,
1199 PREFIX_EVEX_0F3A26,
1200 PREFIX_EVEX_0F3A27,
1201 PREFIX_EVEX_0F3A56,
1202 PREFIX_EVEX_0F3A57,
1203 PREFIX_EVEX_0F3A66,
1204 PREFIX_EVEX_0F3A67,
1205 PREFIX_EVEX_0F3AC2,
1206
1207 PREFIX_EVEX_MAP4_4x,
1208 PREFIX_EVEX_MAP4_F0,
1209 PREFIX_EVEX_MAP4_F1,
1210 PREFIX_EVEX_MAP4_F2,
1211 PREFIX_EVEX_MAP4_F8,
1212
1213 PREFIX_EVEX_MAP5_10,
1214 PREFIX_EVEX_MAP5_11,
1215 PREFIX_EVEX_MAP5_1D,
1216 PREFIX_EVEX_MAP5_2A,
1217 PREFIX_EVEX_MAP5_2C,
1218 PREFIX_EVEX_MAP5_2D,
1219 PREFIX_EVEX_MAP5_2E,
1220 PREFIX_EVEX_MAP5_2F,
1221 PREFIX_EVEX_MAP5_51,
1222 PREFIX_EVEX_MAP5_58,
1223 PREFIX_EVEX_MAP5_59,
1224 PREFIX_EVEX_MAP5_5A,
1225 PREFIX_EVEX_MAP5_5B,
1226 PREFIX_EVEX_MAP5_5C,
1227 PREFIX_EVEX_MAP5_5D,
1228 PREFIX_EVEX_MAP5_5E,
1229 PREFIX_EVEX_MAP5_5F,
1230 PREFIX_EVEX_MAP5_78,
1231 PREFIX_EVEX_MAP5_79,
1232 PREFIX_EVEX_MAP5_7A,
1233 PREFIX_EVEX_MAP5_7B,
1234 PREFIX_EVEX_MAP5_7C,
1235 PREFIX_EVEX_MAP5_7D,
1236
1237 PREFIX_EVEX_MAP6_13,
1238 PREFIX_EVEX_MAP6_56,
1239 PREFIX_EVEX_MAP6_57,
1240 PREFIX_EVEX_MAP6_D6,
1241 PREFIX_EVEX_MAP6_D7,
1242 };
1243
1244 enum
1245 {
1246 X86_64_06 = 0,
1247 X86_64_07,
1248 X86_64_0E,
1249 X86_64_16,
1250 X86_64_17,
1251 X86_64_1E,
1252 X86_64_1F,
1253 X86_64_27,
1254 X86_64_2F,
1255 X86_64_37,
1256 X86_64_3F,
1257 X86_64_60,
1258 X86_64_61,
1259 X86_64_62,
1260 X86_64_63,
1261 X86_64_6D,
1262 X86_64_6F,
1263 X86_64_82,
1264 X86_64_9A,
1265 X86_64_C2,
1266 X86_64_C3,
1267 X86_64_C4,
1268 X86_64_C5,
1269 X86_64_CE,
1270 X86_64_D4,
1271 X86_64_D5,
1272 X86_64_E8,
1273 X86_64_E9,
1274 X86_64_EA,
1275 X86_64_0F00_REG_6,
1276 X86_64_0F01_REG_0,
1277 X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1278 X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1279 X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1280 X86_64_0F01_REG_1,
1281 X86_64_0F01_REG_1_RM_2_PREFIX_1,
1282 X86_64_0F01_REG_1_RM_2_PREFIX_3,
1283 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1284 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1285 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1286 X86_64_0F01_REG_2,
1287 X86_64_0F01_REG_3,
1288 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1289 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1290 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1291 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1292 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1293 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1294 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1295 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1296 X86_64_0F18_REG_6_MOD_0,
1297 X86_64_0F18_REG_7_MOD_0,
1298 X86_64_0F24,
1299 X86_64_0F26,
1300 X86_64_0F38F8_M_1,
1301 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1302
1303 X86_64_VEX_0F3849,
1304 X86_64_VEX_0F384B,
1305 X86_64_VEX_0F385C,
1306 X86_64_VEX_0F385E,
1307 X86_64_VEX_0F386C,
1308 X86_64_VEX_0F38Ex,
1309
1310 X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1311 };
1312
1313 enum
1314 {
1315 THREE_BYTE_0F38 = 0,
1316 THREE_BYTE_0F3A
1317 };
1318
1319 enum
1320 {
1321 XOP_08 = 0,
1322 XOP_09,
1323 XOP_0A
1324 };
1325
1326 enum
1327 {
1328 VEX_0F = 0,
1329 VEX_0F38,
1330 VEX_0F3A,
1331 VEX_MAP7,
1332 };
1333
1334 enum
1335 {
1336 EVEX_0F = 0,
1337 EVEX_0F38,
1338 EVEX_0F3A,
1339 EVEX_MAP4,
1340 EVEX_MAP5,
1341 EVEX_MAP6,
1342 EVEX_MAP7,
1343 };
1344
1345 enum
1346 {
1347 VEX_LEN_0F12_P_0 = 0,
1348 VEX_LEN_0F12_P_2,
1349 VEX_LEN_0F13,
1350 VEX_LEN_0F16_P_0,
1351 VEX_LEN_0F16_P_2,
1352 VEX_LEN_0F17,
1353 VEX_LEN_0F41,
1354 VEX_LEN_0F42,
1355 VEX_LEN_0F44,
1356 VEX_LEN_0F45,
1357 VEX_LEN_0F46,
1358 VEX_LEN_0F47,
1359 VEX_LEN_0F4A,
1360 VEX_LEN_0F4B,
1361 VEX_LEN_0F6E,
1362 VEX_LEN_0F77,
1363 VEX_LEN_0F7E_P_1,
1364 VEX_LEN_0F7E_P_2,
1365 VEX_LEN_0F90,
1366 VEX_LEN_0F91,
1367 VEX_LEN_0F92,
1368 VEX_LEN_0F93,
1369 VEX_LEN_0F98,
1370 VEX_LEN_0F99,
1371 VEX_LEN_0FAE_R_2,
1372 VEX_LEN_0FAE_R_3,
1373 VEX_LEN_0FC4,
1374 VEX_LEN_0FD6,
1375 VEX_LEN_0F3816,
1376 VEX_LEN_0F3819,
1377 VEX_LEN_0F381A,
1378 VEX_LEN_0F3836,
1379 VEX_LEN_0F3841,
1380 VEX_LEN_0F3849_X86_64,
1381 VEX_LEN_0F384B_X86_64,
1382 VEX_LEN_0F385A,
1383 VEX_LEN_0F385C_X86_64,
1384 VEX_LEN_0F385E_X86_64,
1385 VEX_LEN_0F386C_X86_64,
1386 VEX_LEN_0F38CB_P_3_W_0,
1387 VEX_LEN_0F38CC_P_3_W_0,
1388 VEX_LEN_0F38CD_P_3_W_0,
1389 VEX_LEN_0F38DA_W_0_P_0,
1390 VEX_LEN_0F38DA_W_0_P_2,
1391 VEX_LEN_0F38DB,
1392 VEX_LEN_0F38F2,
1393 VEX_LEN_0F38F3,
1394 VEX_LEN_0F38F5,
1395 VEX_LEN_0F38F6,
1396 VEX_LEN_0F38F7,
1397 VEX_LEN_0F3A00,
1398 VEX_LEN_0F3A01,
1399 VEX_LEN_0F3A06,
1400 VEX_LEN_0F3A14,
1401 VEX_LEN_0F3A15,
1402 VEX_LEN_0F3A16,
1403 VEX_LEN_0F3A17,
1404 VEX_LEN_0F3A18,
1405 VEX_LEN_0F3A19,
1406 VEX_LEN_0F3A20,
1407 VEX_LEN_0F3A21,
1408 VEX_LEN_0F3A22,
1409 VEX_LEN_0F3A30,
1410 VEX_LEN_0F3A31,
1411 VEX_LEN_0F3A32,
1412 VEX_LEN_0F3A33,
1413 VEX_LEN_0F3A38,
1414 VEX_LEN_0F3A39,
1415 VEX_LEN_0F3A41,
1416 VEX_LEN_0F3A46,
1417 VEX_LEN_0F3A60,
1418 VEX_LEN_0F3A61,
1419 VEX_LEN_0F3A62,
1420 VEX_LEN_0F3A63,
1421 VEX_LEN_0F3ADE_W_0,
1422 VEX_LEN_0F3ADF,
1423 VEX_LEN_0F3AF0,
1424 VEX_LEN_MAP7_F8,
1425 VEX_LEN_XOP_08_85,
1426 VEX_LEN_XOP_08_86,
1427 VEX_LEN_XOP_08_87,
1428 VEX_LEN_XOP_08_8E,
1429 VEX_LEN_XOP_08_8F,
1430 VEX_LEN_XOP_08_95,
1431 VEX_LEN_XOP_08_96,
1432 VEX_LEN_XOP_08_97,
1433 VEX_LEN_XOP_08_9E,
1434 VEX_LEN_XOP_08_9F,
1435 VEX_LEN_XOP_08_A3,
1436 VEX_LEN_XOP_08_A6,
1437 VEX_LEN_XOP_08_B6,
1438 VEX_LEN_XOP_08_C0,
1439 VEX_LEN_XOP_08_C1,
1440 VEX_LEN_XOP_08_C2,
1441 VEX_LEN_XOP_08_C3,
1442 VEX_LEN_XOP_08_CC,
1443 VEX_LEN_XOP_08_CD,
1444 VEX_LEN_XOP_08_CE,
1445 VEX_LEN_XOP_08_CF,
1446 VEX_LEN_XOP_08_EC,
1447 VEX_LEN_XOP_08_ED,
1448 VEX_LEN_XOP_08_EE,
1449 VEX_LEN_XOP_08_EF,
1450 VEX_LEN_XOP_09_01,
1451 VEX_LEN_XOP_09_02,
1452 VEX_LEN_XOP_09_12,
1453 VEX_LEN_XOP_09_82_W_0,
1454 VEX_LEN_XOP_09_83_W_0,
1455 VEX_LEN_XOP_09_90,
1456 VEX_LEN_XOP_09_91,
1457 VEX_LEN_XOP_09_92,
1458 VEX_LEN_XOP_09_93,
1459 VEX_LEN_XOP_09_94,
1460 VEX_LEN_XOP_09_95,
1461 VEX_LEN_XOP_09_96,
1462 VEX_LEN_XOP_09_97,
1463 VEX_LEN_XOP_09_98,
1464 VEX_LEN_XOP_09_99,
1465 VEX_LEN_XOP_09_9A,
1466 VEX_LEN_XOP_09_9B,
1467 VEX_LEN_XOP_09_C1,
1468 VEX_LEN_XOP_09_C2,
1469 VEX_LEN_XOP_09_C3,
1470 VEX_LEN_XOP_09_C6,
1471 VEX_LEN_XOP_09_C7,
1472 VEX_LEN_XOP_09_CB,
1473 VEX_LEN_XOP_09_D1,
1474 VEX_LEN_XOP_09_D2,
1475 VEX_LEN_XOP_09_D3,
1476 VEX_LEN_XOP_09_D6,
1477 VEX_LEN_XOP_09_D7,
1478 VEX_LEN_XOP_09_DB,
1479 VEX_LEN_XOP_09_E1,
1480 VEX_LEN_XOP_09_E2,
1481 VEX_LEN_XOP_09_E3,
1482 VEX_LEN_XOP_0A_12,
1483 };
1484
1485 enum
1486 {
1487 EVEX_LEN_0F3816 = 0,
1488 EVEX_LEN_0F3819,
1489 EVEX_LEN_0F381A,
1490 EVEX_LEN_0F381B,
1491 EVEX_LEN_0F3836,
1492 EVEX_LEN_0F385A,
1493 EVEX_LEN_0F385B,
1494 EVEX_LEN_0F38C6,
1495 EVEX_LEN_0F38C7,
1496 EVEX_LEN_0F3A00,
1497 EVEX_LEN_0F3A01,
1498 EVEX_LEN_0F3A18,
1499 EVEX_LEN_0F3A19,
1500 EVEX_LEN_0F3A1A,
1501 EVEX_LEN_0F3A1B,
1502 EVEX_LEN_0F3A23,
1503 EVEX_LEN_0F3A38,
1504 EVEX_LEN_0F3A39,
1505 EVEX_LEN_0F3A3A,
1506 EVEX_LEN_0F3A3B,
1507 EVEX_LEN_0F3A43
1508 };
1509
1510 enum
1511 {
1512 VEX_W_0F41_L_1 = 0,
1513 VEX_W_0F42_L_1,
1514 VEX_W_0F44_L_0,
1515 VEX_W_0F45_L_1,
1516 VEX_W_0F46_L_1,
1517 VEX_W_0F47_L_1,
1518 VEX_W_0F4A_L_1,
1519 VEX_W_0F4B_L_1,
1520 VEX_W_0F90_L_0,
1521 VEX_W_0F91_L_0,
1522 VEX_W_0F92_L_0,
1523 VEX_W_0F93_L_0,
1524 VEX_W_0F98_L_0,
1525 VEX_W_0F99_L_0,
1526 VEX_W_0F380C,
1527 VEX_W_0F380D,
1528 VEX_W_0F380E,
1529 VEX_W_0F380F,
1530 VEX_W_0F3813,
1531 VEX_W_0F3816_L_1,
1532 VEX_W_0F3818,
1533 VEX_W_0F3819_L_1,
1534 VEX_W_0F381A_L_1,
1535 VEX_W_0F382C,
1536 VEX_W_0F382D,
1537 VEX_W_0F382E,
1538 VEX_W_0F382F,
1539 VEX_W_0F3836,
1540 VEX_W_0F3846,
1541 VEX_W_0F3849_X86_64_L_0,
1542 VEX_W_0F384B_X86_64_L_0,
1543 VEX_W_0F3850,
1544 VEX_W_0F3851,
1545 VEX_W_0F3852,
1546 VEX_W_0F3853,
1547 VEX_W_0F3858,
1548 VEX_W_0F3859,
1549 VEX_W_0F385A_L_0,
1550 VEX_W_0F385C_X86_64_L_0,
1551 VEX_W_0F385E_X86_64_L_0,
1552 VEX_W_0F386C_X86_64_L_0,
1553 VEX_W_0F3872_P_1,
1554 VEX_W_0F3878,
1555 VEX_W_0F3879,
1556 VEX_W_0F38B0,
1557 VEX_W_0F38B1,
1558 VEX_W_0F38B4,
1559 VEX_W_0F38B5,
1560 VEX_W_0F38CB_P_3,
1561 VEX_W_0F38CC_P_3,
1562 VEX_W_0F38CD_P_3,
1563 VEX_W_0F38CF,
1564 VEX_W_0F38D2,
1565 VEX_W_0F38D3,
1566 VEX_W_0F38DA,
1567 VEX_W_0F3A00_L_1,
1568 VEX_W_0F3A01_L_1,
1569 VEX_W_0F3A02,
1570 VEX_W_0F3A04,
1571 VEX_W_0F3A05,
1572 VEX_W_0F3A06_L_1,
1573 VEX_W_0F3A18_L_1,
1574 VEX_W_0F3A19_L_1,
1575 VEX_W_0F3A1D,
1576 VEX_W_0F3A38_L_1,
1577 VEX_W_0F3A39_L_1,
1578 VEX_W_0F3A46_L_1,
1579 VEX_W_0F3A4A,
1580 VEX_W_0F3A4B,
1581 VEX_W_0F3A4C,
1582 VEX_W_0F3ACE,
1583 VEX_W_0F3ACF,
1584 VEX_W_0F3ADE,
1585 VEX_W_MAP7_F8_L_0,
1586
1587 VEX_W_XOP_08_85_L_0,
1588 VEX_W_XOP_08_86_L_0,
1589 VEX_W_XOP_08_87_L_0,
1590 VEX_W_XOP_08_8E_L_0,
1591 VEX_W_XOP_08_8F_L_0,
1592 VEX_W_XOP_08_95_L_0,
1593 VEX_W_XOP_08_96_L_0,
1594 VEX_W_XOP_08_97_L_0,
1595 VEX_W_XOP_08_9E_L_0,
1596 VEX_W_XOP_08_9F_L_0,
1597 VEX_W_XOP_08_A6_L_0,
1598 VEX_W_XOP_08_B6_L_0,
1599 VEX_W_XOP_08_C0_L_0,
1600 VEX_W_XOP_08_C1_L_0,
1601 VEX_W_XOP_08_C2_L_0,
1602 VEX_W_XOP_08_C3_L_0,
1603 VEX_W_XOP_08_CC_L_0,
1604 VEX_W_XOP_08_CD_L_0,
1605 VEX_W_XOP_08_CE_L_0,
1606 VEX_W_XOP_08_CF_L_0,
1607 VEX_W_XOP_08_EC_L_0,
1608 VEX_W_XOP_08_ED_L_0,
1609 VEX_W_XOP_08_EE_L_0,
1610 VEX_W_XOP_08_EF_L_0,
1611
1612 VEX_W_XOP_09_80,
1613 VEX_W_XOP_09_81,
1614 VEX_W_XOP_09_82,
1615 VEX_W_XOP_09_83,
1616 VEX_W_XOP_09_C1_L_0,
1617 VEX_W_XOP_09_C2_L_0,
1618 VEX_W_XOP_09_C3_L_0,
1619 VEX_W_XOP_09_C6_L_0,
1620 VEX_W_XOP_09_C7_L_0,
1621 VEX_W_XOP_09_CB_L_0,
1622 VEX_W_XOP_09_D1_L_0,
1623 VEX_W_XOP_09_D2_L_0,
1624 VEX_W_XOP_09_D3_L_0,
1625 VEX_W_XOP_09_D6_L_0,
1626 VEX_W_XOP_09_D7_L_0,
1627 VEX_W_XOP_09_DB_L_0,
1628 VEX_W_XOP_09_E1_L_0,
1629 VEX_W_XOP_09_E2_L_0,
1630 VEX_W_XOP_09_E3_L_0,
1631
1632 EVEX_W_0F5B_P_0,
1633 EVEX_W_0F62,
1634 EVEX_W_0F66,
1635 EVEX_W_0F6A,
1636 EVEX_W_0F6B,
1637 EVEX_W_0F6C,
1638 EVEX_W_0F6D,
1639 EVEX_W_0F6F_P_1,
1640 EVEX_W_0F6F_P_2,
1641 EVEX_W_0F6F_P_3,
1642 EVEX_W_0F70_P_2,
1643 EVEX_W_0F72_R_2,
1644 EVEX_W_0F72_R_6,
1645 EVEX_W_0F73_R_2,
1646 EVEX_W_0F73_R_6,
1647 EVEX_W_0F76,
1648 EVEX_W_0F78_P_0,
1649 EVEX_W_0F78_P_2,
1650 EVEX_W_0F79_P_0,
1651 EVEX_W_0F79_P_2,
1652 EVEX_W_0F7A_P_1,
1653 EVEX_W_0F7A_P_2,
1654 EVEX_W_0F7A_P_3,
1655 EVEX_W_0F7B_P_2,
1656 EVEX_W_0F7E_P_1,
1657 EVEX_W_0F7F_P_1,
1658 EVEX_W_0F7F_P_2,
1659 EVEX_W_0F7F_P_3,
1660 EVEX_W_0FD2,
1661 EVEX_W_0FD3,
1662 EVEX_W_0FD4,
1663 EVEX_W_0FD6,
1664 EVEX_W_0FE6_P_1,
1665 EVEX_W_0FE7,
1666 EVEX_W_0FF2,
1667 EVEX_W_0FF3,
1668 EVEX_W_0FF4,
1669 EVEX_W_0FFA,
1670 EVEX_W_0FFB,
1671 EVEX_W_0FFE,
1672
1673 EVEX_W_0F3810_P_1,
1674 EVEX_W_0F3810_P_2,
1675 EVEX_W_0F3811_P_1,
1676 EVEX_W_0F3811_P_2,
1677 EVEX_W_0F3812_P_1,
1678 EVEX_W_0F3812_P_2,
1679 EVEX_W_0F3813_P_1,
1680 EVEX_W_0F3814_P_1,
1681 EVEX_W_0F3815_P_1,
1682 EVEX_W_0F3819_L_n,
1683 EVEX_W_0F381A_L_n,
1684 EVEX_W_0F381B_L_2,
1685 EVEX_W_0F381E,
1686 EVEX_W_0F381F,
1687 EVEX_W_0F3820_P_1,
1688 EVEX_W_0F3821_P_1,
1689 EVEX_W_0F3822_P_1,
1690 EVEX_W_0F3823_P_1,
1691 EVEX_W_0F3824_P_1,
1692 EVEX_W_0F3825_P_1,
1693 EVEX_W_0F3825_P_2,
1694 EVEX_W_0F3828_P_2,
1695 EVEX_W_0F3829_P_2,
1696 EVEX_W_0F382A_P_1,
1697 EVEX_W_0F382A_P_2,
1698 EVEX_W_0F382B,
1699 EVEX_W_0F3830_P_1,
1700 EVEX_W_0F3831_P_1,
1701 EVEX_W_0F3832_P_1,
1702 EVEX_W_0F3833_P_1,
1703 EVEX_W_0F3834_P_1,
1704 EVEX_W_0F3835_P_1,
1705 EVEX_W_0F3835_P_2,
1706 EVEX_W_0F3837,
1707 EVEX_W_0F383A_P_1,
1708 EVEX_W_0F3859,
1709 EVEX_W_0F385A_L_n,
1710 EVEX_W_0F385B_L_2,
1711 EVEX_W_0F3870,
1712 EVEX_W_0F3872_P_2,
1713 EVEX_W_0F387A,
1714 EVEX_W_0F387B,
1715 EVEX_W_0F3883,
1716
1717 EVEX_W_0F3A18_L_n,
1718 EVEX_W_0F3A19_L_n,
1719 EVEX_W_0F3A1A_L_2,
1720 EVEX_W_0F3A1B_L_2,
1721 EVEX_W_0F3A21,
1722 EVEX_W_0F3A23_L_n,
1723 EVEX_W_0F3A38_L_n,
1724 EVEX_W_0F3A39_L_n,
1725 EVEX_W_0F3A3A_L_2,
1726 EVEX_W_0F3A3B_L_2,
1727 EVEX_W_0F3A42,
1728 EVEX_W_0F3A43_L_n,
1729 EVEX_W_0F3A70,
1730 EVEX_W_0F3A72,
1731
1732 EVEX_W_MAP4_8F_R_0,
1733 EVEX_W_MAP4_F8_P1_M_1,
1734 EVEX_W_MAP4_F8_P3_M_1,
1735 EVEX_W_MAP4_FF_R_6,
1736
1737 EVEX_W_MAP5_5B_P_0,
1738 EVEX_W_MAP5_7A_P_3,
1739 };
1740
1741 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1742
1743 struct dis386 {
1744 const char *name;
1745 struct
1746 {
1747 op_rtn rtn;
1748 int bytemode;
1749 } op[MAX_OPERANDS];
1750 unsigned int prefix_requirement;
1751 };
1752
1753 /* Upper case letters in the instruction names here are macros.
1754 'A' => print 'b' if no (suitable) register operand or suffix_always is true
1755 'B' => print 'b' if suffix_always is true
1756 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1757 size prefix
1758 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1759 suffix_always is true
1760 'E' => print 'e' if 32-bit form of jcxz
1761 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1762 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1763 'H' => print ",pt" or ",pn" branch hint
1764 'I' unused.
1765 'J' unused.
1766 'K' => print 'd' or 'q' if rex prefix is present.
1767 'L' => print 'l' or 'q' if suffix_always is true
1768 'M' => print 'r' if intel_mnemonic is false.
1769 'N' => print 'n' if instruction has no wait "prefix"
1770 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1771 'P' => behave as 'T' except with register operand outside of suffix_always
1772 mode
1773 'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1774 suffix_always is true
1775 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1776 'S' => print 'w', 'l' or 'q' if suffix_always is true
1777 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1778 prefix or if suffix_always is true.
1779 'U' unused.
1780 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1781 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1782 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1783 'Y' => no output, mark EVEX.aaa != 0 as bad.
1784 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1785 '!' => change condition from true to false or from false to true.
1786 '%' => add 1 upper case letter to the macro.
1787 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1788 prefix or suffix_always is true (lcall/ljmp).
1789 '@' => in 64bit mode for Intel64 ISA or if instruction
1790 has no operand sizing prefix, print 'q' if suffix_always is true or
1791 nothing otherwise; behave as 'P' in all other cases
1792
1793 2 upper case letter macros:
1794 "CC" => print condition code
1795 "XY" => print 'x' or 'y' if suffix_always is true or no register
1796 operands and no broadcast.
1797 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1798 register operands and no broadcast.
1799 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1800 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1801 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1802 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1803 "XV" => print "{vex} " pseudo prefix
1804 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1805 is used by an EVEX-encoded (AVX512VL) instruction.
1806 "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
1807 pseudo prefix when instructions without NF, EGPR and VVVV,
1808 "NE" => don't print "{evex} " pseudo prefix for some special instructions
1809 in MAP4.
1810 "ZU" => print 'zu' if EVEX.ZU=1.
1811 "SC" => print suffix SCC for SCC insns
1812 "SW" => print '.s' to indicate operands were swapped when suffix_always is
1813 true.
1814 "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1815 "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1816 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1817 being false, or no operand at all in 64bit mode, or if suffix_always
1818 is true.
1819 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1820 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1821 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1822 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1823 "DF" => print default flag value for SCC insns
1824 "BW" => print 'b' or 'w' depending on the VEX.W bit
1825 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1826 an operand size prefix, or suffix_always is true. print
1827 'q' if rex prefix is present.
1828
1829 Many of the above letters print nothing in Intel mode. See "putop"
1830 for the details.
1831
1832 Braces '{' and '}', and vertical bars '|', indicate alternative
1833 mnemonic strings for AT&T and Intel. */
1834
1835 static const struct dis386 dis386[] = {
1836 /* 00 */
1837 { "addB", { Ebh1, Gb }, 0 },
1838 { "addS", { Evh1, Gv }, 0 },
1839 { "addB", { Gb, EbS }, 0 },
1840 { "addS", { Gv, EvS }, 0 },
1841 { "addB", { AL, Ib }, 0 },
1842 { "addS", { eAX, Iv }, 0 },
1843 { X86_64_TABLE (X86_64_06) },
1844 { X86_64_TABLE (X86_64_07) },
1845 /* 08 */
1846 { "orB", { Ebh1, Gb }, 0 },
1847 { "orS", { Evh1, Gv }, 0 },
1848 { "orB", { Gb, EbS }, 0 },
1849 { "orS", { Gv, EvS }, 0 },
1850 { "orB", { AL, Ib }, 0 },
1851 { "orS", { eAX, Iv }, 0 },
1852 { X86_64_TABLE (X86_64_0E) },
1853 { Bad_Opcode }, /* 0x0f extended opcode escape */
1854 /* 10 */
1855 { "adcB", { Ebh1, Gb }, 0 },
1856 { "adcS", { Evh1, Gv }, 0 },
1857 { "adcB", { Gb, EbS }, 0 },
1858 { "adcS", { Gv, EvS }, 0 },
1859 { "adcB", { AL, Ib }, 0 },
1860 { "adcS", { eAX, Iv }, 0 },
1861 { X86_64_TABLE (X86_64_16) },
1862 { X86_64_TABLE (X86_64_17) },
1863 /* 18 */
1864 { "sbbB", { Ebh1, Gb }, 0 },
1865 { "sbbS", { Evh1, Gv }, 0 },
1866 { "sbbB", { Gb, EbS }, 0 },
1867 { "sbbS", { Gv, EvS }, 0 },
1868 { "sbbB", { AL, Ib }, 0 },
1869 { "sbbS", { eAX, Iv }, 0 },
1870 { X86_64_TABLE (X86_64_1E) },
1871 { X86_64_TABLE (X86_64_1F) },
1872 /* 20 */
1873 { "andB", { Ebh1, Gb }, 0 },
1874 { "andS", { Evh1, Gv }, 0 },
1875 { "andB", { Gb, EbS }, 0 },
1876 { "andS", { Gv, EvS }, 0 },
1877 { "andB", { AL, Ib }, 0 },
1878 { "andS", { eAX, Iv }, 0 },
1879 { Bad_Opcode }, /* SEG ES prefix */
1880 { X86_64_TABLE (X86_64_27) },
1881 /* 28 */
1882 { "subB", { Ebh1, Gb }, 0 },
1883 { "subS", { Evh1, Gv }, 0 },
1884 { "subB", { Gb, EbS }, 0 },
1885 { "subS", { Gv, EvS }, 0 },
1886 { "subB", { AL, Ib }, 0 },
1887 { "subS", { eAX, Iv }, 0 },
1888 { Bad_Opcode }, /* SEG CS prefix */
1889 { X86_64_TABLE (X86_64_2F) },
1890 /* 30 */
1891 { "xorB", { Ebh1, Gb }, 0 },
1892 { "xorS", { Evh1, Gv }, 0 },
1893 { "xorB", { Gb, EbS }, 0 },
1894 { "xorS", { Gv, EvS }, 0 },
1895 { "xorB", { AL, Ib }, 0 },
1896 { "xorS", { eAX, Iv }, 0 },
1897 { Bad_Opcode }, /* SEG SS prefix */
1898 { X86_64_TABLE (X86_64_37) },
1899 /* 38 */
1900 { "cmpB", { Eb, Gb }, 0 },
1901 { "cmpS", { Ev, Gv }, 0 },
1902 { "cmpB", { Gb, EbS }, 0 },
1903 { "cmpS", { Gv, EvS }, 0 },
1904 { "cmpB", { AL, Ib }, 0 },
1905 { "cmpS", { eAX, Iv }, 0 },
1906 { Bad_Opcode }, /* SEG DS prefix */
1907 { X86_64_TABLE (X86_64_3F) },
1908 /* 40 */
1909 { "inc{S|}", { RMeAX }, 0 },
1910 { "inc{S|}", { RMeCX }, 0 },
1911 { "inc{S|}", { RMeDX }, 0 },
1912 { "inc{S|}", { RMeBX }, 0 },
1913 { "inc{S|}", { RMeSP }, 0 },
1914 { "inc{S|}", { RMeBP }, 0 },
1915 { "inc{S|}", { RMeSI }, 0 },
1916 { "inc{S|}", { RMeDI }, 0 },
1917 /* 48 */
1918 { "dec{S|}", { RMeAX }, 0 },
1919 { "dec{S|}", { RMeCX }, 0 },
1920 { "dec{S|}", { RMeDX }, 0 },
1921 { "dec{S|}", { RMeBX }, 0 },
1922 { "dec{S|}", { RMeSP }, 0 },
1923 { "dec{S|}", { RMeBP }, 0 },
1924 { "dec{S|}", { RMeSI }, 0 },
1925 { "dec{S|}", { RMeDI }, 0 },
1926 /* 50 */
1927 { "push!P", { RMrAX }, 0 },
1928 { "push!P", { RMrCX }, 0 },
1929 { "push!P", { RMrDX }, 0 },
1930 { "push!P", { RMrBX }, 0 },
1931 { "push!P", { RMrSP }, 0 },
1932 { "push!P", { RMrBP }, 0 },
1933 { "push!P", { RMrSI }, 0 },
1934 { "push!P", { RMrDI }, 0 },
1935 /* 58 */
1936 { "pop!P", { RMrAX }, 0 },
1937 { "pop!P", { RMrCX }, 0 },
1938 { "pop!P", { RMrDX }, 0 },
1939 { "pop!P", { RMrBX }, 0 },
1940 { "pop!P", { RMrSP }, 0 },
1941 { "pop!P", { RMrBP }, 0 },
1942 { "pop!P", { RMrSI }, 0 },
1943 { "pop!P", { RMrDI }, 0 },
1944 /* 60 */
1945 { X86_64_TABLE (X86_64_60) },
1946 { X86_64_TABLE (X86_64_61) },
1947 { X86_64_TABLE (X86_64_62) },
1948 { X86_64_TABLE (X86_64_63) },
1949 { Bad_Opcode }, /* seg fs */
1950 { Bad_Opcode }, /* seg gs */
1951 { Bad_Opcode }, /* op size prefix */
1952 { Bad_Opcode }, /* adr size prefix */
1953 /* 68 */
1954 { "pushP", { sIv }, 0 },
1955 { "imulS", { Gv, Ev, Iv }, 0 },
1956 { "pushP", { sIbT }, 0 },
1957 { "imulS", { Gv, Ev, sIb }, 0 },
1958 { "ins{b|}", { Ybr, indirDX }, 0 },
1959 { X86_64_TABLE (X86_64_6D) },
1960 { "outs{b|}", { indirDXr, Xb }, 0 },
1961 { X86_64_TABLE (X86_64_6F) },
1962 /* 70 */
1963 { "joH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1964 { "jnoH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1965 { "jbH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1966 { "jaeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1967 { "jeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1968 { "jneH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1969 { "jbeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1970 { "jaH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1971 /* 78 */
1972 { "jsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1973 { "jnsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1974 { "jpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1975 { "jnpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1976 { "jlH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1977 { "jgeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1978 { "jleH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1979 { "jgH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1980 /* 80 */
1981 { REG_TABLE (REG_80) },
1982 { REG_TABLE (REG_81) },
1983 { X86_64_TABLE (X86_64_82) },
1984 { REG_TABLE (REG_83) },
1985 { "testB", { Eb, Gb }, 0 },
1986 { "testS", { Ev, Gv }, 0 },
1987 { "xchgB", { Ebh2, Gb }, 0 },
1988 { "xchgS", { Evh2, Gv }, 0 },
1989 /* 88 */
1990 { "movB", { Ebh3, Gb }, 0 },
1991 { "movS", { Evh3, Gv }, 0 },
1992 { "movB", { Gb, EbS }, 0 },
1993 { "movS", { Gv, EvS }, 0 },
1994 { "movD", { Sv, Sw }, 0 },
1995 { "leaS", { Gv, M }, 0 },
1996 { "movD", { Sw, Sv }, 0 },
1997 { REG_TABLE (REG_8F) },
1998 /* 90 */
1999 { PREFIX_TABLE (PREFIX_90) },
2000 { "xchgS", { RMeCX, eAX }, 0 },
2001 { "xchgS", { RMeDX, eAX }, 0 },
2002 { "xchgS", { RMeBX, eAX }, 0 },
2003 { "xchgS", { RMeSP, eAX }, 0 },
2004 { "xchgS", { RMeBP, eAX }, 0 },
2005 { "xchgS", { RMeSI, eAX }, 0 },
2006 { "xchgS", { RMeDI, eAX }, 0 },
2007 /* 98 */
2008 { "cW{t|}R", { XX }, 0 },
2009 { "cR{t|}O", { XX }, 0 },
2010 { X86_64_TABLE (X86_64_9A) },
2011 { Bad_Opcode }, /* fwait */
2012 { "pushfP", { XX }, 0 },
2013 { "popfP", { XX }, 0 },
2014 { "sahf", { XX }, 0 },
2015 { "lahf", { XX }, 0 },
2016 /* a0 */
2017 { "mov%LB", { AL, Ob }, PREFIX_REX2_ILLEGAL },
2018 { "mov%LS", { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2019 { "mov%LB", { Ob, AL }, PREFIX_REX2_ILLEGAL },
2020 { "mov%LS", { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2021 { "movs{b|}", { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2022 { "movs{R|}", { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2023 { "cmps{b|}", { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2024 { "cmps{R|}", { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2025 /* a8 */
2026 { "testB", { AL, Ib }, PREFIX_REX2_ILLEGAL },
2027 { "testS", { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2028 { "stosB", { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2029 { "stosS", { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2030 { "lodsB", { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2031 { "lodsS", { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2032 { "scasB", { AL, Yb }, PREFIX_REX2_ILLEGAL },
2033 { "scasS", { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2034 /* b0 */
2035 { "movB", { RMAL, Ib }, 0 },
2036 { "movB", { RMCL, Ib }, 0 },
2037 { "movB", { RMDL, Ib }, 0 },
2038 { "movB", { RMBL, Ib }, 0 },
2039 { "movB", { RMAH, Ib }, 0 },
2040 { "movB", { RMCH, Ib }, 0 },
2041 { "movB", { RMDH, Ib }, 0 },
2042 { "movB", { RMBH, Ib }, 0 },
2043 /* b8 */
2044 { "mov%LV", { RMeAX, Iv64 }, 0 },
2045 { "mov%LV", { RMeCX, Iv64 }, 0 },
2046 { "mov%LV", { RMeDX, Iv64 }, 0 },
2047 { "mov%LV", { RMeBX, Iv64 }, 0 },
2048 { "mov%LV", { RMeSP, Iv64 }, 0 },
2049 { "mov%LV", { RMeBP, Iv64 }, 0 },
2050 { "mov%LV", { RMeSI, Iv64 }, 0 },
2051 { "mov%LV", { RMeDI, Iv64 }, 0 },
2052 /* c0 */
2053 { REG_TABLE (REG_C0) },
2054 { REG_TABLE (REG_C1) },
2055 { X86_64_TABLE (X86_64_C2) },
2056 { X86_64_TABLE (X86_64_C3) },
2057 { X86_64_TABLE (X86_64_C4) },
2058 { X86_64_TABLE (X86_64_C5) },
2059 { REG_TABLE (REG_C6) },
2060 { REG_TABLE (REG_C7) },
2061 /* c8 */
2062 { "enterP", { Iw, Ib }, 0 },
2063 { "leaveP", { XX }, 0 },
2064 { "{l|}ret{|f}%LP", { Iw }, 0 },
2065 { "{l|}ret{|f}%LP", { XX }, 0 },
2066 { "int3", { XX }, 0 },
2067 { "int", { Ib }, 0 },
2068 { X86_64_TABLE (X86_64_CE) },
2069 { "iret%LP", { XX }, 0 },
2070 /* d0 */
2071 { REG_TABLE (REG_D0) },
2072 { REG_TABLE (REG_D1) },
2073 { REG_TABLE (REG_D2) },
2074 { REG_TABLE (REG_D3) },
2075 { X86_64_TABLE (X86_64_D4) },
2076 { X86_64_TABLE (X86_64_D5) },
2077 { Bad_Opcode },
2078 { "xlat", { DSBX }, 0 },
2079 /* d8 */
2080 { FLOAT },
2081 { FLOAT },
2082 { FLOAT },
2083 { FLOAT },
2084 { FLOAT },
2085 { FLOAT },
2086 { FLOAT },
2087 { FLOAT },
2088 /* e0 */
2089 { "loopneFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2090 { "loopeFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2091 { "loopFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2092 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2093 { "inB", { AL, Ib }, PREFIX_REX2_ILLEGAL },
2094 { "inG", { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2095 { "outB", { Ib, AL }, PREFIX_REX2_ILLEGAL },
2096 { "outG", { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2097 /* e8 */
2098 { X86_64_TABLE (X86_64_E8) },
2099 { X86_64_TABLE (X86_64_E9) },
2100 { X86_64_TABLE (X86_64_EA) },
2101 { "jmp", { Jb, BND }, PREFIX_REX2_ILLEGAL },
2102 { "inB", { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2103 { "inG", { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2104 { "outB", { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2105 { "outG", { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2106 /* f0 */
2107 { Bad_Opcode }, /* lock prefix */
2108 { "int1", { XX }, 0 },
2109 { Bad_Opcode }, /* repne */
2110 { Bad_Opcode }, /* repz */
2111 { "hlt", { XX }, 0 },
2112 { "cmc", { XX }, 0 },
2113 { REG_TABLE (REG_F6) },
2114 { REG_TABLE (REG_F7) },
2115 /* f8 */
2116 { "clc", { XX }, 0 },
2117 { "stc", { XX }, 0 },
2118 { "cli", { XX }, 0 },
2119 { "sti", { XX }, 0 },
2120 { "cld", { XX }, 0 },
2121 { "std", { XX }, 0 },
2122 { REG_TABLE (REG_FE) },
2123 { REG_TABLE (REG_FF) },
2124 };
2125
2126 static const struct dis386 dis386_twobyte[] = {
2127 /* 00 */
2128 { REG_TABLE (REG_0F00 ) },
2129 { REG_TABLE (REG_0F01 ) },
2130 { "larS", { Gv, Sv }, 0 },
2131 { "lslS", { Gv, Sv }, 0 },
2132 { Bad_Opcode },
2133 { "syscall", { XX }, 0 },
2134 { "clts", { XX }, 0 },
2135 { "sysret%LQ", { XX }, 0 },
2136 /* 08 */
2137 { "invd", { XX }, 0 },
2138 { PREFIX_TABLE (PREFIX_0F09) },
2139 { Bad_Opcode },
2140 { "ud2", { XX }, 0 },
2141 { Bad_Opcode },
2142 { REG_TABLE (REG_0F0D) },
2143 { "femms", { XX }, 0 },
2144 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2145 /* 10 */
2146 { PREFIX_TABLE (PREFIX_0F10) },
2147 { PREFIX_TABLE (PREFIX_0F11) },
2148 { PREFIX_TABLE (PREFIX_0F12) },
2149 { "movlpX", { Mq, XM }, PREFIX_OPCODE },
2150 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2151 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2152 { PREFIX_TABLE (PREFIX_0F16) },
2153 { "movhpX", { Mq, XM }, PREFIX_OPCODE },
2154 /* 18 */
2155 { REG_TABLE (REG_0F18) },
2156 { "nopQ", { Ev }, 0 },
2157 { PREFIX_TABLE (PREFIX_0F1A) },
2158 { PREFIX_TABLE (PREFIX_0F1B) },
2159 { PREFIX_TABLE (PREFIX_0F1C) },
2160 { "nopQ", { Ev }, 0 },
2161 { PREFIX_TABLE (PREFIX_0F1E) },
2162 { "nopQ", { Ev }, 0 },
2163 /* 20 */
2164 { "movZ", { Em, Cm }, 0 },
2165 { "movZ", { Em, Dm }, 0 },
2166 { "movZ", { Cm, Em }, 0 },
2167 { "movZ", { Dm, Em }, 0 },
2168 { X86_64_TABLE (X86_64_0F24) },
2169 { Bad_Opcode },
2170 { X86_64_TABLE (X86_64_0F26) },
2171 { Bad_Opcode },
2172 /* 28 */
2173 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2174 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2175 { PREFIX_TABLE (PREFIX_0F2A) },
2176 { PREFIX_TABLE (PREFIX_0F2B) },
2177 { PREFIX_TABLE (PREFIX_0F2C) },
2178 { PREFIX_TABLE (PREFIX_0F2D) },
2179 { PREFIX_TABLE (PREFIX_0F2E) },
2180 { PREFIX_TABLE (PREFIX_0F2F) },
2181 /* 30 */
2182 { "wrmsr", { XX }, PREFIX_REX2_ILLEGAL },
2183 { "rdtsc", { XX }, PREFIX_REX2_ILLEGAL },
2184 { "rdmsr", { XX }, PREFIX_REX2_ILLEGAL },
2185 { "rdpmc", { XX }, PREFIX_REX2_ILLEGAL },
2186 { "sysenter", { SEP }, PREFIX_REX2_ILLEGAL },
2187 { "sysexit%LQ", { SEP }, PREFIX_REX2_ILLEGAL },
2188 { Bad_Opcode },
2189 { "getsec", { XX }, 0 },
2190 /* 38 */
2191 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2192 { Bad_Opcode },
2193 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2194 { Bad_Opcode },
2195 { Bad_Opcode },
2196 { Bad_Opcode },
2197 { Bad_Opcode },
2198 { Bad_Opcode },
2199 /* 40 */
2200 { "cmovoS", { Gv, Ev }, 0 },
2201 { "cmovnoS", { Gv, Ev }, 0 },
2202 { "cmovbS", { Gv, Ev }, 0 },
2203 { "cmovaeS", { Gv, Ev }, 0 },
2204 { "cmoveS", { Gv, Ev }, 0 },
2205 { "cmovneS", { Gv, Ev }, 0 },
2206 { "cmovbeS", { Gv, Ev }, 0 },
2207 { "cmovaS", { Gv, Ev }, 0 },
2208 /* 48 */
2209 { "cmovsS", { Gv, Ev }, 0 },
2210 { "cmovnsS", { Gv, Ev }, 0 },
2211 { "cmovpS", { Gv, Ev }, 0 },
2212 { "cmovnpS", { Gv, Ev }, 0 },
2213 { "cmovlS", { Gv, Ev }, 0 },
2214 { "cmovgeS", { Gv, Ev }, 0 },
2215 { "cmovleS", { Gv, Ev }, 0 },
2216 { "cmovgS", { Gv, Ev }, 0 },
2217 /* 50 */
2218 { "movmskpX", { Gdq, Ux }, PREFIX_OPCODE },
2219 { PREFIX_TABLE (PREFIX_0F51) },
2220 { PREFIX_TABLE (PREFIX_0F52) },
2221 { PREFIX_TABLE (PREFIX_0F53) },
2222 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2223 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2224 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2225 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2226 /* 58 */
2227 { PREFIX_TABLE (PREFIX_0F58) },
2228 { PREFIX_TABLE (PREFIX_0F59) },
2229 { PREFIX_TABLE (PREFIX_0F5A) },
2230 { PREFIX_TABLE (PREFIX_0F5B) },
2231 { PREFIX_TABLE (PREFIX_0F5C) },
2232 { PREFIX_TABLE (PREFIX_0F5D) },
2233 { PREFIX_TABLE (PREFIX_0F5E) },
2234 { PREFIX_TABLE (PREFIX_0F5F) },
2235 /* 60 */
2236 { PREFIX_TABLE (PREFIX_0F60) },
2237 { PREFIX_TABLE (PREFIX_0F61) },
2238 { PREFIX_TABLE (PREFIX_0F62) },
2239 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2240 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2241 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2242 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2243 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2244 /* 68 */
2245 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2246 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2247 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2248 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2249 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2250 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2251 { "movK", { MX, Edq }, PREFIX_OPCODE },
2252 { PREFIX_TABLE (PREFIX_0F6F) },
2253 /* 70 */
2254 { PREFIX_TABLE (PREFIX_0F70) },
2255 { REG_TABLE (REG_0F71) },
2256 { REG_TABLE (REG_0F72) },
2257 { REG_TABLE (REG_0F73) },
2258 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2259 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2260 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2261 { "emms", { XX }, PREFIX_OPCODE },
2262 /* 78 */
2263 { PREFIX_TABLE (PREFIX_0F78) },
2264 { PREFIX_TABLE (PREFIX_0F79) },
2265 { Bad_Opcode },
2266 { Bad_Opcode },
2267 { PREFIX_TABLE (PREFIX_0F7C) },
2268 { PREFIX_TABLE (PREFIX_0F7D) },
2269 { PREFIX_TABLE (PREFIX_0F7E) },
2270 { PREFIX_TABLE (PREFIX_0F7F) },
2271 /* 80 */
2272 { "joH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2273 { "jnoH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2274 { "jbH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2275 { "jaeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2276 { "jeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2277 { "jneH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2278 { "jbeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2279 { "jaH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2280 /* 88 */
2281 { "jsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2282 { "jnsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2283 { "jpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2284 { "jnpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2285 { "jlH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2286 { "jgeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2287 { "jleH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2288 { "jgH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2289 /* 90 */
2290 { "seto", { Eb }, 0 },
2291 { "setno", { Eb }, 0 },
2292 { "setb", { Eb }, 0 },
2293 { "setae", { Eb }, 0 },
2294 { "sete", { Eb }, 0 },
2295 { "setne", { Eb }, 0 },
2296 { "setbe", { Eb }, 0 },
2297 { "seta", { Eb }, 0 },
2298 /* 98 */
2299 { "sets", { Eb }, 0 },
2300 { "setns", { Eb }, 0 },
2301 { "setp", { Eb }, 0 },
2302 { "setnp", { Eb }, 0 },
2303 { "setl", { Eb }, 0 },
2304 { "setge", { Eb }, 0 },
2305 { "setle", { Eb }, 0 },
2306 { "setg", { Eb }, 0 },
2307 /* a0 */
2308 { "pushP", { fs }, 0 },
2309 { "popP", { fs }, 0 },
2310 { "cpuid", { XX }, 0 },
2311 { "btS", { Ev, Gv }, 0 },
2312 { "shldS", { Ev, Gv, Ib }, 0 },
2313 { "shldS", { Ev, Gv, CL }, 0 },
2314 { REG_TABLE (REG_0FA6) },
2315 { REG_TABLE (REG_0FA7) },
2316 /* a8 */
2317 { "pushP", { gs }, 0 },
2318 { "popP", { gs }, 0 },
2319 { "rsm", { XX }, 0 },
2320 { "btsS", { Evh1, Gv }, 0 },
2321 { "shrdS", { Ev, Gv, Ib }, 0 },
2322 { "shrdS", { Ev, Gv, CL }, 0 },
2323 { REG_TABLE (REG_0FAE) },
2324 { "imulS", { Gv, Ev }, 0 },
2325 /* b0 */
2326 { "cmpxchgB", { Ebh1, Gb }, 0 },
2327 { "cmpxchgS", { Evh1, Gv }, 0 },
2328 { "lssS", { Gv, Mp }, 0 },
2329 { "btrS", { Evh1, Gv }, 0 },
2330 { "lfsS", { Gv, Mp }, 0 },
2331 { "lgsS", { Gv, Mp }, 0 },
2332 { "movz{bR|x}", { Gv, Eb }, 0 },
2333 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2334 /* b8 */
2335 { PREFIX_TABLE (PREFIX_0FB8) },
2336 { "ud1S", { Gv, Ev }, 0 },
2337 { REG_TABLE (REG_0FBA) },
2338 { "btcS", { Evh1, Gv }, 0 },
2339 { PREFIX_TABLE (PREFIX_0FBC) },
2340 { PREFIX_TABLE (PREFIX_0FBD) },
2341 { "movs{bR|x}", { Gv, Eb }, 0 },
2342 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2343 /* c0 */
2344 { "xaddB", { Ebh1, Gb }, 0 },
2345 { "xaddS", { Evh1, Gv }, 0 },
2346 { PREFIX_TABLE (PREFIX_0FC2) },
2347 { "movntiS", { Mdq, Gdq }, PREFIX_OPCODE },
2348 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
2349 { "pextrw", { Gd, Nq, Ib }, PREFIX_OPCODE },
2350 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2351 { REG_TABLE (REG_0FC7) },
2352 /* c8 */
2353 { "bswap", { RMeAX }, 0 },
2354 { "bswap", { RMeCX }, 0 },
2355 { "bswap", { RMeDX }, 0 },
2356 { "bswap", { RMeBX }, 0 },
2357 { "bswap", { RMeSP }, 0 },
2358 { "bswap", { RMeBP }, 0 },
2359 { "bswap", { RMeSI }, 0 },
2360 { "bswap", { RMeDI }, 0 },
2361 /* d0 */
2362 { PREFIX_TABLE (PREFIX_0FD0) },
2363 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2364 { "psrld", { MX, EM }, PREFIX_OPCODE },
2365 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2366 { "paddq", { MX, EM }, PREFIX_OPCODE },
2367 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2368 { PREFIX_TABLE (PREFIX_0FD6) },
2369 { "pmovmskb", { Gdq, Nq }, PREFIX_OPCODE },
2370 /* d8 */
2371 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2372 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2373 { "pminub", { MX, EM }, PREFIX_OPCODE },
2374 { "pand", { MX, EM }, PREFIX_OPCODE },
2375 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2376 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2377 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2378 { "pandn", { MX, EM }, PREFIX_OPCODE },
2379 /* e0 */
2380 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2381 { "psraw", { MX, EM }, PREFIX_OPCODE },
2382 { "psrad", { MX, EM }, PREFIX_OPCODE },
2383 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2384 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2385 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2386 { PREFIX_TABLE (PREFIX_0FE6) },
2387 { PREFIX_TABLE (PREFIX_0FE7) },
2388 /* e8 */
2389 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2390 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2391 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2392 { "por", { MX, EM }, PREFIX_OPCODE },
2393 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2394 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2395 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2396 { "pxor", { MX, EM }, PREFIX_OPCODE },
2397 /* f0 */
2398 { PREFIX_TABLE (PREFIX_0FF0) },
2399 { "psllw", { MX, EM }, PREFIX_OPCODE },
2400 { "pslld", { MX, EM }, PREFIX_OPCODE },
2401 { "psllq", { MX, EM }, PREFIX_OPCODE },
2402 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2403 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2404 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2405 { PREFIX_TABLE (PREFIX_0FF7) },
2406 /* f8 */
2407 { "psubb", { MX, EM }, PREFIX_OPCODE },
2408 { "psubw", { MX, EM }, PREFIX_OPCODE },
2409 { "psubd", { MX, EM }, PREFIX_OPCODE },
2410 { "psubq", { MX, EM }, PREFIX_OPCODE },
2411 { "paddb", { MX, EM }, PREFIX_OPCODE },
2412 { "paddw", { MX, EM }, PREFIX_OPCODE },
2413 { "paddd", { MX, EM }, PREFIX_OPCODE },
2414 { "ud0S", { Gv, Ev }, 0 },
2415 };
2416
2417 static const bool onebyte_has_modrm[256] = {
2418 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2419 /* ------------------------------- */
2420 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2421 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2422 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2423 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2424 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2425 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2426 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2427 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2428 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2429 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2430 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2431 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2432 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2433 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2434 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2435 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2436 /* ------------------------------- */
2437 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2438 };
2439
2440 static const bool twobyte_has_modrm[256] = {
2441 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2442 /* ------------------------------- */
2443 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2444 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2445 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2446 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2447 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2448 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2449 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2450 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2451 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2452 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2453 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2454 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2455 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2456 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2457 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2458 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2459 /* ------------------------------- */
2460 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2461 };
2462
2463
2464 struct op
2465 {
2466 const char *name;
2467 unsigned int len;
2468 };
2469
2470 /* If we are accessing mod/rm/reg without need_modrm set, then the
2471 values are stale. Hitting this abort likely indicates that you
2472 need to update onebyte_has_modrm or twobyte_has_modrm. */
2473 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2474
2475 static const char intel_index16[][6] = {
2476 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2477 };
2478
2479 static const char att_names64[][8] = {
2480 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2481 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2482 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2483 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2484 };
2485 static const char att_names32[][8] = {
2486 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2487 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2488 "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2489 "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2490 };
2491 static const char att_names16[][8] = {
2492 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2493 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2494 "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2495 "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2496 };
2497 static const char att_names8[][8] = {
2498 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2499 };
2500 static const char att_names8rex[][8] = {
2501 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2502 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2503 "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2504 "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2505 };
2506 static const char att_names_seg[][4] = {
2507 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2508 };
2509 static const char att_index64[] = "%riz";
2510 static const char att_index32[] = "%eiz";
2511 static const char att_index16[][8] = {
2512 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2513 };
2514
2515 static const char att_names_mm[][8] = {
2516 "%mm0", "%mm1", "%mm2", "%mm3",
2517 "%mm4", "%mm5", "%mm6", "%mm7"
2518 };
2519
2520 static const char att_names_bnd[][8] = {
2521 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2522 };
2523
2524 static const char att_names_xmm[][8] = {
2525 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2526 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2527 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2528 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2529 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2530 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2531 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2532 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2533 };
2534
2535 static const char att_names_ymm[][8] = {
2536 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2537 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2538 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2539 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2540 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2541 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2542 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2543 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2544 };
2545
2546 static const char att_names_zmm[][8] = {
2547 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2548 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2549 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2550 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2551 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2552 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2553 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2554 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2555 };
2556
2557 static const char att_names_tmm[][8] = {
2558 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2559 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2560 };
2561
2562 static const char att_names_mask[][8] = {
2563 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2564 };
2565
2566 static const char *const names_rounding[] =
2567 {
2568 "{rn-",
2569 "{rd-",
2570 "{ru-",
2571 "{rz-"
2572 };
2573
2574 static const struct dis386 reg_table[][8] = {
2575 /* REG_80 */
2576 {
2577 { "addA", { Ebh1, Ib }, 0 },
2578 { "orA", { Ebh1, Ib }, 0 },
2579 { "adcA", { Ebh1, Ib }, 0 },
2580 { "sbbA", { Ebh1, Ib }, 0 },
2581 { "andA", { Ebh1, Ib }, 0 },
2582 { "subA", { Ebh1, Ib }, 0 },
2583 { "xorA", { Ebh1, Ib }, 0 },
2584 { "cmpA", { Eb, Ib }, 0 },
2585 },
2586 /* REG_81 */
2587 {
2588 { "addQ", { Evh1, Iv }, 0 },
2589 { "orQ", { Evh1, Iv }, 0 },
2590 { "adcQ", { Evh1, Iv }, 0 },
2591 { "sbbQ", { Evh1, Iv }, 0 },
2592 { "andQ", { Evh1, Iv }, 0 },
2593 { "subQ", { Evh1, Iv }, 0 },
2594 { "xorQ", { Evh1, Iv }, 0 },
2595 { "cmpQ", { Ev, Iv }, 0 },
2596 },
2597 /* REG_83 */
2598 {
2599 { "addQ", { Evh1, sIb }, 0 },
2600 { "orQ", { Evh1, sIb }, 0 },
2601 { "adcQ", { Evh1, sIb }, 0 },
2602 { "sbbQ", { Evh1, sIb }, 0 },
2603 { "andQ", { Evh1, sIb }, 0 },
2604 { "subQ", { Evh1, sIb }, 0 },
2605 { "xorQ", { Evh1, sIb }, 0 },
2606 { "cmpQ", { Ev, sIb }, 0 },
2607 },
2608 /* REG_8F */
2609 {
2610 { "pop{P|}", { stackEv }, 0 },
2611 { XOP_8F_TABLE () },
2612 { Bad_Opcode },
2613 { Bad_Opcode },
2614 { Bad_Opcode },
2615 { XOP_8F_TABLE () },
2616 },
2617 /* REG_C0 */
2618 {
2619 { "%NFrolA", { VexGb, Eb, Ib }, NO_PREFIX },
2620 { "%NFrorA", { VexGb, Eb, Ib }, NO_PREFIX },
2621 { "rclA", { VexGb, Eb, Ib }, NO_PREFIX },
2622 { "rcrA", { VexGb, Eb, Ib }, NO_PREFIX },
2623 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX },
2624 { "%NFshrA", { VexGb, Eb, Ib }, NO_PREFIX },
2625 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX },
2626 { "%NFsarA", { VexGb, Eb, Ib }, NO_PREFIX },
2627 },
2628 /* REG_C1 */
2629 {
2630 { "%NFrolQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2631 { "%NFrorQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2632 { "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2633 { "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2634 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2635 { "%NFshrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2636 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2637 { "%NFsarQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2638 },
2639 /* REG_C6 */
2640 {
2641 { "movA", { Ebh3, Ib }, 0 },
2642 { Bad_Opcode },
2643 { Bad_Opcode },
2644 { Bad_Opcode },
2645 { Bad_Opcode },
2646 { Bad_Opcode },
2647 { Bad_Opcode },
2648 { RM_TABLE (RM_C6_REG_7) },
2649 },
2650 /* REG_C7 */
2651 {
2652 { "movQ", { Evh3, Iv }, 0 },
2653 { Bad_Opcode },
2654 { Bad_Opcode },
2655 { Bad_Opcode },
2656 { Bad_Opcode },
2657 { Bad_Opcode },
2658 { Bad_Opcode },
2659 { RM_TABLE (RM_C7_REG_7) },
2660 },
2661 /* REG_D0 */
2662 {
2663 { "%NFrolA", { VexGb, Eb, I1 }, NO_PREFIX },
2664 { "%NFrorA", { VexGb, Eb, I1 }, NO_PREFIX },
2665 { "rclA", { VexGb, Eb, I1 }, NO_PREFIX },
2666 { "rcrA", { VexGb, Eb, I1 }, NO_PREFIX },
2667 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX },
2668 { "%NFshrA", { VexGb, Eb, I1 }, NO_PREFIX },
2669 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX },
2670 { "%NFsarA", { VexGb, Eb, I1 }, NO_PREFIX },
2671 },
2672 /* REG_D1 */
2673 {
2674 { "%NFrolQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2675 { "%NFrorQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2676 { "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2677 { "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2678 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2679 { "%NFshrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2680 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2681 { "%NFsarQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2682 },
2683 /* REG_D2 */
2684 {
2685 { "%NFrolA", { VexGb, Eb, CL }, NO_PREFIX },
2686 { "%NFrorA", { VexGb, Eb, CL }, NO_PREFIX },
2687 { "rclA", { VexGb, Eb, CL }, NO_PREFIX },
2688 { "rcrA", { VexGb, Eb, CL }, NO_PREFIX },
2689 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX },
2690 { "%NFshrA", { VexGb, Eb, CL }, NO_PREFIX },
2691 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX },
2692 { "%NFsarA", { VexGb, Eb, CL }, NO_PREFIX },
2693 },
2694 /* REG_D3 */
2695 {
2696 { "%NFrolQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2697 { "%NFrorQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2698 { "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2699 { "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2700 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2701 { "%NFshrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2702 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2703 { "%NFsarQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2704 },
2705 /* REG_F6 */
2706 {
2707 { "testA", { Eb, Ib }, 0 },
2708 { "testA", { Eb, Ib }, 0 },
2709 { "notA", { Ebh1 }, 0 },
2710 { "negA", { Ebh1 }, 0 },
2711 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2712 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2713 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2714 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2715 },
2716 /* REG_F7 */
2717 {
2718 { "testQ", { Ev, Iv }, 0 },
2719 { "testQ", { Ev, Iv }, 0 },
2720 { "notQ", { Evh1 }, 0 },
2721 { "negQ", { Evh1 }, 0 },
2722 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2723 { "imulQ", { Ev }, 0 },
2724 { "divQ", { Ev }, 0 },
2725 { "idivQ", { Ev }, 0 },
2726 },
2727 /* REG_FE */
2728 {
2729 { "incA", { Ebh1 }, 0 },
2730 { "decA", { Ebh1 }, 0 },
2731 },
2732 /* REG_FF */
2733 {
2734 { "incQ", { Evh1 }, 0 },
2735 { "decQ", { Evh1 }, 0 },
2736 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2737 { "{l|}call^", { indirEp }, 0 },
2738 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2739 { "{l|}jmp^", { indirEp }, 0 },
2740 { "push{P|}", { stackEv }, 0 },
2741 { Bad_Opcode },
2742 },
2743 /* REG_0F00 */
2744 {
2745 { "sldtD", { Sv }, 0 },
2746 { "strD", { Sv }, 0 },
2747 { "lldtD", { Sv }, 0 },
2748 { "ltrD", { Sv }, 0 },
2749 { "verrD", { Sv }, 0 },
2750 { "verwD", { Sv }, 0 },
2751 { X86_64_TABLE (X86_64_0F00_REG_6) },
2752 { Bad_Opcode },
2753 },
2754 /* REG_0F01 */
2755 {
2756 { MOD_TABLE (MOD_0F01_REG_0) },
2757 { MOD_TABLE (MOD_0F01_REG_1) },
2758 { MOD_TABLE (MOD_0F01_REG_2) },
2759 { MOD_TABLE (MOD_0F01_REG_3) },
2760 { "smswD", { Sv }, 0 },
2761 { MOD_TABLE (MOD_0F01_REG_5) },
2762 { "lmsw", { Ew }, 0 },
2763 { MOD_TABLE (MOD_0F01_REG_7) },
2764 },
2765 /* REG_0F0D */
2766 {
2767 { "prefetch", { Mb }, 0 },
2768 { "prefetchw", { Mb }, 0 },
2769 { "prefetchwt1", { Mb }, 0 },
2770 { "prefetch", { Mb }, 0 },
2771 { "prefetch", { Mb }, 0 },
2772 { "prefetch", { Mb }, 0 },
2773 { "prefetch", { Mb }, 0 },
2774 { "prefetch", { Mb }, 0 },
2775 },
2776 /* REG_0F18 */
2777 {
2778 { MOD_TABLE (MOD_0F18_REG_0) },
2779 { MOD_TABLE (MOD_0F18_REG_1) },
2780 { MOD_TABLE (MOD_0F18_REG_2) },
2781 { MOD_TABLE (MOD_0F18_REG_3) },
2782 { "nopQ", { Ev }, 0 },
2783 { "nopQ", { Ev }, 0 },
2784 { MOD_TABLE (MOD_0F18_REG_6) },
2785 { MOD_TABLE (MOD_0F18_REG_7) },
2786 },
2787 /* REG_0F1C_P_0_MOD_0 */
2788 {
2789 { "cldemote", { Mb }, 0 },
2790 { "nopQ", { Ev }, 0 },
2791 { "nopQ", { Ev }, 0 },
2792 { "nopQ", { Ev }, 0 },
2793 { "nopQ", { Ev }, 0 },
2794 { "nopQ", { Ev }, 0 },
2795 { "nopQ", { Ev }, 0 },
2796 { "nopQ", { Ev }, 0 },
2797 },
2798 /* REG_0F1E_P_1_MOD_3 */
2799 {
2800 { "nopQ", { Ev }, PREFIX_IGNORED },
2801 { "rdsspK", { Edq }, 0 },
2802 { "nopQ", { Ev }, PREFIX_IGNORED },
2803 { "nopQ", { Ev }, PREFIX_IGNORED },
2804 { "nopQ", { Ev }, PREFIX_IGNORED },
2805 { "nopQ", { Ev }, PREFIX_IGNORED },
2806 { "nopQ", { Ev }, PREFIX_IGNORED },
2807 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2808 },
2809 /* REG_0F38D8_PREFIX_1 */
2810 {
2811 { "aesencwide128kl", { M }, 0 },
2812 { "aesdecwide128kl", { M }, 0 },
2813 { "aesencwide256kl", { M }, 0 },
2814 { "aesdecwide256kl", { M }, 0 },
2815 },
2816 /* REG_0F3A0F_P_1 */
2817 {
2818 { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2819 },
2820 /* REG_0F71 */
2821 {
2822 { Bad_Opcode },
2823 { Bad_Opcode },
2824 { "psrlw", { Nq, Ib }, PREFIX_OPCODE },
2825 { Bad_Opcode },
2826 { "psraw", { Nq, Ib }, PREFIX_OPCODE },
2827 { Bad_Opcode },
2828 { "psllw", { Nq, Ib }, PREFIX_OPCODE },
2829 },
2830 /* REG_0F72 */
2831 {
2832 { Bad_Opcode },
2833 { Bad_Opcode },
2834 { "psrld", { Nq, Ib }, PREFIX_OPCODE },
2835 { Bad_Opcode },
2836 { "psrad", { Nq, Ib }, PREFIX_OPCODE },
2837 { Bad_Opcode },
2838 { "pslld", { Nq, Ib }, PREFIX_OPCODE },
2839 },
2840 /* REG_0F73 */
2841 {
2842 { Bad_Opcode },
2843 { Bad_Opcode },
2844 { "psrlq", { Nq, Ib }, PREFIX_OPCODE },
2845 { "psrldq", { Ux, Ib }, PREFIX_DATA },
2846 { Bad_Opcode },
2847 { Bad_Opcode },
2848 { "psllq", { Nq, Ib }, PREFIX_OPCODE },
2849 { "pslldq", { Ux, Ib }, PREFIX_DATA },
2850 },
2851 /* REG_0FA6 */
2852 {
2853 { "montmul", { { OP_0f07, 0 } }, 0 },
2854 { "xsha1", { { OP_0f07, 0 } }, 0 },
2855 { "xsha256", { { OP_0f07, 0 } }, 0 },
2856 },
2857 /* REG_0FA7 */
2858 {
2859 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2860 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2861 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2862 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2863 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2864 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2865 },
2866 /* REG_0FAE */
2867 {
2868 { MOD_TABLE (MOD_0FAE_REG_0) },
2869 { MOD_TABLE (MOD_0FAE_REG_1) },
2870 { MOD_TABLE (MOD_0FAE_REG_2) },
2871 { MOD_TABLE (MOD_0FAE_REG_3) },
2872 { MOD_TABLE (MOD_0FAE_REG_4) },
2873 { MOD_TABLE (MOD_0FAE_REG_5) },
2874 { MOD_TABLE (MOD_0FAE_REG_6) },
2875 { MOD_TABLE (MOD_0FAE_REG_7) },
2876 },
2877 /* REG_0FBA */
2878 {
2879 { Bad_Opcode },
2880 { Bad_Opcode },
2881 { Bad_Opcode },
2882 { Bad_Opcode },
2883 { "btQ", { Ev, Ib }, 0 },
2884 { "btsQ", { Evh1, Ib }, 0 },
2885 { "btrQ", { Evh1, Ib }, 0 },
2886 { "btcQ", { Evh1, Ib }, 0 },
2887 },
2888 /* REG_0FC7 */
2889 {
2890 { Bad_Opcode },
2891 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2892 { Bad_Opcode },
2893 { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2894 { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2895 { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2896 { MOD_TABLE (MOD_0FC7_REG_6) },
2897 { MOD_TABLE (MOD_0FC7_REG_7) },
2898 },
2899 /* REG_VEX_0F71 */
2900 {
2901 { Bad_Opcode },
2902 { Bad_Opcode },
2903 { "vpsrlw", { Vex, Ux, Ib }, PREFIX_DATA },
2904 { Bad_Opcode },
2905 { "vpsraw", { Vex, Ux, Ib }, PREFIX_DATA },
2906 { Bad_Opcode },
2907 { "vpsllw", { Vex, Ux, Ib }, PREFIX_DATA },
2908 },
2909 /* REG_VEX_0F72 */
2910 {
2911 { Bad_Opcode },
2912 { Bad_Opcode },
2913 { "vpsrld", { Vex, Ux, Ib }, PREFIX_DATA },
2914 { Bad_Opcode },
2915 { "vpsrad", { Vex, Ux, Ib }, PREFIX_DATA },
2916 { Bad_Opcode },
2917 { "vpslld", { Vex, Ux, Ib }, PREFIX_DATA },
2918 },
2919 /* REG_VEX_0F73 */
2920 {
2921 { Bad_Opcode },
2922 { Bad_Opcode },
2923 { "vpsrlq", { Vex, Ux, Ib }, PREFIX_DATA },
2924 { "vpsrldq", { Vex, Ux, Ib }, PREFIX_DATA },
2925 { Bad_Opcode },
2926 { Bad_Opcode },
2927 { "vpsllq", { Vex, Ux, Ib }, PREFIX_DATA },
2928 { "vpslldq", { Vex, Ux, Ib }, PREFIX_DATA },
2929 },
2930 /* REG_VEX_0FAE */
2931 {
2932 { Bad_Opcode },
2933 { Bad_Opcode },
2934 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
2935 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
2936 },
2937 /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2938 {
2939 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2940 },
2941 /* REG_VEX_0F38F3_L_0_P_0 */
2942 {
2943 { Bad_Opcode },
2944 { "%NFblsrS", { VexGdq, Edq }, 0 },
2945 { "%NFblsmskS", { VexGdq, Edq }, 0 },
2946 { "%NFblsiS", { VexGdq, Edq }, 0 },
2947 },
2948 /* REG_VEX_MAP7_F8_L_0_W_0 */
2949 {
2950 { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
2951 },
2952 /* REG_XOP_09_01_L_0 */
2953 {
2954 { Bad_Opcode },
2955 { "blcfill", { VexGdq, Edq }, 0 },
2956 { "blsfill", { VexGdq, Edq }, 0 },
2957 { "blcs", { VexGdq, Edq }, 0 },
2958 { "tzmsk", { VexGdq, Edq }, 0 },
2959 { "blcic", { VexGdq, Edq }, 0 },
2960 { "blsic", { VexGdq, Edq }, 0 },
2961 { "t1mskc", { VexGdq, Edq }, 0 },
2962 },
2963 /* REG_XOP_09_02_L_0 */
2964 {
2965 { Bad_Opcode },
2966 { "blcmsk", { VexGdq, Edq }, 0 },
2967 { Bad_Opcode },
2968 { Bad_Opcode },
2969 { Bad_Opcode },
2970 { Bad_Opcode },
2971 { "blci", { VexGdq, Edq }, 0 },
2972 },
2973 /* REG_XOP_09_12_L_0 */
2974 {
2975 { "llwpcb", { Rdq }, 0 },
2976 { "slwpcb", { Rdq }, 0 },
2977 },
2978 /* REG_XOP_0A_12_L_0 */
2979 {
2980 { "lwpins", { VexGdq, Ed, Id }, 0 },
2981 { "lwpval", { VexGdq, Ed, Id }, 0 },
2982 },
2983
2984 #include "i386-dis-evex-reg.h"
2985 };
2986
2987 static const struct dis386 prefix_table[][4] = {
2988 /* PREFIX_90 */
2989 {
2990 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2991 { "pause", { XX }, 0 },
2992 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2993 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2994 },
2995
2996 /* PREFIX_0F00_REG_6_X86_64 */
2997 {
2998 { Bad_Opcode },
2999 { Bad_Opcode },
3000 { Bad_Opcode },
3001 { "lkgsD", { Sv }, 0 },
3002 },
3003
3004 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3005 {
3006 { "wrmsrns", { Skip_MODRM }, 0 },
3007 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3008 { Bad_Opcode },
3009 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3010 },
3011
3012 /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3013 {
3014 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3015 },
3016
3017 /* PREFIX_0F01_REG_1_RM_2 */
3018 {
3019 { "clac", { Skip_MODRM }, 0 },
3020 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3021 { Bad_Opcode },
3022 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3023 },
3024
3025 /* PREFIX_0F01_REG_1_RM_4 */
3026 {
3027 { Bad_Opcode },
3028 { Bad_Opcode },
3029 { "tdcall", { Skip_MODRM }, 0 },
3030 { Bad_Opcode },
3031 },
3032
3033 /* PREFIX_0F01_REG_1_RM_5 */
3034 {
3035 { Bad_Opcode },
3036 { Bad_Opcode },
3037 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3038 { Bad_Opcode },
3039 },
3040
3041 /* PREFIX_0F01_REG_1_RM_6 */
3042 {
3043 { Bad_Opcode },
3044 { Bad_Opcode },
3045 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3046 { Bad_Opcode },
3047 },
3048
3049 /* PREFIX_0F01_REG_1_RM_7 */
3050 {
3051 { "encls", { Skip_MODRM }, 0 },
3052 { Bad_Opcode },
3053 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3054 { Bad_Opcode },
3055 },
3056
3057 /* PREFIX_0F01_REG_3_RM_1 */
3058 {
3059 { "vmmcall", { Skip_MODRM }, 0 },
3060 { "vmgexit", { Skip_MODRM }, 0 },
3061 { Bad_Opcode },
3062 { "vmgexit", { Skip_MODRM }, 0 },
3063 },
3064
3065 /* PREFIX_0F01_REG_5_MOD_0 */
3066 {
3067 { Bad_Opcode },
3068 { "rstorssp", { Mq }, PREFIX_OPCODE },
3069 },
3070
3071 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3072 {
3073 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3074 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3075 { Bad_Opcode },
3076 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3077 },
3078
3079 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3080 {
3081 { Bad_Opcode },
3082 { Bad_Opcode },
3083 { Bad_Opcode },
3084 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3085 },
3086
3087 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3088 {
3089 { Bad_Opcode },
3090 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3091 },
3092
3093 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3094 {
3095 { Bad_Opcode },
3096 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3097 },
3098
3099 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3100 {
3101 { Bad_Opcode },
3102 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3103 },
3104
3105 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3106 {
3107 { "rdpkru", { Skip_MODRM }, 0 },
3108 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3109 },
3110
3111 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3112 {
3113 { "wrpkru", { Skip_MODRM }, 0 },
3114 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3115 },
3116
3117 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3118 {
3119 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3120 { "mcommit", { Skip_MODRM }, 0 },
3121 },
3122
3123 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3124 {
3125 { "rdpru", { Skip_MODRM }, 0 },
3126 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3127 },
3128
3129 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3130 {
3131 { "invlpgb", { Skip_MODRM }, 0 },
3132 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3133 { Bad_Opcode },
3134 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3135 },
3136
3137 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3138 {
3139 { "tlbsync", { Skip_MODRM }, 0 },
3140 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3141 { Bad_Opcode },
3142 { "pvalidate", { Skip_MODRM }, 0 },
3143 },
3144
3145 /* PREFIX_0F09 */
3146 {
3147 { "wbinvd", { XX }, 0 },
3148 { "wbnoinvd", { XX }, 0 },
3149 },
3150
3151 /* PREFIX_0F10 */
3152 {
3153 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3154 { "%XEVmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3155 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3156 { "%XEVmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3157 },
3158
3159 /* PREFIX_0F11 */
3160 {
3161 { "%XEVmovupX", { EXxS, XM }, 0 },
3162 { "%XEVmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3163 { "%XEVmovupX", { EXxS, XM }, 0 },
3164 { "%XEVmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3165 },
3166
3167 /* PREFIX_0F12 */
3168 {
3169 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3170 { "movsldup", { XM, EXx }, 0 },
3171 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
3172 { "movddup", { XM, EXq }, 0 },
3173 },
3174
3175 /* PREFIX_0F16 */
3176 {
3177 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3178 { "movshdup", { XM, EXx }, 0 },
3179 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
3180 },
3181
3182 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3183 {
3184 { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
3185 { "nopQ", { Ev }, 0 },
3186 { "nopQ", { Ev }, 0 },
3187 { "nopQ", { Ev }, 0 },
3188 },
3189
3190 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3191 {
3192 { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
3193 { "nopQ", { Ev }, 0 },
3194 { "nopQ", { Ev }, 0 },
3195 { "nopQ", { Ev }, 0 },
3196 },
3197
3198 /* PREFIX_0F1A */
3199 {
3200 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3201 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3202 { "bndmov", { Gbnd, Ebnd }, 0 },
3203 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3204 },
3205
3206 /* PREFIX_0F1B */
3207 {
3208 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3209 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3210 { "bndmov", { EbndS, Gbnd }, 0 },
3211 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3212 },
3213
3214 /* PREFIX_0F1C */
3215 {
3216 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3217 { "nopQ", { Ev }, PREFIX_IGNORED },
3218 { "nopQ", { Ev }, 0 },
3219 { "nopQ", { Ev }, PREFIX_IGNORED },
3220 },
3221
3222 /* PREFIX_0F1E */
3223 {
3224 { "nopQ", { Ev }, 0 },
3225 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3226 { "nopQ", { Ev }, 0 },
3227 { NULL, { XX }, PREFIX_IGNORED },
3228 },
3229
3230 /* PREFIX_0F2A */
3231 {
3232 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3233 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3234 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3235 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3236 },
3237
3238 /* PREFIX_0F2B */
3239 {
3240 { "movntps", { Mx, XM }, 0 },
3241 { "movntss", { Md, XM }, 0 },
3242 { "movntpd", { Mx, XM }, 0 },
3243 { "movntsd", { Mq, XM }, 0 },
3244 },
3245
3246 /* PREFIX_0F2C */
3247 {
3248 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3249 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3250 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3251 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3252 },
3253
3254 /* PREFIX_0F2D */
3255 {
3256 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3257 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3258 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3259 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3260 },
3261
3262 /* PREFIX_0F2E */
3263 {
3264 { "%XEVucomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3265 { Bad_Opcode },
3266 { "%XEVucomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3267 },
3268
3269 /* PREFIX_0F2F */
3270 {
3271 { "%XEVcomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3272 { Bad_Opcode },
3273 { "%XEVcomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3274 },
3275
3276 /* PREFIX_0F51 */
3277 {
3278 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3279 { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3280 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3281 { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3282 },
3283
3284 /* PREFIX_0F52 */
3285 {
3286 { "Vrsqrtps", { XM, EXx }, 0 },
3287 { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3288 },
3289
3290 /* PREFIX_0F53 */
3291 {
3292 { "Vrcpps", { XM, EXx }, 0 },
3293 { "Vrcpss", { XMScalar, VexScalar, EXd }, 0 },
3294 },
3295
3296 /* PREFIX_0F58 */
3297 {
3298 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3299 { "%XEVadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3300 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3301 { "%XEVadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3302 },
3303
3304 /* PREFIX_0F59 */
3305 {
3306 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3307 { "%XEVmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3308 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3309 { "%XEVmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3310 },
3311
3312 /* PREFIX_0F5A */
3313 {
3314 { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3315 { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3316 { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3317 { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3318 },
3319
3320 /* PREFIX_0F5B */
3321 {
3322 { "Vcvtdq2ps", { XM, EXx }, 0 },
3323 { "Vcvttps2dq", { XM, EXx }, 0 },
3324 { "Vcvtps2dq", { XM, EXx }, 0 },
3325 },
3326
3327 /* PREFIX_0F5C */
3328 {
3329 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3330 { "%XEVsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3331 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3332 { "%XEVsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3333 },
3334
3335 /* PREFIX_0F5D */
3336 {
3337 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3338 { "%XEVmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3339 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3340 { "%XEVmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3341 },
3342
3343 /* PREFIX_0F5E */
3344 {
3345 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3346 { "%XEVdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3347 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3348 { "%XEVdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3349 },
3350
3351 /* PREFIX_0F5F */
3352 {
3353 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3354 { "%XEVmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3355 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3356 { "%XEVmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3357 },
3358
3359 /* PREFIX_0F60 */
3360 {
3361 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3362 { Bad_Opcode },
3363 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3364 },
3365
3366 /* PREFIX_0F61 */
3367 {
3368 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3369 { Bad_Opcode },
3370 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3371 },
3372
3373 /* PREFIX_0F62 */
3374 {
3375 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3376 { Bad_Opcode },
3377 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3378 },
3379
3380 /* PREFIX_0F6F */
3381 {
3382 { "movq", { MX, EM }, PREFIX_OPCODE },
3383 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3384 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3385 },
3386
3387 /* PREFIX_0F70 */
3388 {
3389 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3390 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3391 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3392 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3393 },
3394
3395 /* PREFIX_0F78 */
3396 {
3397 {"vmread", { Em, Gm }, 0 },
3398 { Bad_Opcode },
3399 {"extrq", { Uxmm, Ib, Ib }, 0 },
3400 {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3401 },
3402
3403 /* PREFIX_0F79 */
3404 {
3405 {"vmwrite", { Gm, Em }, 0 },
3406 { Bad_Opcode },
3407 {"extrq", { XM, Uxmm }, 0 },
3408 {"insertq", { XM, Uxmm }, 0 },
3409 },
3410
3411 /* PREFIX_0F7C */
3412 {
3413 { Bad_Opcode },
3414 { Bad_Opcode },
3415 { "Vhaddpd", { XM, Vex, EXx }, 0 },
3416 { "Vhaddps", { XM, Vex, EXx }, 0 },
3417 },
3418
3419 /* PREFIX_0F7D */
3420 {
3421 { Bad_Opcode },
3422 { Bad_Opcode },
3423 { "Vhsubpd", { XM, Vex, EXx }, 0 },
3424 { "Vhsubps", { XM, Vex, EXx }, 0 },
3425 },
3426
3427 /* PREFIX_0F7E */
3428 {
3429 { "movK", { Edq, MX }, PREFIX_OPCODE },
3430 { "movq", { XM, EXq }, PREFIX_OPCODE },
3431 { "movK", { Edq, XM }, PREFIX_OPCODE },
3432 },
3433
3434 /* PREFIX_0F7F */
3435 {
3436 { "movq", { EMS, MX }, PREFIX_OPCODE },
3437 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3438 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3439 },
3440
3441 /* PREFIX_0FAE_REG_0_MOD_3 */
3442 {
3443 { Bad_Opcode },
3444 { "rdfsbase", { Ev }, 0 },
3445 },
3446
3447 /* PREFIX_0FAE_REG_1_MOD_3 */
3448 {
3449 { Bad_Opcode },
3450 { "rdgsbase", { Ev }, 0 },
3451 },
3452
3453 /* PREFIX_0FAE_REG_2_MOD_3 */
3454 {
3455 { Bad_Opcode },
3456 { "wrfsbase", { Ev }, 0 },
3457 },
3458
3459 /* PREFIX_0FAE_REG_3_MOD_3 */
3460 {
3461 { Bad_Opcode },
3462 { "wrgsbase", { Ev }, 0 },
3463 },
3464
3465 /* PREFIX_0FAE_REG_4_MOD_0 */
3466 {
3467 { "xsave", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3468 { "ptwrite{%LQ|}", { Edq }, 0 },
3469 },
3470
3471 /* PREFIX_0FAE_REG_4_MOD_3 */
3472 {
3473 { Bad_Opcode },
3474 { "ptwrite{%LQ|}", { Edq }, 0 },
3475 },
3476
3477 /* PREFIX_0FAE_REG_5_MOD_3 */
3478 {
3479 { "lfence", { Skip_MODRM }, 0 },
3480 { "incsspK", { Edq }, PREFIX_OPCODE },
3481 },
3482
3483 /* PREFIX_0FAE_REG_6_MOD_0 */
3484 {
3485 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3486 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3487 { "clwb", { Mb }, PREFIX_OPCODE },
3488 },
3489
3490 /* PREFIX_0FAE_REG_6_MOD_3 */
3491 {
3492 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3493 { "umonitor", { Eva }, PREFIX_OPCODE },
3494 { "tpause", { Edq }, PREFIX_OPCODE },
3495 { "umwait", { Edq }, PREFIX_OPCODE },
3496 },
3497
3498 /* PREFIX_0FAE_REG_7_MOD_0 */
3499 {
3500 { "clflush", { Mb }, 0 },
3501 { Bad_Opcode },
3502 { "clflushopt", { Mb }, 0 },
3503 },
3504
3505 /* PREFIX_0FB8 */
3506 {
3507 { Bad_Opcode },
3508 { "popcntS", { Gv, Ev }, 0 },
3509 },
3510
3511 /* PREFIX_0FBC */
3512 {
3513 { "bsfS", { Gv, Ev }, 0 },
3514 { "tzcntS", { Gv, Ev }, 0 },
3515 { "bsfS", { Gv, Ev }, 0 },
3516 },
3517
3518 /* PREFIX_0FBD */
3519 {
3520 { "bsrS", { Gv, Ev }, 0 },
3521 { "lzcntS", { Gv, Ev }, 0 },
3522 { "bsrS", { Gv, Ev }, 0 },
3523 },
3524
3525 /* PREFIX_0FC2 */
3526 {
3527 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3528 { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3529 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3530 { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3531 },
3532
3533 /* PREFIX_0FC7_REG_6_MOD_0 */
3534 {
3535 { "vmptrld",{ Mq }, 0 },
3536 { "vmxon", { Mq }, 0 },
3537 { "vmclear",{ Mq }, 0 },
3538 },
3539
3540 /* PREFIX_0FC7_REG_6_MOD_3 */
3541 {
3542 { "rdrand", { Ev }, 0 },
3543 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3544 { "rdrand", { Ev }, 0 }
3545 },
3546
3547 /* PREFIX_0FC7_REG_7_MOD_3 */
3548 {
3549 { "rdseed", { Ev }, 0 },
3550 { "rdpid", { Em }, 0 },
3551 { "rdseed", { Ev }, 0 },
3552 },
3553
3554 /* PREFIX_0FD0 */
3555 {
3556 { Bad_Opcode },
3557 { Bad_Opcode },
3558 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3559 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3560 },
3561
3562 /* PREFIX_0FD6 */
3563 {
3564 { Bad_Opcode },
3565 { "movq2dq",{ XM, Nq }, 0 },
3566 { "movq", { EXqS, XM }, 0 },
3567 { "movdq2q",{ MX, Ux }, 0 },
3568 },
3569
3570 /* PREFIX_0FE6 */
3571 {
3572 { Bad_Opcode },
3573 { "Vcvtdq2pd", { XM, EXxmmq }, 0 },
3574 { "Vcvttpd2dq%XY", { XMM, EXx }, 0 },
3575 { "Vcvtpd2dq%XY", { XMM, EXx }, 0 },
3576 },
3577
3578 /* PREFIX_0FE7 */
3579 {
3580 { "movntq", { Mq, MX }, 0 },
3581 { Bad_Opcode },
3582 { "movntdq", { Mx, XM }, 0 },
3583 },
3584
3585 /* PREFIX_0FF0 */
3586 {
3587 { Bad_Opcode },
3588 { Bad_Opcode },
3589 { Bad_Opcode },
3590 { "Vlddqu", { XM, M }, 0 },
3591 },
3592
3593 /* PREFIX_0FF7 */
3594 {
3595 { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3596 { Bad_Opcode },
3597 { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3598 },
3599
3600 /* PREFIX_0F38D8 */
3601 {
3602 { Bad_Opcode },
3603 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3604 },
3605
3606 /* PREFIX_0F38DC */
3607 {
3608 { Bad_Opcode },
3609 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3610 { "aesenc", { XM, EXx }, 0 },
3611 },
3612
3613 /* PREFIX_0F38DD */
3614 {
3615 { Bad_Opcode },
3616 { "aesdec128kl", { XM, M }, 0 },
3617 { "aesenclast", { XM, EXx }, 0 },
3618 },
3619
3620 /* PREFIX_0F38DE */
3621 {
3622 { Bad_Opcode },
3623 { "aesenc256kl", { XM, M }, 0 },
3624 { "aesdec", { XM, EXx }, 0 },
3625 },
3626
3627 /* PREFIX_0F38DF */
3628 {
3629 { Bad_Opcode },
3630 { "aesdec256kl", { XM, M }, 0 },
3631 { "aesdeclast", { XM, EXx }, 0 },
3632 },
3633
3634 /* PREFIX_0F38F0 */
3635 {
3636 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3637 { Bad_Opcode },
3638 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3639 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3640 },
3641
3642 /* PREFIX_0F38F1 */
3643 {
3644 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3645 { Bad_Opcode },
3646 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3647 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3648 },
3649
3650 /* PREFIX_0F38F6 */
3651 {
3652 { "wrssK", { M, Gdq }, 0 },
3653 { "adoxL", { VexGdq, Gdq, Edq }, 0 },
3654 { "adcxL", { VexGdq, Gdq, Edq }, 0 },
3655 { Bad_Opcode },
3656 },
3657
3658 /* PREFIX_0F38F8_M_0 */
3659 {
3660 { Bad_Opcode },
3661 { "enqcmds", { Gva, M }, 0 },
3662 { "movdir64b", { Gva, M }, 0 },
3663 { "enqcmd", { Gva, M }, 0 },
3664 },
3665
3666 /* PREFIX_0F38F8_M_1_X86_64 */
3667 {
3668 { Bad_Opcode },
3669 { "uwrmsr", { Gq, Rq }, 0 },
3670 { Bad_Opcode },
3671 { "urdmsr", { Rq, Gq }, 0 },
3672 },
3673
3674 /* PREFIX_0F38FA */
3675 {
3676 { Bad_Opcode },
3677 { "encodekey128", { Gd, Rd }, 0 },
3678 },
3679
3680 /* PREFIX_0F38FB */
3681 {
3682 { Bad_Opcode },
3683 { "encodekey256", { Gd, Rd }, 0 },
3684 },
3685
3686 /* PREFIX_0F38FC */
3687 {
3688 { "aadd", { Mdq, Gdq }, 0 },
3689 { "axor", { Mdq, Gdq }, 0 },
3690 { "aand", { Mdq, Gdq }, 0 },
3691 { "aor", { Mdq, Gdq }, 0 },
3692 },
3693
3694 /* PREFIX_0F3A0F */
3695 {
3696 { Bad_Opcode },
3697 { REG_TABLE (REG_0F3A0F_P_1) },
3698 },
3699
3700 /* PREFIX_VEX_0F12 */
3701 {
3702 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3703 { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3704 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3705 { "%XEvmov%XDdup", { XM, EXymmq }, 0 },
3706 },
3707
3708 /* PREFIX_VEX_0F16 */
3709 {
3710 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3711 { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3712 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3713 },
3714
3715 /* PREFIX_VEX_0F2A */
3716 {
3717 { Bad_Opcode },
3718 { "%XEvcvtsi2ssY{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3719 { Bad_Opcode },
3720 { "%XEvcvtsi2sdY{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3721 },
3722
3723 /* PREFIX_VEX_0F2C */
3724 {
3725 { Bad_Opcode },
3726 { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3727 { Bad_Opcode },
3728 { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3729 },
3730
3731 /* PREFIX_VEX_0F2D */
3732 {
3733 { Bad_Opcode },
3734 { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3735 { Bad_Opcode },
3736 { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3737 },
3738
3739 /* PREFIX_VEX_0F41_L_1_W_0 */
3740 {
3741 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
3742 { Bad_Opcode },
3743 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
3744 },
3745
3746 /* PREFIX_VEX_0F41_L_1_W_1 */
3747 {
3748 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
3749 { Bad_Opcode },
3750 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
3751 },
3752
3753 /* PREFIX_VEX_0F42_L_1_W_0 */
3754 {
3755 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
3756 { Bad_Opcode },
3757 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
3758 },
3759
3760 /* PREFIX_VEX_0F42_L_1_W_1 */
3761 {
3762 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
3763 { Bad_Opcode },
3764 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
3765 },
3766
3767 /* PREFIX_VEX_0F44_L_0_W_0 */
3768 {
3769 { "knotw", { MaskG, MaskR }, 0 },
3770 { Bad_Opcode },
3771 { "knotb", { MaskG, MaskR }, 0 },
3772 },
3773
3774 /* PREFIX_VEX_0F44_L_0_W_1 */
3775 {
3776 { "knotq", { MaskG, MaskR }, 0 },
3777 { Bad_Opcode },
3778 { "knotd", { MaskG, MaskR }, 0 },
3779 },
3780
3781 /* PREFIX_VEX_0F45_L_1_W_0 */
3782 {
3783 { "korw", { MaskG, MaskVex, MaskR }, 0 },
3784 { Bad_Opcode },
3785 { "korb", { MaskG, MaskVex, MaskR }, 0 },
3786 },
3787
3788 /* PREFIX_VEX_0F45_L_1_W_1 */
3789 {
3790 { "korq", { MaskG, MaskVex, MaskR }, 0 },
3791 { Bad_Opcode },
3792 { "kord", { MaskG, MaskVex, MaskR }, 0 },
3793 },
3794
3795 /* PREFIX_VEX_0F46_L_1_W_0 */
3796 {
3797 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
3798 { Bad_Opcode },
3799 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
3800 },
3801
3802 /* PREFIX_VEX_0F46_L_1_W_1 */
3803 {
3804 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
3805 { Bad_Opcode },
3806 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
3807 },
3808
3809 /* PREFIX_VEX_0F47_L_1_W_0 */
3810 {
3811 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
3812 { Bad_Opcode },
3813 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
3814 },
3815
3816 /* PREFIX_VEX_0F47_L_1_W_1 */
3817 {
3818 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
3819 { Bad_Opcode },
3820 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
3821 },
3822
3823 /* PREFIX_VEX_0F4A_L_1_W_0 */
3824 {
3825 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
3826 { Bad_Opcode },
3827 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
3828 },
3829
3830 /* PREFIX_VEX_0F4A_L_1_W_1 */
3831 {
3832 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
3833 { Bad_Opcode },
3834 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
3835 },
3836
3837 /* PREFIX_VEX_0F4B_L_1_W_0 */
3838 {
3839 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
3840 { Bad_Opcode },
3841 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
3842 },
3843
3844 /* PREFIX_VEX_0F4B_L_1_W_1 */
3845 {
3846 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
3847 },
3848
3849 /* PREFIX_VEX_0F6F */
3850 {
3851 { Bad_Opcode },
3852 { "vmovdqu", { XM, EXx }, 0 },
3853 { "vmovdqa", { XM, EXx }, 0 },
3854 },
3855
3856 /* PREFIX_VEX_0F70 */
3857 {
3858 { Bad_Opcode },
3859 { "vpshufhw", { XM, EXx, Ib }, 0 },
3860 { "vpshufd", { XM, EXx, Ib }, 0 },
3861 { "vpshuflw", { XM, EXx, Ib }, 0 },
3862 },
3863
3864 /* PREFIX_VEX_0F7E */
3865 {
3866 { Bad_Opcode },
3867 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3868 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3869 },
3870
3871 /* PREFIX_VEX_0F7F */
3872 {
3873 { Bad_Opcode },
3874 { "vmovdqu", { EXxS, XM }, 0 },
3875 { "vmovdqa", { EXxS, XM }, 0 },
3876 },
3877
3878 /* PREFIX_VEX_0F90_L_0_W_0 */
3879 {
3880 { "%XEkmovw", { MaskG, MaskE }, 0 },
3881 { Bad_Opcode },
3882 { "%XEkmovb", { MaskG, MaskBDE }, 0 },
3883 },
3884
3885 /* PREFIX_VEX_0F90_L_0_W_1 */
3886 {
3887 { "%XEkmovq", { MaskG, MaskE }, 0 },
3888 { Bad_Opcode },
3889 { "%XEkmovd", { MaskG, MaskBDE }, 0 },
3890 },
3891
3892 /* PREFIX_VEX_0F91_L_0_W_0 */
3893 {
3894 { "%XEkmovw", { Mw, MaskG }, 0 },
3895 { Bad_Opcode },
3896 { "%XEkmovb", { Mb, MaskG }, 0 },
3897 },
3898
3899 /* PREFIX_VEX_0F91_L_0_W_1 */
3900 {
3901 { "%XEkmovq", { Mq, MaskG }, 0 },
3902 { Bad_Opcode },
3903 { "%XEkmovd", { Md, MaskG }, 0 },
3904 },
3905
3906 /* PREFIX_VEX_0F92_L_0_W_0 */
3907 {
3908 { "%XEkmovw", { MaskG, Rdq }, 0 },
3909 { Bad_Opcode },
3910 { "%XEkmovb", { MaskG, Rdq }, 0 },
3911 { "%XEkmovd", { MaskG, Rdq }, 0 },
3912 },
3913
3914 /* PREFIX_VEX_0F92_L_0_W_1 */
3915 {
3916 { Bad_Opcode },
3917 { Bad_Opcode },
3918 { Bad_Opcode },
3919 { "%XEkmovK", { MaskG, Rdq }, 0 },
3920 },
3921
3922 /* PREFIX_VEX_0F93_L_0_W_0 */
3923 {
3924 { "%XEkmovw", { Gdq, MaskR }, 0 },
3925 { Bad_Opcode },
3926 { "%XEkmovb", { Gdq, MaskR }, 0 },
3927 { "%XEkmovd", { Gdq, MaskR }, 0 },
3928 },
3929
3930 /* PREFIX_VEX_0F93_L_0_W_1 */
3931 {
3932 { Bad_Opcode },
3933 { Bad_Opcode },
3934 { Bad_Opcode },
3935 { "%XEkmovK", { Gdq, MaskR }, 0 },
3936 },
3937
3938 /* PREFIX_VEX_0F98_L_0_W_0 */
3939 {
3940 { "kortestw", { MaskG, MaskR }, 0 },
3941 { Bad_Opcode },
3942 { "kortestb", { MaskG, MaskR }, 0 },
3943 },
3944
3945 /* PREFIX_VEX_0F98_L_0_W_1 */
3946 {
3947 { "kortestq", { MaskG, MaskR }, 0 },
3948 { Bad_Opcode },
3949 { "kortestd", { MaskG, MaskR }, 0 },
3950 },
3951
3952 /* PREFIX_VEX_0F99_L_0_W_0 */
3953 {
3954 { "ktestw", { MaskG, MaskR }, 0 },
3955 { Bad_Opcode },
3956 { "ktestb", { MaskG, MaskR }, 0 },
3957 },
3958
3959 /* PREFIX_VEX_0F99_L_0_W_1 */
3960 {
3961 { "ktestq", { MaskG, MaskR }, 0 },
3962 { Bad_Opcode },
3963 { "ktestd", { MaskG, MaskR }, 0 },
3964 },
3965
3966 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
3967 {
3968 { "ldtilecfg", { M }, 0 },
3969 { Bad_Opcode },
3970 { "sttilecfg", { M }, 0 },
3971 },
3972
3973 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
3974 {
3975 { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
3976 { Bad_Opcode },
3977 { Bad_Opcode },
3978 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
3979 },
3980
3981 /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
3982 {
3983 { Bad_Opcode },
3984 { "tilestored", { MVexSIBMEM, TMM }, 0 },
3985 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
3986 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
3987 },
3988
3989 /* PREFIX_VEX_0F3850_W_0 */
3990 {
3991 { "vpdpbuud", { XM, Vex, EXx }, 0 },
3992 { "vpdpbsud", { XM, Vex, EXx }, 0 },
3993 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 },
3994 { "vpdpbssd", { XM, Vex, EXx }, 0 },
3995 },
3996
3997 /* PREFIX_VEX_0F3851_W_0 */
3998 {
3999 { "vpdpbuuds", { XM, Vex, EXx }, 0 },
4000 { "vpdpbsuds", { XM, Vex, EXx }, 0 },
4001 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
4002 { "vpdpbssds", { XM, Vex, EXx }, 0 },
4003 },
4004 /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4005 {
4006 { Bad_Opcode },
4007 { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4008 { Bad_Opcode },
4009 { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4010 },
4011
4012 /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4013 {
4014 { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4015 { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4016 { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4017 { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4018 },
4019
4020 /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4021 {
4022 { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4023 { Bad_Opcode },
4024 { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4025 },
4026
4027 /* PREFIX_VEX_0F3872 */
4028 {
4029 { Bad_Opcode },
4030 { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4031 },
4032
4033 /* PREFIX_VEX_0F38B0_W_0 */
4034 {
4035 { "vcvtneoph2ps", { XM, Mx }, 0 },
4036 { "vcvtneebf162ps", { XM, Mx }, 0 },
4037 { "vcvtneeph2ps", { XM, Mx }, 0 },
4038 { "vcvtneobf162ps", { XM, Mx }, 0 },
4039 },
4040
4041 /* PREFIX_VEX_0F38B1_W_0 */
4042 {
4043 { Bad_Opcode },
4044 { "vbcstnebf162ps", { XM, Mw }, 0 },
4045 { "vbcstnesh2ps", { XM, Mw }, 0 },
4046 },
4047
4048 /* PREFIX_VEX_0F38D2_W_0 */
4049 {
4050 { "vpdpwuud", { XM, Vex, EXx }, 0 },
4051 { "vpdpwsud", { XM, Vex, EXx }, 0 },
4052 { "vpdpwusd", { XM, Vex, EXx }, 0 },
4053 },
4054
4055 /* PREFIX_VEX_0F38D3_W_0 */
4056 {
4057 { "vpdpwuuds", { XM, Vex, EXx }, 0 },
4058 { "vpdpwsuds", { XM, Vex, EXx }, 0 },
4059 { "vpdpwusds", { XM, Vex, EXx }, 0 },
4060 },
4061
4062 /* PREFIX_VEX_0F38CB */
4063 {
4064 { Bad_Opcode },
4065 { Bad_Opcode },
4066 { Bad_Opcode },
4067 { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4068 },
4069
4070 /* PREFIX_VEX_0F38CC */
4071 {
4072 { Bad_Opcode },
4073 { Bad_Opcode },
4074 { Bad_Opcode },
4075 { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4076 },
4077
4078 /* PREFIX_VEX_0F38CD */
4079 {
4080 { Bad_Opcode },
4081 { Bad_Opcode },
4082 { Bad_Opcode },
4083 { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4084 },
4085
4086 /* PREFIX_VEX_0F38DA_W_0 */
4087 {
4088 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4089 { "vsm4key4", { XM, Vex, EXx }, 0 },
4090 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4091 { "vsm4rnds4", { XM, Vex, EXx }, 0 },
4092 },
4093
4094 /* PREFIX_VEX_0F38F2_L_0 */
4095 {
4096 { "%NFandnS", { Gdq, VexGdq, Edq }, 0 },
4097 },
4098
4099 /* PREFIX_VEX_0F38F3_L_0 */
4100 {
4101 { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4102 },
4103
4104 /* PREFIX_VEX_0F38F5_L_0 */
4105 {
4106 { "%NFbzhiS", { Gdq, Edq, VexGdq }, 0 },
4107 { "%XEpextS", { Gdq, VexGdq, Edq }, 0 },
4108 { Bad_Opcode },
4109 { "%XEpdepS", { Gdq, VexGdq, Edq }, 0 },
4110 },
4111
4112 /* PREFIX_VEX_0F38F6_L_0 */
4113 {
4114 { Bad_Opcode },
4115 { Bad_Opcode },
4116 { Bad_Opcode },
4117 { "%XEmulxS", { Gdq, VexGdq, Edq }, 0 },
4118 },
4119
4120 /* PREFIX_VEX_0F38F7_L_0 */
4121 {
4122 { "%NFbextrS", { Gdq, Edq, VexGdq }, 0 },
4123 { "%XEsarxS", { Gdq, Edq, VexGdq }, 0 },
4124 { "%XEshlxS", { Gdq, Edq, VexGdq }, 0 },
4125 { "%XEshrxS", { Gdq, Edq, VexGdq }, 0 },
4126 },
4127
4128 /* PREFIX_VEX_0F3AF0_L_0 */
4129 {
4130 { Bad_Opcode },
4131 { Bad_Opcode },
4132 { Bad_Opcode },
4133 { "%XErorxS", { Gdq, Edq, Ib }, 0 },
4134 },
4135
4136 /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4137 {
4138 { Bad_Opcode },
4139 { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4140 { Bad_Opcode },
4141 { "urdmsr", { Rq, Id }, 0 },
4142 },
4143
4144 #include "i386-dis-evex-prefix.h"
4145 };
4146
4147 static const struct dis386 x86_64_table[][2] = {
4148 /* X86_64_06 */
4149 {
4150 { "pushP", { es }, 0 },
4151 },
4152
4153 /* X86_64_07 */
4154 {
4155 { "popP", { es }, 0 },
4156 },
4157
4158 /* X86_64_0E */
4159 {
4160 { "pushP", { cs }, 0 },
4161 },
4162
4163 /* X86_64_16 */
4164 {
4165 { "pushP", { ss }, 0 },
4166 },
4167
4168 /* X86_64_17 */
4169 {
4170 { "popP", { ss }, 0 },
4171 },
4172
4173 /* X86_64_1E */
4174 {
4175 { "pushP", { ds }, 0 },
4176 },
4177
4178 /* X86_64_1F */
4179 {
4180 { "popP", { ds }, 0 },
4181 },
4182
4183 /* X86_64_27 */
4184 {
4185 { "daa", { XX }, 0 },
4186 },
4187
4188 /* X86_64_2F */
4189 {
4190 { "das", { XX }, 0 },
4191 },
4192
4193 /* X86_64_37 */
4194 {
4195 { "aaa", { XX }, 0 },
4196 },
4197
4198 /* X86_64_3F */
4199 {
4200 { "aas", { XX }, 0 },
4201 },
4202
4203 /* X86_64_60 */
4204 {
4205 { "pushaP", { XX }, 0 },
4206 },
4207
4208 /* X86_64_61 */
4209 {
4210 { "popaP", { XX }, 0 },
4211 },
4212
4213 /* X86_64_62 */
4214 {
4215 { MOD_TABLE (MOD_62_32BIT) },
4216 { EVEX_TABLE () },
4217 },
4218
4219 /* X86_64_63 */
4220 {
4221 { "arplS", { Sv, Gv }, 0 },
4222 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4223 },
4224
4225 /* X86_64_6D */
4226 {
4227 { "ins{R|}", { Yzr, indirDX }, 0 },
4228 { "ins{G|}", { Yzr, indirDX }, 0 },
4229 },
4230
4231 /* X86_64_6F */
4232 {
4233 { "outs{R|}", { indirDXr, Xz }, 0 },
4234 { "outs{G|}", { indirDXr, Xz }, 0 },
4235 },
4236
4237 /* X86_64_82 */
4238 {
4239 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4240 { REG_TABLE (REG_80) },
4241 },
4242
4243 /* X86_64_9A */
4244 {
4245 { "{l|}call{P|}", { Ap }, 0 },
4246 },
4247
4248 /* X86_64_C2 */
4249 {
4250 { "retP", { Iw, BND }, 0 },
4251 { "ret@", { Iw, BND }, 0 },
4252 },
4253
4254 /* X86_64_C3 */
4255 {
4256 { "retP", { BND }, 0 },
4257 { "ret@", { BND }, 0 },
4258 },
4259
4260 /* X86_64_C4 */
4261 {
4262 { MOD_TABLE (MOD_C4_32BIT) },
4263 { VEX_C4_TABLE () },
4264 },
4265
4266 /* X86_64_C5 */
4267 {
4268 { MOD_TABLE (MOD_C5_32BIT) },
4269 { VEX_C5_TABLE () },
4270 },
4271
4272 /* X86_64_CE */
4273 {
4274 { "into", { XX }, 0 },
4275 },
4276
4277 /* X86_64_D4 */
4278 {
4279 { "aam", { Ib }, 0 },
4280 },
4281
4282 /* X86_64_D5 */
4283 {
4284 { "aad", { Ib }, 0 },
4285 },
4286
4287 /* X86_64_E8 */
4288 {
4289 { "callP", { Jv, BND }, 0 },
4290 { "call@", { Jv, BND }, PREFIX_REX2_ILLEGAL }
4291 },
4292
4293 /* X86_64_E9 */
4294 {
4295 { "jmpP", { Jv, BND }, 0 },
4296 { "jmp@", { Jv, BND }, PREFIX_REX2_ILLEGAL }
4297 },
4298
4299 /* X86_64_EA */
4300 {
4301 { "{l|}jmp{P|}", { Ap }, 0 },
4302 },
4303
4304 /* X86_64_0F00_REG_6 */
4305 {
4306 { Bad_Opcode },
4307 { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4308 },
4309
4310 /* X86_64_0F01_REG_0 */
4311 {
4312 { "sgdt{Q|Q}", { M }, 0 },
4313 { "sgdt", { M }, 0 },
4314 },
4315
4316 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4317 {
4318 { Bad_Opcode },
4319 { "wrmsrlist", { Skip_MODRM }, 0 },
4320 },
4321
4322 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4323 {
4324 { Bad_Opcode },
4325 { "rdmsrlist", { Skip_MODRM }, 0 },
4326 },
4327
4328 /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4329 {
4330 { Bad_Opcode },
4331 { "pbndkb", { Skip_MODRM }, 0 },
4332 },
4333
4334 /* X86_64_0F01_REG_1 */
4335 {
4336 { "sidt{Q|Q}", { M }, 0 },
4337 { "sidt", { M }, 0 },
4338 },
4339
4340 /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4341 {
4342 { Bad_Opcode },
4343 { "eretu", { Skip_MODRM }, 0 },
4344 },
4345
4346 /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4347 {
4348 { Bad_Opcode },
4349 { "erets", { Skip_MODRM }, 0 },
4350 },
4351
4352 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4353 {
4354 { Bad_Opcode },
4355 { "seamret", { Skip_MODRM }, 0 },
4356 },
4357
4358 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4359 {
4360 { Bad_Opcode },
4361 { "seamops", { Skip_MODRM }, 0 },
4362 },
4363
4364 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4365 {
4366 { Bad_Opcode },
4367 { "seamcall", { Skip_MODRM }, 0 },
4368 },
4369
4370 /* X86_64_0F01_REG_2 */
4371 {
4372 { "lgdt{Q|Q}", { M }, 0 },
4373 { "lgdt", { M }, 0 },
4374 },
4375
4376 /* X86_64_0F01_REG_3 */
4377 {
4378 { "lidt{Q|Q}", { M }, 0 },
4379 { "lidt", { M }, 0 },
4380 },
4381
4382 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4383 {
4384 { Bad_Opcode },
4385 { "uiret", { Skip_MODRM }, 0 },
4386 },
4387
4388 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4389 {
4390 { Bad_Opcode },
4391 { "testui", { Skip_MODRM }, 0 },
4392 },
4393
4394 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4395 {
4396 { Bad_Opcode },
4397 { "clui", { Skip_MODRM }, 0 },
4398 },
4399
4400 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4401 {
4402 { Bad_Opcode },
4403 { "stui", { Skip_MODRM }, 0 },
4404 },
4405
4406 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4407 {
4408 { Bad_Opcode },
4409 { "rmpquery", { Skip_MODRM }, 0 },
4410 },
4411
4412 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4413 {
4414 { Bad_Opcode },
4415 { "rmpadjust", { Skip_MODRM }, 0 },
4416 },
4417
4418 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4419 {
4420 { Bad_Opcode },
4421 { "rmpupdate", { Skip_MODRM }, 0 },
4422 },
4423
4424 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4425 {
4426 { Bad_Opcode },
4427 { "psmash", { Skip_MODRM }, 0 },
4428 },
4429
4430 /* X86_64_0F18_REG_6_MOD_0 */
4431 {
4432 { "nopQ", { Ev }, 0 },
4433 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4434 },
4435
4436 /* X86_64_0F18_REG_7_MOD_0 */
4437 {
4438 { "nopQ", { Ev }, 0 },
4439 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4440 },
4441
4442 {
4443 /* X86_64_0F24 */
4444 { "movZ", { Em, Td }, 0 },
4445 },
4446
4447 {
4448 /* X86_64_0F26 */
4449 { "movZ", { Td, Em }, 0 },
4450 },
4451
4452 {
4453 /* X86_64_0F38F8_M_1 */
4454 { Bad_Opcode },
4455 { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4456 },
4457
4458 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4459 {
4460 { Bad_Opcode },
4461 { "senduipi", { Eq }, 0 },
4462 },
4463
4464 /* X86_64_VEX_0F3849 */
4465 {
4466 { Bad_Opcode },
4467 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4468 },
4469
4470 /* X86_64_VEX_0F384B */
4471 {
4472 { Bad_Opcode },
4473 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4474 },
4475
4476 /* X86_64_VEX_0F385C */
4477 {
4478 { Bad_Opcode },
4479 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4480 },
4481
4482 /* X86_64_VEX_0F385E */
4483 {
4484 { Bad_Opcode },
4485 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4486 },
4487
4488 /* X86_64_VEX_0F386C */
4489 {
4490 { Bad_Opcode },
4491 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4492 },
4493
4494 /* X86_64_VEX_0F38Ex */
4495 {
4496 { Bad_Opcode },
4497 { "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4498 },
4499
4500 /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4501 {
4502 { Bad_Opcode },
4503 { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4504 },
4505 };
4506
4507 static const struct dis386 three_byte_table[][256] = {
4508
4509 /* THREE_BYTE_0F38 */
4510 {
4511 /* 00 */
4512 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4513 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4514 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4515 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4516 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4517 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4518 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4519 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4520 /* 08 */
4521 { "psignb", { MX, EM }, PREFIX_OPCODE },
4522 { "psignw", { MX, EM }, PREFIX_OPCODE },
4523 { "psignd", { MX, EM }, PREFIX_OPCODE },
4524 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4525 { Bad_Opcode },
4526 { Bad_Opcode },
4527 { Bad_Opcode },
4528 { Bad_Opcode },
4529 /* 10 */
4530 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { Bad_Opcode },
4534 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4535 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4536 { Bad_Opcode },
4537 { "ptest", { XM, EXx }, PREFIX_DATA },
4538 /* 18 */
4539 { Bad_Opcode },
4540 { Bad_Opcode },
4541 { Bad_Opcode },
4542 { Bad_Opcode },
4543 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4544 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4545 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4546 { Bad_Opcode },
4547 /* 20 */
4548 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4549 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4550 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4551 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4552 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4553 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 /* 28 */
4557 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4558 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4559 { "movntdqa", { XM, Mx }, PREFIX_DATA },
4560 { "packusdw", { XM, EXx }, PREFIX_DATA },
4561 { Bad_Opcode },
4562 { Bad_Opcode },
4563 { Bad_Opcode },
4564 { Bad_Opcode },
4565 /* 30 */
4566 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4567 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4568 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4569 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4570 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4571 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4572 { Bad_Opcode },
4573 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4574 /* 38 */
4575 { "pminsb", { XM, EXx }, PREFIX_DATA },
4576 { "pminsd", { XM, EXx }, PREFIX_DATA },
4577 { "pminuw", { XM, EXx }, PREFIX_DATA },
4578 { "pminud", { XM, EXx }, PREFIX_DATA },
4579 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4580 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4581 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4582 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4583 /* 40 */
4584 { "pmulld", { XM, EXx }, PREFIX_DATA },
4585 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4586 { Bad_Opcode },
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 { Bad_Opcode },
4592 /* 48 */
4593 { Bad_Opcode },
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 /* 50 */
4602 { Bad_Opcode },
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 /* 58 */
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { Bad_Opcode },
4618 { Bad_Opcode },
4619 /* 60 */
4620 { Bad_Opcode },
4621 { Bad_Opcode },
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 { Bad_Opcode },
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 /* 68 */
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 /* 70 */
4638 { Bad_Opcode },
4639 { Bad_Opcode },
4640 { Bad_Opcode },
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 /* 78 */
4647 { Bad_Opcode },
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 { Bad_Opcode },
4655 /* 80 */
4656 { "invept", { Gm, Mo }, PREFIX_DATA },
4657 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4658 { "invpcid", { Gm, M }, PREFIX_DATA },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 /* 88 */
4665 { Bad_Opcode },
4666 { Bad_Opcode },
4667 { Bad_Opcode },
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 /* 90 */
4674 { Bad_Opcode },
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 /* 98 */
4683 { Bad_Opcode },
4684 { Bad_Opcode },
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 /* a0 */
4692 { Bad_Opcode },
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 /* a8 */
4701 { Bad_Opcode },
4702 { Bad_Opcode },
4703 { Bad_Opcode },
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 /* b0 */
4710 { Bad_Opcode },
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 /* b8 */
4719 { Bad_Opcode },
4720 { Bad_Opcode },
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 /* c0 */
4728 { Bad_Opcode },
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 /* c8 */
4737 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4738 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4739 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4740 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4741 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4742 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4743 { Bad_Opcode },
4744 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4745 /* d0 */
4746 { Bad_Opcode },
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 /* d8 */
4755 { PREFIX_TABLE (PREFIX_0F38D8) },
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { "aesimc", { XM, EXx }, PREFIX_DATA },
4759 { PREFIX_TABLE (PREFIX_0F38DC) },
4760 { PREFIX_TABLE (PREFIX_0F38DD) },
4761 { PREFIX_TABLE (PREFIX_0F38DE) },
4762 { PREFIX_TABLE (PREFIX_0F38DF) },
4763 /* e0 */
4764 { Bad_Opcode },
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 /* e8 */
4773 { Bad_Opcode },
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 /* f0 */
4782 { PREFIX_TABLE (PREFIX_0F38F0) },
4783 { PREFIX_TABLE (PREFIX_0F38F1) },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { "wrussK", { M, Gdq }, PREFIX_DATA },
4788 { PREFIX_TABLE (PREFIX_0F38F6) },
4789 { Bad_Opcode },
4790 /* f8 */
4791 { MOD_TABLE (MOD_0F38F8) },
4792 { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE },
4793 { PREFIX_TABLE (PREFIX_0F38FA) },
4794 { PREFIX_TABLE (PREFIX_0F38FB) },
4795 { PREFIX_TABLE (PREFIX_0F38FC) },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 },
4800 /* THREE_BYTE_0F3A */
4801 {
4802 /* 00 */
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 { Bad_Opcode },
4811 /* 08 */
4812 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4813 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4814 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4815 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4816 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4817 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4818 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4819 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4820 /* 10 */
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4826 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4827 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4828 { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4829 /* 18 */
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 { Bad_Opcode },
4838 /* 20 */
4839 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4840 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4841 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 /* 28 */
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 /* 30 */
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 /* 38 */
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 { Bad_Opcode },
4873 { Bad_Opcode },
4874 /* 40 */
4875 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4876 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4877 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4878 { Bad_Opcode },
4879 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 /* 48 */
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 /* 50 */
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 { Bad_Opcode },
4901 /* 58 */
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 /* 60 */
4911 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4912 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4913 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4914 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 /* 68 */
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 /* 70 */
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 /* 78 */
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 /* 80 */
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 { Bad_Opcode },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 /* 88 */
4956 { Bad_Opcode },
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 /* 90 */
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 /* 98 */
4974 { Bad_Opcode },
4975 { Bad_Opcode },
4976 { Bad_Opcode },
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 /* a0 */
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 /* a8 */
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 /* b0 */
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 /* b8 */
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 { Bad_Opcode },
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 /* c0 */
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 /* c8 */
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5033 { Bad_Opcode },
5034 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5035 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5036 /* d0 */
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 /* d8 */
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5054 /* e0 */
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 /* e8 */
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 /* f0 */
5073 { PREFIX_TABLE (PREFIX_0F3A0F) },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 /* f8 */
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 },
5091 };
5092
5093 static const struct dis386 xop_table[][256] = {
5094 /* XOP_08 */
5095 {
5096 /* 00 */
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 /* 08 */
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 /* 10 */
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 /* 18 */
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 /* 20 */
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 /* 28 */
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 /* 30 */
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 /* 38 */
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 /* 40 */
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 /* 48 */
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 /* 50 */
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 /* 58 */
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 /* 60 */
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 /* 68 */
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 /* 70 */
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 /* 78 */
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 /* 80 */
5241 { Bad_Opcode },
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5247 { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5248 { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5249 /* 88 */
5250 { Bad_Opcode },
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5257 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5258 /* 90 */
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5265 { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5266 { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5267 /* 98 */
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5275 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5276 /* a0 */
5277 { Bad_Opcode },
5278 { Bad_Opcode },
5279 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5280 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5284 { Bad_Opcode },
5285 /* a8 */
5286 { Bad_Opcode },
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 /* b0 */
5295 { Bad_Opcode },
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5302 { Bad_Opcode },
5303 /* b8 */
5304 { Bad_Opcode },
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 /* c0 */
5313 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5314 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5315 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5316 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 /* c8 */
5322 { Bad_Opcode },
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5327 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5328 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5329 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5330 /* d0 */
5331 { Bad_Opcode },
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 /* d8 */
5340 { Bad_Opcode },
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 /* e0 */
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 /* e8 */
5358 { Bad_Opcode },
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5363 { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5364 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5365 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5366 /* f0 */
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 /* f8 */
5376 { Bad_Opcode },
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 },
5385 /* XOP_09 */
5386 {
5387 /* 00 */
5388 { Bad_Opcode },
5389 { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5390 { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 { Bad_Opcode },
5396 /* 08 */
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 /* 10 */
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 /* 18 */
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 /* 20 */
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 /* 28 */
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 /* 30 */
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 /* 38 */
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 /* 40 */
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 /* 48 */
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 /* 50 */
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 /* 58 */
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 /* 60 */
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 /* 68 */
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 /* 70 */
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 /* 78 */
5523 { Bad_Opcode },
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 /* 80 */
5532 { VEX_W_TABLE (VEX_W_XOP_09_80) },
5533 { VEX_W_TABLE (VEX_W_XOP_09_81) },
5534 { VEX_W_TABLE (VEX_W_XOP_09_82) },
5535 { VEX_W_TABLE (VEX_W_XOP_09_83) },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 /* 88 */
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 /* 90 */
5550 { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5551 { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5552 { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5553 { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5554 { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5555 { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5556 { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5557 { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5558 /* 98 */
5559 { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5560 { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5561 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5562 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 /* a0 */
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 /* a8 */
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 /* b0 */
5586 { Bad_Opcode },
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 /* b8 */
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 /* c0 */
5604 { Bad_Opcode },
5605 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5606 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5607 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5611 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5612 /* c8 */
5613 { Bad_Opcode },
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 /* d0 */
5622 { Bad_Opcode },
5623 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5624 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5625 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5629 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5630 /* d8 */
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 /* e0 */
5640 { Bad_Opcode },
5641 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5642 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5643 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 /* e8 */
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 /* f0 */
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 /* f8 */
5667 { Bad_Opcode },
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 },
5676 /* XOP_0A */
5677 {
5678 /* 00 */
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 /* 08 */
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 /* 10 */
5697 { "bextrS", { Gdq, Edq, Id }, 0 },
5698 { Bad_Opcode },
5699 { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 /* 18 */
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 /* 20 */
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 { Bad_Opcode },
5723 /* 28 */
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 { Bad_Opcode },
5732 /* 30 */
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { Bad_Opcode },
5740 { Bad_Opcode },
5741 /* 38 */
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 { Bad_Opcode },
5749 { Bad_Opcode },
5750 /* 40 */
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 /* 48 */
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { Bad_Opcode },
5767 { Bad_Opcode },
5768 /* 50 */
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 { Bad_Opcode },
5776 { Bad_Opcode },
5777 /* 58 */
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 /* 60 */
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 /* 68 */
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 /* 70 */
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 /* 78 */
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 /* 80 */
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 /* 88 */
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 /* 90 */
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 /* 98 */
5850 { Bad_Opcode },
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 /* a0 */
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 /* a8 */
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 /* b0 */
5877 { Bad_Opcode },
5878 { Bad_Opcode },
5879 { Bad_Opcode },
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 /* b8 */
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 /* c0 */
5895 { Bad_Opcode },
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 /* c8 */
5904 { Bad_Opcode },
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 /* d0 */
5913 { Bad_Opcode },
5914 { Bad_Opcode },
5915 { Bad_Opcode },
5916 { Bad_Opcode },
5917 { Bad_Opcode },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 /* d8 */
5922 { Bad_Opcode },
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 /* e0 */
5931 { Bad_Opcode },
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 /* e8 */
5940 { Bad_Opcode },
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 /* f0 */
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 /* f8 */
5958 { Bad_Opcode },
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 },
5967 };
5968
5969 static const struct dis386 vex_table[][256] = {
5970 /* VEX_0F */
5971 {
5972 /* 00 */
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 { Bad_Opcode },
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 /* 08 */
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 { Bad_Opcode },
5986 { Bad_Opcode },
5987 { Bad_Opcode },
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 /* 10 */
5991 { PREFIX_TABLE (PREFIX_0F10) },
5992 { PREFIX_TABLE (PREFIX_0F11) },
5993 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5994 { VEX_LEN_TABLE (VEX_LEN_0F13) },
5995 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5996 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5997 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5998 { VEX_LEN_TABLE (VEX_LEN_0F17) },
5999 /* 18 */
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 { Bad_Opcode },
6004 { Bad_Opcode },
6005 { Bad_Opcode },
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 /* 20 */
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 { Bad_Opcode },
6013 { Bad_Opcode },
6014 { Bad_Opcode },
6015 { Bad_Opcode },
6016 { Bad_Opcode },
6017 /* 28 */
6018 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
6019 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
6020 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6021 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
6022 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6023 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6024 { PREFIX_TABLE (PREFIX_0F2E) },
6025 { PREFIX_TABLE (PREFIX_0F2F) },
6026 /* 30 */
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 /* 38 */
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 { Bad_Opcode },
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 /* 40 */
6045 { Bad_Opcode },
6046 { VEX_LEN_TABLE (VEX_LEN_0F41) },
6047 { VEX_LEN_TABLE (VEX_LEN_0F42) },
6048 { Bad_Opcode },
6049 { VEX_LEN_TABLE (VEX_LEN_0F44) },
6050 { VEX_LEN_TABLE (VEX_LEN_0F45) },
6051 { VEX_LEN_TABLE (VEX_LEN_0F46) },
6052 { VEX_LEN_TABLE (VEX_LEN_0F47) },
6053 /* 48 */
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6057 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 /* 50 */
6063 { "vmovmskpX", { Gdq, Ux }, PREFIX_OPCODE },
6064 { PREFIX_TABLE (PREFIX_0F51) },
6065 { PREFIX_TABLE (PREFIX_0F52) },
6066 { PREFIX_TABLE (PREFIX_0F53) },
6067 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6068 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6069 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6070 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6071 /* 58 */
6072 { PREFIX_TABLE (PREFIX_0F58) },
6073 { PREFIX_TABLE (PREFIX_0F59) },
6074 { PREFIX_TABLE (PREFIX_0F5A) },
6075 { PREFIX_TABLE (PREFIX_0F5B) },
6076 { PREFIX_TABLE (PREFIX_0F5C) },
6077 { PREFIX_TABLE (PREFIX_0F5D) },
6078 { PREFIX_TABLE (PREFIX_0F5E) },
6079 { PREFIX_TABLE (PREFIX_0F5F) },
6080 /* 60 */
6081 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6082 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6083 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6084 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6085 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6086 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6087 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6088 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6089 /* 68 */
6090 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6091 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6092 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6093 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6094 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6095 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6096 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6097 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6098 /* 70 */
6099 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6100 { REG_TABLE (REG_VEX_0F71) },
6101 { REG_TABLE (REG_VEX_0F72) },
6102 { REG_TABLE (REG_VEX_0F73) },
6103 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6104 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6105 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6106 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6107 /* 78 */
6108 { Bad_Opcode },
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { PREFIX_TABLE (PREFIX_0F7C) },
6113 { PREFIX_TABLE (PREFIX_0F7D) },
6114 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6115 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6116 /* 80 */
6117 { Bad_Opcode },
6118 { Bad_Opcode },
6119 { Bad_Opcode },
6120 { Bad_Opcode },
6121 { Bad_Opcode },
6122 { Bad_Opcode },
6123 { Bad_Opcode },
6124 { Bad_Opcode },
6125 /* 88 */
6126 { Bad_Opcode },
6127 { Bad_Opcode },
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 { Bad_Opcode },
6132 { Bad_Opcode },
6133 { Bad_Opcode },
6134 /* 90 */
6135 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6136 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6137 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6138 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6139 { Bad_Opcode },
6140 { Bad_Opcode },
6141 { Bad_Opcode },
6142 { Bad_Opcode },
6143 /* 98 */
6144 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6145 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6146 { Bad_Opcode },
6147 { Bad_Opcode },
6148 { Bad_Opcode },
6149 { Bad_Opcode },
6150 { Bad_Opcode },
6151 { Bad_Opcode },
6152 /* a0 */
6153 { Bad_Opcode },
6154 { Bad_Opcode },
6155 { Bad_Opcode },
6156 { Bad_Opcode },
6157 { Bad_Opcode },
6158 { Bad_Opcode },
6159 { Bad_Opcode },
6160 { Bad_Opcode },
6161 /* a8 */
6162 { Bad_Opcode },
6163 { Bad_Opcode },
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { REG_TABLE (REG_VEX_0FAE) },
6169 { Bad_Opcode },
6170 /* b0 */
6171 { Bad_Opcode },
6172 { Bad_Opcode },
6173 { Bad_Opcode },
6174 { Bad_Opcode },
6175 { Bad_Opcode },
6176 { Bad_Opcode },
6177 { Bad_Opcode },
6178 { Bad_Opcode },
6179 /* b8 */
6180 { Bad_Opcode },
6181 { Bad_Opcode },
6182 { Bad_Opcode },
6183 { Bad_Opcode },
6184 { Bad_Opcode },
6185 { Bad_Opcode },
6186 { Bad_Opcode },
6187 { Bad_Opcode },
6188 /* c0 */
6189 { Bad_Opcode },
6190 { Bad_Opcode },
6191 { PREFIX_TABLE (PREFIX_0FC2) },
6192 { Bad_Opcode },
6193 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6194 { "vpextrw", { Gd, Uxmm, Ib }, PREFIX_DATA },
6195 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6196 { Bad_Opcode },
6197 /* c8 */
6198 { Bad_Opcode },
6199 { Bad_Opcode },
6200 { Bad_Opcode },
6201 { Bad_Opcode },
6202 { Bad_Opcode },
6203 { Bad_Opcode },
6204 { Bad_Opcode },
6205 { Bad_Opcode },
6206 /* d0 */
6207 { PREFIX_TABLE (PREFIX_0FD0) },
6208 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6209 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6210 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6211 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6212 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6213 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6214 { "vpmovmskb", { Gdq, Ux }, PREFIX_DATA },
6215 /* d8 */
6216 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6217 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6218 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6219 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6220 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6221 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6222 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6223 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6224 /* e0 */
6225 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6226 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6227 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6228 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6229 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6230 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6231 { PREFIX_TABLE (PREFIX_0FE6) },
6232 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
6233 /* e8 */
6234 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6235 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6236 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6237 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6238 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6239 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6240 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6241 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6242 /* f0 */
6243 { PREFIX_TABLE (PREFIX_0FF0) },
6244 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6245 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6246 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6247 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6248 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6249 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6250 { "vmaskmovdqu", { XM, Uxmm }, PREFIX_DATA },
6251 /* f8 */
6252 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6253 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6254 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6255 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6256 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6257 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6258 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6259 { Bad_Opcode },
6260 },
6261 /* VEX_0F38 */
6262 {
6263 /* 00 */
6264 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6265 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6266 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6267 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6268 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6269 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6270 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6271 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6272 /* 08 */
6273 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6274 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6275 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6276 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6277 { VEX_W_TABLE (VEX_W_0F380C) },
6278 { VEX_W_TABLE (VEX_W_0F380D) },
6279 { VEX_W_TABLE (VEX_W_0F380E) },
6280 { VEX_W_TABLE (VEX_W_0F380F) },
6281 /* 10 */
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { VEX_W_TABLE (VEX_W_0F3813) },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6289 { "vptest", { XM, EXx }, PREFIX_DATA },
6290 /* 18 */
6291 { VEX_W_TABLE (VEX_W_0F3818) },
6292 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6293 { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6294 { Bad_Opcode },
6295 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6296 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6297 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6298 { Bad_Opcode },
6299 /* 20 */
6300 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6301 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6302 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6303 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6304 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6305 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6306 { Bad_Opcode },
6307 { Bad_Opcode },
6308 /* 28 */
6309 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6310 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6311 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
6312 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6313 { VEX_W_TABLE (VEX_W_0F382C) },
6314 { VEX_W_TABLE (VEX_W_0F382D) },
6315 { VEX_W_TABLE (VEX_W_0F382E) },
6316 { VEX_W_TABLE (VEX_W_0F382F) },
6317 /* 30 */
6318 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6319 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6320 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6321 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6322 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6323 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6324 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6325 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6326 /* 38 */
6327 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6328 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6329 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6330 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6331 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6332 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6333 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6334 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6335 /* 40 */
6336 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6337 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6338 { Bad_Opcode },
6339 { Bad_Opcode },
6340 { Bad_Opcode },
6341 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6342 { VEX_W_TABLE (VEX_W_0F3846) },
6343 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6344 /* 48 */
6345 { Bad_Opcode },
6346 { X86_64_TABLE (X86_64_VEX_0F3849) },
6347 { Bad_Opcode },
6348 { X86_64_TABLE (X86_64_VEX_0F384B) },
6349 { Bad_Opcode },
6350 { Bad_Opcode },
6351 { Bad_Opcode },
6352 { Bad_Opcode },
6353 /* 50 */
6354 { VEX_W_TABLE (VEX_W_0F3850) },
6355 { VEX_W_TABLE (VEX_W_0F3851) },
6356 { VEX_W_TABLE (VEX_W_0F3852) },
6357 { VEX_W_TABLE (VEX_W_0F3853) },
6358 { Bad_Opcode },
6359 { Bad_Opcode },
6360 { Bad_Opcode },
6361 { Bad_Opcode },
6362 /* 58 */
6363 { VEX_W_TABLE (VEX_W_0F3858) },
6364 { VEX_W_TABLE (VEX_W_0F3859) },
6365 { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6366 { Bad_Opcode },
6367 { X86_64_TABLE (X86_64_VEX_0F385C) },
6368 { Bad_Opcode },
6369 { X86_64_TABLE (X86_64_VEX_0F385E) },
6370 { Bad_Opcode },
6371 /* 60 */
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { Bad_Opcode },
6377 { Bad_Opcode },
6378 { Bad_Opcode },
6379 { Bad_Opcode },
6380 /* 68 */
6381 { Bad_Opcode },
6382 { Bad_Opcode },
6383 { Bad_Opcode },
6384 { Bad_Opcode },
6385 { X86_64_TABLE (X86_64_VEX_0F386C) },
6386 { Bad_Opcode },
6387 { Bad_Opcode },
6388 { Bad_Opcode },
6389 /* 70 */
6390 { Bad_Opcode },
6391 { Bad_Opcode },
6392 { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6393 { Bad_Opcode },
6394 { Bad_Opcode },
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { Bad_Opcode },
6398 /* 78 */
6399 { VEX_W_TABLE (VEX_W_0F3878) },
6400 { VEX_W_TABLE (VEX_W_0F3879) },
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 { Bad_Opcode },
6405 { Bad_Opcode },
6406 { Bad_Opcode },
6407 /* 80 */
6408 { Bad_Opcode },
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 /* 88 */
6417 { Bad_Opcode },
6418 { Bad_Opcode },
6419 { Bad_Opcode },
6420 { Bad_Opcode },
6421 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
6422 { Bad_Opcode },
6423 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
6424 { Bad_Opcode },
6425 /* 90 */
6426 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6427 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6428 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6429 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6433 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6434 /* 98 */
6435 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6436 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6437 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6438 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6439 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6440 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6441 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6442 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6443 /* a0 */
6444 { Bad_Opcode },
6445 { Bad_Opcode },
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6451 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6452 /* a8 */
6453 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6454 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6455 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6456 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6457 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6458 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6459 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6460 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6461 /* b0 */
6462 { VEX_W_TABLE (VEX_W_0F38B0) },
6463 { VEX_W_TABLE (VEX_W_0F38B1) },
6464 { Bad_Opcode },
6465 { Bad_Opcode },
6466 { VEX_W_TABLE (VEX_W_0F38B4) },
6467 { VEX_W_TABLE (VEX_W_0F38B5) },
6468 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6469 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6470 /* b8 */
6471 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6472 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6473 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6474 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6475 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6476 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6477 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6478 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6479 /* c0 */
6480 { Bad_Opcode },
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 /* c8 */
6489 { Bad_Opcode },
6490 { Bad_Opcode },
6491 { Bad_Opcode },
6492 { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6493 { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6494 { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6495 { Bad_Opcode },
6496 { VEX_W_TABLE (VEX_W_0F38CF) },
6497 /* d0 */
6498 { Bad_Opcode },
6499 { Bad_Opcode },
6500 { VEX_W_TABLE (VEX_W_0F38D2) },
6501 { VEX_W_TABLE (VEX_W_0F38D3) },
6502 { Bad_Opcode },
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 /* d8 */
6507 { Bad_Opcode },
6508 { Bad_Opcode },
6509 { VEX_W_TABLE (VEX_W_0F38DA) },
6510 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6511 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6512 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6513 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6514 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6515 /* e0 */
6516 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6517 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6518 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6519 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6520 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6521 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6522 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6523 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6524 /* e8 */
6525 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6526 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6527 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6528 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6529 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6530 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6531 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6532 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6533 /* f0 */
6534 { Bad_Opcode },
6535 { Bad_Opcode },
6536 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6537 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6538 { Bad_Opcode },
6539 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6540 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6541 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6542 /* f8 */
6543 { Bad_Opcode },
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 },
6552 /* VEX_0F3A */
6553 {
6554 /* 00 */
6555 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6556 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6557 { VEX_W_TABLE (VEX_W_0F3A02) },
6558 { Bad_Opcode },
6559 { VEX_W_TABLE (VEX_W_0F3A04) },
6560 { VEX_W_TABLE (VEX_W_0F3A05) },
6561 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6562 { Bad_Opcode },
6563 /* 08 */
6564 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6565 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6566 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6567 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6568 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6569 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6570 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6571 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6572 /* 10 */
6573 { Bad_Opcode },
6574 { Bad_Opcode },
6575 { Bad_Opcode },
6576 { Bad_Opcode },
6577 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6578 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6579 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6580 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6581 /* 18 */
6582 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6583 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6584 { Bad_Opcode },
6585 { Bad_Opcode },
6586 { Bad_Opcode },
6587 { VEX_W_TABLE (VEX_W_0F3A1D) },
6588 { Bad_Opcode },
6589 { Bad_Opcode },
6590 /* 20 */
6591 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6592 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6593 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { Bad_Opcode },
6597 { Bad_Opcode },
6598 { Bad_Opcode },
6599 /* 28 */
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 { Bad_Opcode },
6606 { Bad_Opcode },
6607 { Bad_Opcode },
6608 /* 30 */
6609 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6610 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6611 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6612 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6613 { Bad_Opcode },
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 { Bad_Opcode },
6617 /* 38 */
6618 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6619 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6620 { Bad_Opcode },
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 { Bad_Opcode },
6624 { Bad_Opcode },
6625 { Bad_Opcode },
6626 /* 40 */
6627 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6628 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6629 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6630 { Bad_Opcode },
6631 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6632 { Bad_Opcode },
6633 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6634 { Bad_Opcode },
6635 /* 48 */
6636 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6637 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6638 { VEX_W_TABLE (VEX_W_0F3A4A) },
6639 { VEX_W_TABLE (VEX_W_0F3A4B) },
6640 { VEX_W_TABLE (VEX_W_0F3A4C) },
6641 { Bad_Opcode },
6642 { Bad_Opcode },
6643 { Bad_Opcode },
6644 /* 50 */
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 { Bad_Opcode },
6652 { Bad_Opcode },
6653 /* 58 */
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6659 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6660 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6661 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6662 /* 60 */
6663 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6664 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6666 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6667 { Bad_Opcode },
6668 { Bad_Opcode },
6669 { Bad_Opcode },
6670 { Bad_Opcode },
6671 /* 68 */
6672 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6673 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6674 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6675 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6676 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6677 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6678 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6679 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6680 /* 70 */
6681 { Bad_Opcode },
6682 { Bad_Opcode },
6683 { Bad_Opcode },
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 { Bad_Opcode },
6688 { Bad_Opcode },
6689 /* 78 */
6690 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6691 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6692 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6693 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6694 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6695 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6696 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6697 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6698 /* 80 */
6699 { Bad_Opcode },
6700 { Bad_Opcode },
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 /* 88 */
6708 { Bad_Opcode },
6709 { Bad_Opcode },
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 { Bad_Opcode },
6716 /* 90 */
6717 { Bad_Opcode },
6718 { Bad_Opcode },
6719 { Bad_Opcode },
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 { Bad_Opcode },
6724 { Bad_Opcode },
6725 /* 98 */
6726 { Bad_Opcode },
6727 { Bad_Opcode },
6728 { Bad_Opcode },
6729 { Bad_Opcode },
6730 { Bad_Opcode },
6731 { Bad_Opcode },
6732 { Bad_Opcode },
6733 { Bad_Opcode },
6734 /* a0 */
6735 { Bad_Opcode },
6736 { Bad_Opcode },
6737 { Bad_Opcode },
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 /* a8 */
6744 { Bad_Opcode },
6745 { Bad_Opcode },
6746 { Bad_Opcode },
6747 { Bad_Opcode },
6748 { Bad_Opcode },
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 /* b0 */
6753 { Bad_Opcode },
6754 { Bad_Opcode },
6755 { Bad_Opcode },
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 /* b8 */
6762 { Bad_Opcode },
6763 { Bad_Opcode },
6764 { Bad_Opcode },
6765 { Bad_Opcode },
6766 { Bad_Opcode },
6767 { Bad_Opcode },
6768 { Bad_Opcode },
6769 { Bad_Opcode },
6770 /* c0 */
6771 { Bad_Opcode },
6772 { Bad_Opcode },
6773 { Bad_Opcode },
6774 { Bad_Opcode },
6775 { Bad_Opcode },
6776 { Bad_Opcode },
6777 { Bad_Opcode },
6778 { Bad_Opcode },
6779 /* c8 */
6780 { Bad_Opcode },
6781 { Bad_Opcode },
6782 { Bad_Opcode },
6783 { Bad_Opcode },
6784 { Bad_Opcode },
6785 { Bad_Opcode },
6786 { VEX_W_TABLE (VEX_W_0F3ACE) },
6787 { VEX_W_TABLE (VEX_W_0F3ACF) },
6788 /* d0 */
6789 { Bad_Opcode },
6790 { Bad_Opcode },
6791 { Bad_Opcode },
6792 { Bad_Opcode },
6793 { Bad_Opcode },
6794 { Bad_Opcode },
6795 { Bad_Opcode },
6796 { Bad_Opcode },
6797 /* d8 */
6798 { Bad_Opcode },
6799 { Bad_Opcode },
6800 { Bad_Opcode },
6801 { Bad_Opcode },
6802 { Bad_Opcode },
6803 { Bad_Opcode },
6804 { VEX_W_TABLE (VEX_W_0F3ADE) },
6805 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6806 /* e0 */
6807 { Bad_Opcode },
6808 { Bad_Opcode },
6809 { Bad_Opcode },
6810 { Bad_Opcode },
6811 { Bad_Opcode },
6812 { Bad_Opcode },
6813 { Bad_Opcode },
6814 { Bad_Opcode },
6815 /* e8 */
6816 { Bad_Opcode },
6817 { Bad_Opcode },
6818 { Bad_Opcode },
6819 { Bad_Opcode },
6820 { Bad_Opcode },
6821 { Bad_Opcode },
6822 { Bad_Opcode },
6823 { Bad_Opcode },
6824 /* f0 */
6825 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6826 { Bad_Opcode },
6827 { Bad_Opcode },
6828 { Bad_Opcode },
6829 { Bad_Opcode },
6830 { Bad_Opcode },
6831 { Bad_Opcode },
6832 { Bad_Opcode },
6833 /* f8 */
6834 { Bad_Opcode },
6835 { Bad_Opcode },
6836 { Bad_Opcode },
6837 { Bad_Opcode },
6838 { Bad_Opcode },
6839 { Bad_Opcode },
6840 { Bad_Opcode },
6841 { Bad_Opcode },
6842 },
6843 };
6844
6845 #include "i386-dis-evex.h"
6846
6847 static const struct dis386 vex_len_table[][2] = {
6848 /* VEX_LEN_0F12_P_0 */
6849 {
6850 { MOD_TABLE (MOD_0F12_PREFIX_0) },
6851 },
6852
6853 /* VEX_LEN_0F12_P_2 */
6854 {
6855 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
6856 },
6857
6858 /* VEX_LEN_0F13 */
6859 {
6860 { "%XEVmovlpYX", { Mq, XM }, PREFIX_OPCODE },
6861 },
6862
6863 /* VEX_LEN_0F16_P_0 */
6864 {
6865 { MOD_TABLE (MOD_0F16_PREFIX_0) },
6866 },
6867
6868 /* VEX_LEN_0F16_P_2 */
6869 {
6870 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
6871 },
6872
6873 /* VEX_LEN_0F17 */
6874 {
6875 { "%XEVmovhpYX", { Mq, XM }, PREFIX_OPCODE },
6876 },
6877
6878 /* VEX_LEN_0F41 */
6879 {
6880 { Bad_Opcode },
6881 { VEX_W_TABLE (VEX_W_0F41_L_1) },
6882 },
6883
6884 /* VEX_LEN_0F42 */
6885 {
6886 { Bad_Opcode },
6887 { VEX_W_TABLE (VEX_W_0F42_L_1) },
6888 },
6889
6890 /* VEX_LEN_0F44 */
6891 {
6892 { VEX_W_TABLE (VEX_W_0F44_L_0) },
6893 },
6894
6895 /* VEX_LEN_0F45 */
6896 {
6897 { Bad_Opcode },
6898 { VEX_W_TABLE (VEX_W_0F45_L_1) },
6899 },
6900
6901 /* VEX_LEN_0F46 */
6902 {
6903 { Bad_Opcode },
6904 { VEX_W_TABLE (VEX_W_0F46_L_1) },
6905 },
6906
6907 /* VEX_LEN_0F47 */
6908 {
6909 { Bad_Opcode },
6910 { VEX_W_TABLE (VEX_W_0F47_L_1) },
6911 },
6912
6913 /* VEX_LEN_0F4A */
6914 {
6915 { Bad_Opcode },
6916 { VEX_W_TABLE (VEX_W_0F4A_L_1) },
6917 },
6918
6919 /* VEX_LEN_0F4B */
6920 {
6921 { Bad_Opcode },
6922 { VEX_W_TABLE (VEX_W_0F4B_L_1) },
6923 },
6924
6925 /* VEX_LEN_0F6E */
6926 {
6927 { "%XEvmovYK", { XMScalar, Edq }, PREFIX_DATA },
6928 },
6929
6930 /* VEX_LEN_0F77 */
6931 {
6932 { "vzeroupper", { XX }, 0 },
6933 { "vzeroall", { XX }, 0 },
6934 },
6935
6936 /* VEX_LEN_0F7E_P_1 */
6937 {
6938 { "%XEvmovqY", { XMScalar, EXq }, 0 },
6939 },
6940
6941 /* VEX_LEN_0F7E_P_2 */
6942 {
6943 { "%XEvmovK", { Edq, XMScalar }, 0 },
6944 },
6945
6946 /* VEX_LEN_0F90 */
6947 {
6948 { VEX_W_TABLE (VEX_W_0F90_L_0) },
6949 },
6950
6951 /* VEX_LEN_0F91 */
6952 {
6953 { VEX_W_TABLE (VEX_W_0F91_L_0) },
6954 },
6955
6956 /* VEX_LEN_0F92 */
6957 {
6958 { VEX_W_TABLE (VEX_W_0F92_L_0) },
6959 },
6960
6961 /* VEX_LEN_0F93 */
6962 {
6963 { VEX_W_TABLE (VEX_W_0F93_L_0) },
6964 },
6965
6966 /* VEX_LEN_0F98 */
6967 {
6968 { VEX_W_TABLE (VEX_W_0F98_L_0) },
6969 },
6970
6971 /* VEX_LEN_0F99 */
6972 {
6973 { VEX_W_TABLE (VEX_W_0F99_L_0) },
6974 },
6975
6976 /* VEX_LEN_0FAE_R_2 */
6977 {
6978 { "vldmxcsr", { Md }, 0 },
6979 },
6980
6981 /* VEX_LEN_0FAE_R_3 */
6982 {
6983 { "vstmxcsr", { Md }, 0 },
6984 },
6985
6986 /* VEX_LEN_0FC4 */
6987 {
6988 { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA },
6989 },
6990
6991 /* VEX_LEN_0FD6 */
6992 {
6993 { "%XEvmovqY", { EXqS, XMScalar }, PREFIX_DATA },
6994 },
6995
6996 /* VEX_LEN_0F3816 */
6997 {
6998 { Bad_Opcode },
6999 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7000 },
7001
7002 /* VEX_LEN_0F3819 */
7003 {
7004 { Bad_Opcode },
7005 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7006 },
7007
7008 /* VEX_LEN_0F381A */
7009 {
7010 { Bad_Opcode },
7011 { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7012 },
7013
7014 /* VEX_LEN_0F3836 */
7015 {
7016 { Bad_Opcode },
7017 { VEX_W_TABLE (VEX_W_0F3836) },
7018 },
7019
7020 /* VEX_LEN_0F3841 */
7021 {
7022 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
7023 },
7024
7025 /* VEX_LEN_0F3849_X86_64 */
7026 {
7027 { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7028 },
7029
7030 /* VEX_LEN_0F384B_X86_64 */
7031 {
7032 { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7033 },
7034
7035 /* VEX_LEN_0F385A */
7036 {
7037 { Bad_Opcode },
7038 { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7039 },
7040
7041 /* VEX_LEN_0F385C_X86_64 */
7042 {
7043 { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7044 },
7045
7046 /* VEX_LEN_0F385E_X86_64 */
7047 {
7048 { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7049 },
7050
7051 /* VEX_LEN_0F386C_X86_64 */
7052 {
7053 { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7054 },
7055
7056 /* VEX_LEN_0F38CB_P_3_W_0 */
7057 {
7058 { Bad_Opcode },
7059 { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7060 },
7061
7062 /* VEX_LEN_0F38CC_P_3_W_0 */
7063 {
7064 { Bad_Opcode },
7065 { "vsha512msg1", { XM, Rxmmq }, 0 },
7066 },
7067
7068 /* VEX_LEN_0F38CD_P_3_W_0 */
7069 {
7070 { Bad_Opcode },
7071 { "vsha512msg2", { XM, Rymm }, 0 },
7072 },
7073
7074 /* VEX_LEN_0F38DA_W_0_P_0 */
7075 {
7076 { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7077 },
7078
7079 /* VEX_LEN_0F38DA_W_0_P_2 */
7080 {
7081 { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7082 },
7083
7084 /* VEX_LEN_0F38DB */
7085 {
7086 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7087 },
7088
7089 /* VEX_LEN_0F38F2 */
7090 {
7091 { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7092 },
7093
7094 /* VEX_LEN_0F38F3 */
7095 {
7096 { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7097 },
7098
7099 /* VEX_LEN_0F38F5 */
7100 {
7101 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7102 },
7103
7104 /* VEX_LEN_0F38F6 */
7105 {
7106 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7107 },
7108
7109 /* VEX_LEN_0F38F7 */
7110 {
7111 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7112 },
7113
7114 /* VEX_LEN_0F3A00 */
7115 {
7116 { Bad_Opcode },
7117 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7118 },
7119
7120 /* VEX_LEN_0F3A01 */
7121 {
7122 { Bad_Opcode },
7123 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7124 },
7125
7126 /* VEX_LEN_0F3A06 */
7127 {
7128 { Bad_Opcode },
7129 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7130 },
7131
7132 /* VEX_LEN_0F3A14 */
7133 {
7134 { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
7135 },
7136
7137 /* VEX_LEN_0F3A15 */
7138 {
7139 { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
7140 },
7141
7142 /* VEX_LEN_0F3A16 */
7143 {
7144 { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7145 },
7146
7147 /* VEX_LEN_0F3A17 */
7148 {
7149 { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA },
7150 },
7151
7152 /* VEX_LEN_0F3A18 */
7153 {
7154 { Bad_Opcode },
7155 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7156 },
7157
7158 /* VEX_LEN_0F3A19 */
7159 {
7160 { Bad_Opcode },
7161 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7162 },
7163
7164 /* VEX_LEN_0F3A20 */
7165 {
7166 { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7167 },
7168
7169 /* VEX_LEN_0F3A21 */
7170 {
7171 { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7172 },
7173
7174 /* VEX_LEN_0F3A22 */
7175 {
7176 { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7177 },
7178
7179 /* VEX_LEN_0F3A30 */
7180 {
7181 { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7182 },
7183
7184 /* VEX_LEN_0F3A31 */
7185 {
7186 { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7187 },
7188
7189 /* VEX_LEN_0F3A32 */
7190 {
7191 { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7192 },
7193
7194 /* VEX_LEN_0F3A33 */
7195 {
7196 { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7197 },
7198
7199 /* VEX_LEN_0F3A38 */
7200 {
7201 { Bad_Opcode },
7202 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7203 },
7204
7205 /* VEX_LEN_0F3A39 */
7206 {
7207 { Bad_Opcode },
7208 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7209 },
7210
7211 /* VEX_LEN_0F3A41 */
7212 {
7213 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7214 },
7215
7216 /* VEX_LEN_0F3A46 */
7217 {
7218 { Bad_Opcode },
7219 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7220 },
7221
7222 /* VEX_LEN_0F3A60 */
7223 {
7224 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7225 },
7226
7227 /* VEX_LEN_0F3A61 */
7228 {
7229 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7230 },
7231
7232 /* VEX_LEN_0F3A62 */
7233 {
7234 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7235 },
7236
7237 /* VEX_LEN_0F3A63 */
7238 {
7239 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7240 },
7241
7242 /* VEX_LEN_0F3ADE_W_0 */
7243 {
7244 { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7245 },
7246
7247 /* VEX_LEN_0F3ADF */
7248 {
7249 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7250 },
7251
7252 /* VEX_LEN_0F3AF0 */
7253 {
7254 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7255 },
7256
7257 /* VEX_LEN_MAP7_F8 */
7258 {
7259 { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7260 },
7261
7262 /* VEX_LEN_XOP_08_85 */
7263 {
7264 { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7265 },
7266
7267 /* VEX_LEN_XOP_08_86 */
7268 {
7269 { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7270 },
7271
7272 /* VEX_LEN_XOP_08_87 */
7273 {
7274 { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7275 },
7276
7277 /* VEX_LEN_XOP_08_8E */
7278 {
7279 { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7280 },
7281
7282 /* VEX_LEN_XOP_08_8F */
7283 {
7284 { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7285 },
7286
7287 /* VEX_LEN_XOP_08_95 */
7288 {
7289 { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7290 },
7291
7292 /* VEX_LEN_XOP_08_96 */
7293 {
7294 { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7295 },
7296
7297 /* VEX_LEN_XOP_08_97 */
7298 {
7299 { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7300 },
7301
7302 /* VEX_LEN_XOP_08_9E */
7303 {
7304 { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7305 },
7306
7307 /* VEX_LEN_XOP_08_9F */
7308 {
7309 { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7310 },
7311
7312 /* VEX_LEN_XOP_08_A3 */
7313 {
7314 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7315 },
7316
7317 /* VEX_LEN_XOP_08_A6 */
7318 {
7319 { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7320 },
7321
7322 /* VEX_LEN_XOP_08_B6 */
7323 {
7324 { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7325 },
7326
7327 /* VEX_LEN_XOP_08_C0 */
7328 {
7329 { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7330 },
7331
7332 /* VEX_LEN_XOP_08_C1 */
7333 {
7334 { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7335 },
7336
7337 /* VEX_LEN_XOP_08_C2 */
7338 {
7339 { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7340 },
7341
7342 /* VEX_LEN_XOP_08_C3 */
7343 {
7344 { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7345 },
7346
7347 /* VEX_LEN_XOP_08_CC */
7348 {
7349 { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7350 },
7351
7352 /* VEX_LEN_XOP_08_CD */
7353 {
7354 { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7355 },
7356
7357 /* VEX_LEN_XOP_08_CE */
7358 {
7359 { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7360 },
7361
7362 /* VEX_LEN_XOP_08_CF */
7363 {
7364 { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7365 },
7366
7367 /* VEX_LEN_XOP_08_EC */
7368 {
7369 { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7370 },
7371
7372 /* VEX_LEN_XOP_08_ED */
7373 {
7374 { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7375 },
7376
7377 /* VEX_LEN_XOP_08_EE */
7378 {
7379 { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7380 },
7381
7382 /* VEX_LEN_XOP_08_EF */
7383 {
7384 { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7385 },
7386
7387 /* VEX_LEN_XOP_09_01 */
7388 {
7389 { REG_TABLE (REG_XOP_09_01_L_0) },
7390 },
7391
7392 /* VEX_LEN_XOP_09_02 */
7393 {
7394 { REG_TABLE (REG_XOP_09_02_L_0) },
7395 },
7396
7397 /* VEX_LEN_XOP_09_12 */
7398 {
7399 { REG_TABLE (REG_XOP_09_12_L_0) },
7400 },
7401
7402 /* VEX_LEN_XOP_09_82_W_0 */
7403 {
7404 { "vfrczss", { XM, EXd }, 0 },
7405 },
7406
7407 /* VEX_LEN_XOP_09_83_W_0 */
7408 {
7409 { "vfrczsd", { XM, EXq }, 0 },
7410 },
7411
7412 /* VEX_LEN_XOP_09_90 */
7413 {
7414 { "vprotb", { XM, EXx, VexW }, 0 },
7415 },
7416
7417 /* VEX_LEN_XOP_09_91 */
7418 {
7419 { "vprotw", { XM, EXx, VexW }, 0 },
7420 },
7421
7422 /* VEX_LEN_XOP_09_92 */
7423 {
7424 { "vprotd", { XM, EXx, VexW }, 0 },
7425 },
7426
7427 /* VEX_LEN_XOP_09_93 */
7428 {
7429 { "vprotq", { XM, EXx, VexW }, 0 },
7430 },
7431
7432 /* VEX_LEN_XOP_09_94 */
7433 {
7434 { "vpshlb", { XM, EXx, VexW }, 0 },
7435 },
7436
7437 /* VEX_LEN_XOP_09_95 */
7438 {
7439 { "vpshlw", { XM, EXx, VexW }, 0 },
7440 },
7441
7442 /* VEX_LEN_XOP_09_96 */
7443 {
7444 { "vpshld", { XM, EXx, VexW }, 0 },
7445 },
7446
7447 /* VEX_LEN_XOP_09_97 */
7448 {
7449 { "vpshlq", { XM, EXx, VexW }, 0 },
7450 },
7451
7452 /* VEX_LEN_XOP_09_98 */
7453 {
7454 { "vpshab", { XM, EXx, VexW }, 0 },
7455 },
7456
7457 /* VEX_LEN_XOP_09_99 */
7458 {
7459 { "vpshaw", { XM, EXx, VexW }, 0 },
7460 },
7461
7462 /* VEX_LEN_XOP_09_9A */
7463 {
7464 { "vpshad", { XM, EXx, VexW }, 0 },
7465 },
7466
7467 /* VEX_LEN_XOP_09_9B */
7468 {
7469 { "vpshaq", { XM, EXx, VexW }, 0 },
7470 },
7471
7472 /* VEX_LEN_XOP_09_C1 */
7473 {
7474 { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7475 },
7476
7477 /* VEX_LEN_XOP_09_C2 */
7478 {
7479 { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7480 },
7481
7482 /* VEX_LEN_XOP_09_C3 */
7483 {
7484 { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7485 },
7486
7487 /* VEX_LEN_XOP_09_C6 */
7488 {
7489 { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7490 },
7491
7492 /* VEX_LEN_XOP_09_C7 */
7493 {
7494 { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7495 },
7496
7497 /* VEX_LEN_XOP_09_CB */
7498 {
7499 { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7500 },
7501
7502 /* VEX_LEN_XOP_09_D1 */
7503 {
7504 { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7505 },
7506
7507 /* VEX_LEN_XOP_09_D2 */
7508 {
7509 { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7510 },
7511
7512 /* VEX_LEN_XOP_09_D3 */
7513 {
7514 { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7515 },
7516
7517 /* VEX_LEN_XOP_09_D6 */
7518 {
7519 { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7520 },
7521
7522 /* VEX_LEN_XOP_09_D7 */
7523 {
7524 { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7525 },
7526
7527 /* VEX_LEN_XOP_09_DB */
7528 {
7529 { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7530 },
7531
7532 /* VEX_LEN_XOP_09_E1 */
7533 {
7534 { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7535 },
7536
7537 /* VEX_LEN_XOP_09_E2 */
7538 {
7539 { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7540 },
7541
7542 /* VEX_LEN_XOP_09_E3 */
7543 {
7544 { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7545 },
7546
7547 /* VEX_LEN_XOP_0A_12 */
7548 {
7549 { REG_TABLE (REG_XOP_0A_12_L_0) },
7550 },
7551 };
7552
7553 #include "i386-dis-evex-len.h"
7554
7555 static const struct dis386 vex_w_table[][2] = {
7556 {
7557 /* VEX_W_0F41_L_1_M_1 */
7558 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7559 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7560 },
7561 {
7562 /* VEX_W_0F42_L_1_M_1 */
7563 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7564 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7565 },
7566 {
7567 /* VEX_W_0F44_L_0_M_1 */
7568 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7569 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7570 },
7571 {
7572 /* VEX_W_0F45_L_1_M_1 */
7573 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7574 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7575 },
7576 {
7577 /* VEX_W_0F46_L_1_M_1 */
7578 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7579 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7580 },
7581 {
7582 /* VEX_W_0F47_L_1_M_1 */
7583 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7584 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7585 },
7586 {
7587 /* VEX_W_0F4A_L_1_M_1 */
7588 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7589 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7590 },
7591 {
7592 /* VEX_W_0F4B_L_1_M_1 */
7593 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7594 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7595 },
7596 {
7597 /* VEX_W_0F90_L_0 */
7598 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7599 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7600 },
7601 {
7602 /* VEX_W_0F91_L_0_M_0 */
7603 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7604 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7605 },
7606 {
7607 /* VEX_W_0F92_L_0_M_1 */
7608 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7609 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7610 },
7611 {
7612 /* VEX_W_0F93_L_0_M_1 */
7613 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7614 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7615 },
7616 {
7617 /* VEX_W_0F98_L_0_M_1 */
7618 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7619 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7620 },
7621 {
7622 /* VEX_W_0F99_L_0_M_1 */
7623 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7624 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7625 },
7626 {
7627 /* VEX_W_0F380C */
7628 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7629 },
7630 {
7631 /* VEX_W_0F380D */
7632 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7633 },
7634 {
7635 /* VEX_W_0F380E */
7636 { "vtestps", { XM, EXx }, PREFIX_DATA },
7637 },
7638 {
7639 /* VEX_W_0F380F */
7640 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7641 },
7642 {
7643 /* VEX_W_0F3813 */
7644 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7645 },
7646 {
7647 /* VEX_W_0F3816_L_1 */
7648 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7649 },
7650 {
7651 /* VEX_W_0F3818 */
7652 { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA },
7653 },
7654 {
7655 /* VEX_W_0F3819_L_1 */
7656 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7657 },
7658 {
7659 /* VEX_W_0F381A_L_1 */
7660 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7661 },
7662 {
7663 /* VEX_W_0F382C */
7664 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7665 },
7666 {
7667 /* VEX_W_0F382D */
7668 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7669 },
7670 {
7671 /* VEX_W_0F382E */
7672 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7673 },
7674 {
7675 /* VEX_W_0F382F */
7676 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7677 },
7678 {
7679 /* VEX_W_0F3836 */
7680 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7681 },
7682 {
7683 /* VEX_W_0F3846 */
7684 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7685 },
7686 {
7687 /* VEX_W_0F3849_X86_64_L_0 */
7688 { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7689 },
7690 {
7691 /* VEX_W_0F384B_X86_64_L_0 */
7692 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
7693 },
7694 {
7695 /* VEX_W_0F3850 */
7696 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7697 },
7698 {
7699 /* VEX_W_0F3851 */
7700 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7701 },
7702 {
7703 /* VEX_W_0F3852 */
7704 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA },
7705 },
7706 {
7707 /* VEX_W_0F3853 */
7708 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
7709 },
7710 {
7711 /* VEX_W_0F3858 */
7712 { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7713 },
7714 {
7715 /* VEX_W_0F3859 */
7716 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7717 },
7718 {
7719 /* VEX_W_0F385A_L_0 */
7720 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7721 },
7722 {
7723 /* VEX_W_0F385C_X86_64_L_0 */
7724 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
7725 },
7726 {
7727 /* VEX_W_0F385E_X86_64_L_0 */
7728 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
7729 },
7730 {
7731 /* VEX_W_0F386C_X86_64_L_0 */
7732 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
7733 },
7734 {
7735 /* VEX_W_0F3872_P_1 */
7736 { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7737 },
7738 {
7739 /* VEX_W_0F3878 */
7740 { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA },
7741 },
7742 {
7743 /* VEX_W_0F3879 */
7744 { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA },
7745 },
7746 {
7747 /* VEX_W_0F38B0 */
7748 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7749 },
7750 {
7751 /* VEX_W_0F38B1 */
7752 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7753 },
7754 {
7755 /* VEX_W_0F38B4 */
7756 { Bad_Opcode },
7757 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7758 },
7759 {
7760 /* VEX_W_0F38B5 */
7761 { Bad_Opcode },
7762 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7763 },
7764 {
7765 /* VEX_W_0F38CB_P_3 */
7766 { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
7767 },
7768 {
7769 /* VEX_W_0F38CC_P_3 */
7770 { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
7771 },
7772 {
7773 /* VEX_W_0F38CD_P_3 */
7774 { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
7775 },
7776 {
7777 /* VEX_W_0F38CF */
7778 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7779 },
7780 {
7781 /* VEX_W_0F38D2 */
7782 { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
7783 },
7784 {
7785 /* VEX_W_0F38D3 */
7786 { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
7787 },
7788 {
7789 /* VEX_W_0F38DA */
7790 { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
7791 },
7792 {
7793 /* VEX_W_0F3A00_L_1 */
7794 { Bad_Opcode },
7795 { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA },
7796 },
7797 {
7798 /* VEX_W_0F3A01_L_1 */
7799 { Bad_Opcode },
7800 { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7801 },
7802 {
7803 /* VEX_W_0F3A02 */
7804 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7805 },
7806 {
7807 /* VEX_W_0F3A04 */
7808 { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7809 },
7810 {
7811 /* VEX_W_0F3A05 */
7812 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7813 },
7814 {
7815 /* VEX_W_0F3A06_L_1 */
7816 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7817 },
7818 {
7819 /* VEX_W_0F3A18_L_1 */
7820 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7821 },
7822 {
7823 /* VEX_W_0F3A19_L_1 */
7824 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7825 },
7826 {
7827 /* VEX_W_0F3A1D */
7828 { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7829 },
7830 {
7831 /* VEX_W_0F3A38_L_1 */
7832 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7833 },
7834 {
7835 /* VEX_W_0F3A39_L_1 */
7836 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7837 },
7838 {
7839 /* VEX_W_0F3A46_L_1 */
7840 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7841 },
7842 {
7843 /* VEX_W_0F3A4A */
7844 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7845 },
7846 {
7847 /* VEX_W_0F3A4B */
7848 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7849 },
7850 {
7851 /* VEX_W_0F3A4C */
7852 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7853 },
7854 {
7855 /* VEX_W_0F3ACE */
7856 { Bad_Opcode },
7857 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7858 },
7859 {
7860 /* VEX_W_0F3ACF */
7861 { Bad_Opcode },
7862 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7863 },
7864 {
7865 /* VEX_W_0F3ADE */
7866 { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
7867 },
7868 {
7869 /* VEX_W_MAP7_F8_L_0 */
7870 { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
7871 },
7872 /* VEX_W_XOP_08_85_L_0 */
7873 {
7874 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7875 },
7876 /* VEX_W_XOP_08_86_L_0 */
7877 {
7878 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7879 },
7880 /* VEX_W_XOP_08_87_L_0 */
7881 {
7882 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7883 },
7884 /* VEX_W_XOP_08_8E_L_0 */
7885 {
7886 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7887 },
7888 /* VEX_W_XOP_08_8F_L_0 */
7889 {
7890 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7891 },
7892 /* VEX_W_XOP_08_95_L_0 */
7893 {
7894 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7895 },
7896 /* VEX_W_XOP_08_96_L_0 */
7897 {
7898 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7899 },
7900 /* VEX_W_XOP_08_97_L_0 */
7901 {
7902 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7903 },
7904 /* VEX_W_XOP_08_9E_L_0 */
7905 {
7906 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7907 },
7908 /* VEX_W_XOP_08_9F_L_0 */
7909 {
7910 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7911 },
7912 /* VEX_W_XOP_08_A6_L_0 */
7913 {
7914 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7915 },
7916 /* VEX_W_XOP_08_B6_L_0 */
7917 {
7918 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7919 },
7920 /* VEX_W_XOP_08_C0_L_0 */
7921 {
7922 { "vprotb", { XM, EXx, Ib }, 0 },
7923 },
7924 /* VEX_W_XOP_08_C1_L_0 */
7925 {
7926 { "vprotw", { XM, EXx, Ib }, 0 },
7927 },
7928 /* VEX_W_XOP_08_C2_L_0 */
7929 {
7930 { "vprotd", { XM, EXx, Ib }, 0 },
7931 },
7932 /* VEX_W_XOP_08_C3_L_0 */
7933 {
7934 { "vprotq", { XM, EXx, Ib }, 0 },
7935 },
7936 /* VEX_W_XOP_08_CC_L_0 */
7937 {
7938 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7939 },
7940 /* VEX_W_XOP_08_CD_L_0 */
7941 {
7942 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7943 },
7944 /* VEX_W_XOP_08_CE_L_0 */
7945 {
7946 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7947 },
7948 /* VEX_W_XOP_08_CF_L_0 */
7949 {
7950 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7951 },
7952 /* VEX_W_XOP_08_EC_L_0 */
7953 {
7954 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7955 },
7956 /* VEX_W_XOP_08_ED_L_0 */
7957 {
7958 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7959 },
7960 /* VEX_W_XOP_08_EE_L_0 */
7961 {
7962 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7963 },
7964 /* VEX_W_XOP_08_EF_L_0 */
7965 {
7966 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7967 },
7968 /* VEX_W_XOP_09_80 */
7969 {
7970 { "vfrczps", { XM, EXx }, 0 },
7971 },
7972 /* VEX_W_XOP_09_81 */
7973 {
7974 { "vfrczpd", { XM, EXx }, 0 },
7975 },
7976 /* VEX_W_XOP_09_82 */
7977 {
7978 { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
7979 },
7980 /* VEX_W_XOP_09_83 */
7981 {
7982 { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
7983 },
7984 /* VEX_W_XOP_09_C1_L_0 */
7985 {
7986 { "vphaddbw", { XM, EXxmm }, 0 },
7987 },
7988 /* VEX_W_XOP_09_C2_L_0 */
7989 {
7990 { "vphaddbd", { XM, EXxmm }, 0 },
7991 },
7992 /* VEX_W_XOP_09_C3_L_0 */
7993 {
7994 { "vphaddbq", { XM, EXxmm }, 0 },
7995 },
7996 /* VEX_W_XOP_09_C6_L_0 */
7997 {
7998 { "vphaddwd", { XM, EXxmm }, 0 },
7999 },
8000 /* VEX_W_XOP_09_C7_L_0 */
8001 {
8002 { "vphaddwq", { XM, EXxmm }, 0 },
8003 },
8004 /* VEX_W_XOP_09_CB_L_0 */
8005 {
8006 { "vphadddq", { XM, EXxmm }, 0 },
8007 },
8008 /* VEX_W_XOP_09_D1_L_0 */
8009 {
8010 { "vphaddubw", { XM, EXxmm }, 0 },
8011 },
8012 /* VEX_W_XOP_09_D2_L_0 */
8013 {
8014 { "vphaddubd", { XM, EXxmm }, 0 },
8015 },
8016 /* VEX_W_XOP_09_D3_L_0 */
8017 {
8018 { "vphaddubq", { XM, EXxmm }, 0 },
8019 },
8020 /* VEX_W_XOP_09_D6_L_0 */
8021 {
8022 { "vphadduwd", { XM, EXxmm }, 0 },
8023 },
8024 /* VEX_W_XOP_09_D7_L_0 */
8025 {
8026 { "vphadduwq", { XM, EXxmm }, 0 },
8027 },
8028 /* VEX_W_XOP_09_DB_L_0 */
8029 {
8030 { "vphaddudq", { XM, EXxmm }, 0 },
8031 },
8032 /* VEX_W_XOP_09_E1_L_0 */
8033 {
8034 { "vphsubbw", { XM, EXxmm }, 0 },
8035 },
8036 /* VEX_W_XOP_09_E2_L_0 */
8037 {
8038 { "vphsubwd", { XM, EXxmm }, 0 },
8039 },
8040 /* VEX_W_XOP_09_E3_L_0 */
8041 {
8042 { "vphsubdq", { XM, EXxmm }, 0 },
8043 },
8044
8045 #include "i386-dis-evex-w.h"
8046 };
8047
8048 static const struct dis386 mod_table[][2] = {
8049 {
8050 /* MOD_62_32BIT */
8051 { "bound{S|}", { Gv, Ma }, 0 },
8052 { EVEX_TABLE () },
8053 },
8054 {
8055 /* MOD_C4_32BIT */
8056 { "lesS", { Gv, Mp }, 0 },
8057 { VEX_C4_TABLE () },
8058 },
8059 {
8060 /* MOD_C5_32BIT */
8061 { "ldsS", { Gv, Mp }, 0 },
8062 { VEX_C5_TABLE () },
8063 },
8064 {
8065 /* MOD_0F01_REG_0 */
8066 { X86_64_TABLE (X86_64_0F01_REG_0) },
8067 { RM_TABLE (RM_0F01_REG_0) },
8068 },
8069 {
8070 /* MOD_0F01_REG_1 */
8071 { X86_64_TABLE (X86_64_0F01_REG_1) },
8072 { RM_TABLE (RM_0F01_REG_1) },
8073 },
8074 {
8075 /* MOD_0F01_REG_2 */
8076 { X86_64_TABLE (X86_64_0F01_REG_2) },
8077 { RM_TABLE (RM_0F01_REG_2) },
8078 },
8079 {
8080 /* MOD_0F01_REG_3 */
8081 { X86_64_TABLE (X86_64_0F01_REG_3) },
8082 { RM_TABLE (RM_0F01_REG_3) },
8083 },
8084 {
8085 /* MOD_0F01_REG_5 */
8086 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8087 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8088 },
8089 {
8090 /* MOD_0F01_REG_7 */
8091 { "invlpg", { Mb }, 0 },
8092 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8093 },
8094 {
8095 /* MOD_0F12_PREFIX_0 */
8096 { "%XEVmovlpYX", { XM, Vex, EXq }, 0 },
8097 { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8098 },
8099 {
8100 /* MOD_0F16_PREFIX_0 */
8101 { "%XEVmovhpYX", { XM, Vex, EXq }, 0 },
8102 { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8103 },
8104 {
8105 /* MOD_0F18_REG_0 */
8106 { "prefetchnta", { Mb }, 0 },
8107 { "nopQ", { Ev }, 0 },
8108 },
8109 {
8110 /* MOD_0F18_REG_1 */
8111 { "prefetcht0", { Mb }, 0 },
8112 { "nopQ", { Ev }, 0 },
8113 },
8114 {
8115 /* MOD_0F18_REG_2 */
8116 { "prefetcht1", { Mb }, 0 },
8117 { "nopQ", { Ev }, 0 },
8118 },
8119 {
8120 /* MOD_0F18_REG_3 */
8121 { "prefetcht2", { Mb }, 0 },
8122 { "nopQ", { Ev }, 0 },
8123 },
8124 {
8125 /* MOD_0F18_REG_6 */
8126 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8127 { "nopQ", { Ev }, 0 },
8128 },
8129 {
8130 /* MOD_0F18_REG_7 */
8131 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8132 { "nopQ", { Ev }, 0 },
8133 },
8134 {
8135 /* MOD_0F1A_PREFIX_0 */
8136 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8137 { "nopQ", { Ev }, 0 },
8138 },
8139 {
8140 /* MOD_0F1B_PREFIX_0 */
8141 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8142 { "nopQ", { Ev }, 0 },
8143 },
8144 {
8145 /* MOD_0F1B_PREFIX_1 */
8146 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8147 { "nopQ", { Ev }, PREFIX_IGNORED },
8148 },
8149 {
8150 /* MOD_0F1C_PREFIX_0 */
8151 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8152 { "nopQ", { Ev }, 0 },
8153 },
8154 {
8155 /* MOD_0F1E_PREFIX_1 */
8156 { "nopQ", { Ev }, PREFIX_IGNORED },
8157 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8158 },
8159 {
8160 /* MOD_0FAE_REG_0 */
8161 { "fxsave", { FXSAVE }, 0 },
8162 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8163 },
8164 {
8165 /* MOD_0FAE_REG_1 */
8166 { "fxrstor", { FXSAVE }, 0 },
8167 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8168 },
8169 {
8170 /* MOD_0FAE_REG_2 */
8171 { "ldmxcsr", { Md }, 0 },
8172 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8173 },
8174 {
8175 /* MOD_0FAE_REG_3 */
8176 { "stmxcsr", { Md }, 0 },
8177 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8178 },
8179 {
8180 /* MOD_0FAE_REG_4 */
8181 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8182 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8183 },
8184 {
8185 /* MOD_0FAE_REG_5 */
8186 { "xrstor", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8187 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8188 },
8189 {
8190 /* MOD_0FAE_REG_6 */
8191 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8192 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8193 },
8194 {
8195 /* MOD_0FAE_REG_7 */
8196 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8197 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8198 },
8199 {
8200 /* MOD_0FC7_REG_6 */
8201 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8202 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8203 },
8204 {
8205 /* MOD_0FC7_REG_7 */
8206 { "vmptrst", { Mq }, 0 },
8207 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8208 },
8209 {
8210 /* MOD_0F38DC_PREFIX_1 */
8211 { "aesenc128kl", { XM, M }, 0 },
8212 { "loadiwkey", { XM, EXx }, 0 },
8213 },
8214 /* MOD_0F38F8 */
8215 {
8216 { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8217 { X86_64_TABLE (X86_64_0F38F8_M_1) },
8218 },
8219 {
8220 /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8221 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8222 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8223 },
8224
8225 #include "i386-dis-evex-mod.h"
8226 };
8227
8228 static const struct dis386 rm_table[][8] = {
8229 {
8230 /* RM_C6_REG_7 */
8231 { "xabort", { Skip_MODRM, Ib }, 0 },
8232 },
8233 {
8234 /* RM_C7_REG_7 */
8235 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8236 },
8237 {
8238 /* RM_0F01_REG_0 */
8239 { "enclv", { Skip_MODRM }, 0 },
8240 { "vmcall", { Skip_MODRM }, 0 },
8241 { "vmlaunch", { Skip_MODRM }, 0 },
8242 { "vmresume", { Skip_MODRM }, 0 },
8243 { "vmxoff", { Skip_MODRM }, 0 },
8244 { "pconfig", { Skip_MODRM }, 0 },
8245 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8246 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8247 },
8248 {
8249 /* RM_0F01_REG_1 */
8250 { "monitor", { { OP_Monitor, 0 } }, 0 },
8251 { "mwait", { { OP_Mwait, 0 } }, 0 },
8252 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8253 { "stac", { Skip_MODRM }, 0 },
8254 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8255 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8256 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8257 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8258 },
8259 {
8260 /* RM_0F01_REG_2 */
8261 { "xgetbv", { Skip_MODRM }, 0 },
8262 { "xsetbv", { Skip_MODRM }, 0 },
8263 { Bad_Opcode },
8264 { Bad_Opcode },
8265 { "vmfunc", { Skip_MODRM }, 0 },
8266 { "xend", { Skip_MODRM }, 0 },
8267 { "xtest", { Skip_MODRM }, 0 },
8268 { "enclu", { Skip_MODRM }, 0 },
8269 },
8270 {
8271 /* RM_0F01_REG_3 */
8272 { "vmrun", { Skip_MODRM }, 0 },
8273 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8274 { "vmload", { Skip_MODRM }, 0 },
8275 { "vmsave", { Skip_MODRM }, 0 },
8276 { "stgi", { Skip_MODRM }, 0 },
8277 { "clgi", { Skip_MODRM }, 0 },
8278 { "skinit", { Skip_MODRM }, 0 },
8279 { "invlpga", { Skip_MODRM }, 0 },
8280 },
8281 {
8282 /* RM_0F01_REG_5_MOD_3 */
8283 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8284 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8285 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8286 { Bad_Opcode },
8287 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8288 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8289 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8290 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8291 },
8292 {
8293 /* RM_0F01_REG_7_MOD_3 */
8294 { "swapgs", { Skip_MODRM }, 0 },
8295 { "rdtscp", { Skip_MODRM }, 0 },
8296 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8297 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8298 { "clzero", { Skip_MODRM }, 0 },
8299 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8300 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8301 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8302 },
8303 {
8304 /* RM_0F1E_P_1_MOD_3_REG_7 */
8305 { "nopQ", { Ev }, PREFIX_IGNORED },
8306 { "nopQ", { Ev }, PREFIX_IGNORED },
8307 { "endbr64", { Skip_MODRM }, 0 },
8308 { "endbr32", { Skip_MODRM }, 0 },
8309 { "nopQ", { Ev }, PREFIX_IGNORED },
8310 { "nopQ", { Ev }, PREFIX_IGNORED },
8311 { "nopQ", { Ev }, PREFIX_IGNORED },
8312 { "nopQ", { Ev }, PREFIX_IGNORED },
8313 },
8314 {
8315 /* RM_0FAE_REG_6_MOD_3 */
8316 { "mfence", { Skip_MODRM }, 0 },
8317 },
8318 {
8319 /* RM_0FAE_REG_7_MOD_3 */
8320 { "sfence", { Skip_MODRM }, 0 },
8321 },
8322 {
8323 /* RM_0F3A0F_P_1_R_0 */
8324 { "hreset", { Skip_MODRM, Ib }, 0 },
8325 },
8326 {
8327 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8328 { "tilerelease", { Skip_MODRM }, 0 },
8329 },
8330 {
8331 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8332 { "tilezero", { TMM, Skip_MODRM }, 0 },
8333 },
8334 };
8335
8336 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8337
8338 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8339 in conflict with actual prefix opcodes. */
8340 #define REP_PREFIX 0x01
8341 #define XACQUIRE_PREFIX 0x02
8342 #define XRELEASE_PREFIX 0x03
8343 #define BND_PREFIX 0x04
8344 #define NOTRACK_PREFIX 0x05
8345
8346 static enum {
8347 ckp_okay,
8348 ckp_bogus,
8349 ckp_fetch_error,
8350 }
8351 ckprefix (instr_info *ins)
8352 {
8353 int i, length;
8354 uint8_t newrex;
8355
8356 i = 0;
8357 length = 0;
8358 /* The maximum instruction length is 15bytes. */
8359 while (length < MAX_CODE_LENGTH - 1)
8360 {
8361 if (!fetch_code (ins->info, ins->codep + 1))
8362 return ckp_fetch_error;
8363 newrex = 0;
8364 switch (*ins->codep)
8365 {
8366 /* REX prefixes family. */
8367 case 0x40:
8368 case 0x41:
8369 case 0x42:
8370 case 0x43:
8371 case 0x44:
8372 case 0x45:
8373 case 0x46:
8374 case 0x47:
8375 case 0x48:
8376 case 0x49:
8377 case 0x4a:
8378 case 0x4b:
8379 case 0x4c:
8380 case 0x4d:
8381 case 0x4e:
8382 case 0x4f:
8383 if (ins->address_mode == mode_64bit)
8384 newrex = *ins->codep;
8385 else
8386 return ckp_okay;
8387 ins->last_rex_prefix = i;
8388 break;
8389 /* REX2 must be the last prefix. */
8390 case REX2_OPCODE:
8391 if (ins->address_mode == mode_64bit)
8392 {
8393 if (ins->last_rex_prefix >= 0)
8394 return ckp_bogus;
8395
8396 ins->codep++;
8397 if (!fetch_code (ins->info, ins->codep + 1))
8398 return ckp_fetch_error;
8399 ins->rex2_payload = *ins->codep;
8400 ins->rex2 = ins->rex2_payload >> 4;
8401 ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8402 ins->codep++;
8403 ins->last_rex2_prefix = i;
8404 ins->all_prefixes[i] = REX2_OPCODE;
8405 }
8406 return ckp_okay;
8407 case 0xf3:
8408 ins->prefixes |= PREFIX_REPZ;
8409 ins->last_repz_prefix = i;
8410 break;
8411 case 0xf2:
8412 ins->prefixes |= PREFIX_REPNZ;
8413 ins->last_repnz_prefix = i;
8414 break;
8415 case 0xf0:
8416 ins->prefixes |= PREFIX_LOCK;
8417 ins->last_lock_prefix = i;
8418 break;
8419 case 0x2e:
8420 ins->prefixes |= PREFIX_CS;
8421 ins->last_seg_prefix = i;
8422 if (ins->address_mode != mode_64bit)
8423 ins->active_seg_prefix = PREFIX_CS;
8424 break;
8425 case 0x36:
8426 ins->prefixes |= PREFIX_SS;
8427 ins->last_seg_prefix = i;
8428 if (ins->address_mode != mode_64bit)
8429 ins->active_seg_prefix = PREFIX_SS;
8430 break;
8431 case 0x3e:
8432 ins->prefixes |= PREFIX_DS;
8433 ins->last_seg_prefix = i;
8434 if (ins->address_mode != mode_64bit)
8435 ins->active_seg_prefix = PREFIX_DS;
8436 break;
8437 case 0x26:
8438 ins->prefixes |= PREFIX_ES;
8439 ins->last_seg_prefix = i;
8440 if (ins->address_mode != mode_64bit)
8441 ins->active_seg_prefix = PREFIX_ES;
8442 break;
8443 case 0x64:
8444 ins->prefixes |= PREFIX_FS;
8445 ins->last_seg_prefix = i;
8446 ins->active_seg_prefix = PREFIX_FS;
8447 break;
8448 case 0x65:
8449 ins->prefixes |= PREFIX_GS;
8450 ins->last_seg_prefix = i;
8451 ins->active_seg_prefix = PREFIX_GS;
8452 break;
8453 case 0x66:
8454 ins->prefixes |= PREFIX_DATA;
8455 ins->last_data_prefix = i;
8456 break;
8457 case 0x67:
8458 ins->prefixes |= PREFIX_ADDR;
8459 ins->last_addr_prefix = i;
8460 break;
8461 case FWAIT_OPCODE:
8462 /* fwait is really an instruction. If there are prefixes
8463 before the fwait, they belong to the fwait, *not* to the
8464 following instruction. */
8465 ins->fwait_prefix = i;
8466 if (ins->prefixes || ins->rex)
8467 {
8468 ins->prefixes |= PREFIX_FWAIT;
8469 ins->codep++;
8470 /* This ensures that the previous REX prefixes are noticed
8471 as unused prefixes, as in the return case below. */
8472 return ins->rex ? ckp_bogus : ckp_okay;
8473 }
8474 ins->prefixes = PREFIX_FWAIT;
8475 break;
8476 default:
8477 return ckp_okay;
8478 }
8479 /* Rex is ignored when followed by another prefix. */
8480 if (ins->rex)
8481 return ckp_bogus;
8482 if (*ins->codep != FWAIT_OPCODE)
8483 ins->all_prefixes[i++] = *ins->codep;
8484 ins->rex = newrex;
8485 ins->codep++;
8486 length++;
8487 }
8488 return ckp_bogus;
8489 }
8490
8491 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8492 prefix byte. */
8493
8494 static const char *
8495 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8496 {
8497 static const char *rexes [16] =
8498 {
8499 "rex", /* 0x40 */
8500 "rex.B", /* 0x41 */
8501 "rex.X", /* 0x42 */
8502 "rex.XB", /* 0x43 */
8503 "rex.R", /* 0x44 */
8504 "rex.RB", /* 0x45 */
8505 "rex.RX", /* 0x46 */
8506 "rex.RXB", /* 0x47 */
8507 "rex.W", /* 0x48 */
8508 "rex.WB", /* 0x49 */
8509 "rex.WX", /* 0x4a */
8510 "rex.WXB", /* 0x4b */
8511 "rex.WR", /* 0x4c */
8512 "rex.WRB", /* 0x4d */
8513 "rex.WRX", /* 0x4e */
8514 "rex.WRXB", /* 0x4f */
8515 };
8516
8517 switch (pref)
8518 {
8519 /* REX prefixes family. */
8520 case 0x40:
8521 case 0x41:
8522 case 0x42:
8523 case 0x43:
8524 case 0x44:
8525 case 0x45:
8526 case 0x46:
8527 case 0x47:
8528 case 0x48:
8529 case 0x49:
8530 case 0x4a:
8531 case 0x4b:
8532 case 0x4c:
8533 case 0x4d:
8534 case 0x4e:
8535 case 0x4f:
8536 return rexes [pref - 0x40];
8537 case 0xf3:
8538 return "repz";
8539 case 0xf2:
8540 return "repnz";
8541 case 0xf0:
8542 return "lock";
8543 case 0x2e:
8544 return "cs";
8545 case 0x36:
8546 return "ss";
8547 case 0x3e:
8548 return "ds";
8549 case 0x26:
8550 return "es";
8551 case 0x64:
8552 return "fs";
8553 case 0x65:
8554 return "gs";
8555 case 0x66:
8556 return (sizeflag & DFLAG) ? "data16" : "data32";
8557 case 0x67:
8558 if (mode == mode_64bit)
8559 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8560 else
8561 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8562 case FWAIT_OPCODE:
8563 return "fwait";
8564 case REP_PREFIX:
8565 return "rep";
8566 case XACQUIRE_PREFIX:
8567 return "xacquire";
8568 case XRELEASE_PREFIX:
8569 return "xrelease";
8570 case BND_PREFIX:
8571 return "bnd";
8572 case NOTRACK_PREFIX:
8573 return "notrack";
8574 case REX2_OPCODE:
8575 return "rex2";
8576 default:
8577 return NULL;
8578 }
8579 }
8580
8581 void
8582 print_i386_disassembler_options (FILE *stream)
8583 {
8584 fprintf (stream, _("\n\
8585 The following i386/x86-64 specific disassembler options are supported for use\n\
8586 with the -M switch (multiple options should be separated by commas):\n"));
8587
8588 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8589 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8590 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8591 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8592 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8593 fprintf (stream, _(" att-mnemonic (AT&T syntax only)\n"
8594 " Display instruction with AT&T mnemonic\n"));
8595 fprintf (stream, _(" intel-mnemonic (AT&T syntax only)\n"
8596 " Display instruction with Intel mnemonic\n"));
8597 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8598 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8599 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8600 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8601 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8602 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8603 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8604 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8605 }
8606
8607 /* Bad opcode. */
8608 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8609
8610 /* Fetch error indicator. */
8611 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
8612
8613 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
8614
8615 /* Get a pointer to struct dis386 with a valid name. */
8616
8617 static const struct dis386 *
8618 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8619 {
8620 int vindex, vex_table_index;
8621
8622 if (dp->name != NULL)
8623 return dp;
8624
8625 switch (dp->op[0].bytemode)
8626 {
8627 case USE_REG_TABLE:
8628 dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8629 break;
8630
8631 case USE_MOD_TABLE:
8632 vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8633 dp = &mod_table[dp->op[1].bytemode][vindex];
8634 break;
8635
8636 case USE_RM_TABLE:
8637 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8638 break;
8639
8640 case USE_PREFIX_TABLE:
8641 use_prefix_table:
8642 if (ins->need_vex)
8643 {
8644 /* The prefix in VEX is implicit. */
8645 switch (ins->vex.prefix)
8646 {
8647 case 0:
8648 vindex = 0;
8649 break;
8650 case REPE_PREFIX_OPCODE:
8651 vindex = 1;
8652 break;
8653 case DATA_PREFIX_OPCODE:
8654 vindex = 2;
8655 break;
8656 case REPNE_PREFIX_OPCODE:
8657 vindex = 3;
8658 break;
8659 default:
8660 abort ();
8661 break;
8662 }
8663 }
8664 else
8665 {
8666 int last_prefix = -1;
8667 int prefix = 0;
8668 vindex = 0;
8669 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8670 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8671 last one wins. */
8672 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8673 {
8674 if (ins->last_repz_prefix > ins->last_repnz_prefix)
8675 {
8676 vindex = 1;
8677 prefix = PREFIX_REPZ;
8678 last_prefix = ins->last_repz_prefix;
8679 }
8680 else
8681 {
8682 vindex = 3;
8683 prefix = PREFIX_REPNZ;
8684 last_prefix = ins->last_repnz_prefix;
8685 }
8686
8687 /* Check if prefix should be ignored. */
8688 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8689 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8690 & prefix) != 0
8691 && !prefix_table[dp->op[1].bytemode][vindex].name)
8692 vindex = 0;
8693 }
8694
8695 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8696 {
8697 vindex = 2;
8698 prefix = PREFIX_DATA;
8699 last_prefix = ins->last_data_prefix;
8700 }
8701
8702 if (vindex != 0)
8703 {
8704 ins->used_prefixes |= prefix;
8705 ins->all_prefixes[last_prefix] = 0;
8706 }
8707 }
8708 dp = &prefix_table[dp->op[1].bytemode][vindex];
8709 break;
8710
8711 case USE_X86_64_EVEX_FROM_VEX_TABLE:
8712 case USE_X86_64_EVEX_PFX_TABLE:
8713 case USE_X86_64_EVEX_W_TABLE:
8714 case USE_X86_64_EVEX_MEM_W_TABLE:
8715 ins->evex_type = evex_from_vex;
8716 /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
8717 EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0. */
8718 if (ins->address_mode != mode_64bit
8719 || (ins->vex.mask_register_specifier & 0x3) != 0
8720 || ins->vex.ll != 0
8721 || ins->vex.zeroing != 0
8722 || ins->vex.b)
8723 return &bad_opcode;
8724
8725 if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE)
8726 goto use_prefix_table;
8727 if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE)
8728 goto use_vex_w_table;
8729 if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE)
8730 {
8731 if (ins->modrm.mod == 3)
8732 return &bad_opcode;
8733 goto use_vex_w_table;
8734 }
8735
8736 /* Fall through. */
8737 case USE_X86_64_TABLE:
8738 vindex = ins->address_mode == mode_64bit ? 1 : 0;
8739 dp = &x86_64_table[dp->op[1].bytemode][vindex];
8740 break;
8741
8742 case USE_3BYTE_TABLE:
8743 if (ins->last_rex2_prefix >= 0)
8744 return &err_opcode;
8745 if (!fetch_code (ins->info, ins->codep + 2))
8746 return &err_opcode;
8747 vindex = *ins->codep++;
8748 dp = &three_byte_table[dp->op[1].bytemode][vindex];
8749 ins->end_codep = ins->codep;
8750 if (!fetch_modrm (ins))
8751 return &err_opcode;
8752 break;
8753
8754 case USE_VEX_LEN_TABLE:
8755 if (!ins->need_vex)
8756 abort ();
8757
8758 switch (ins->vex.length)
8759 {
8760 case 128:
8761 vindex = 0;
8762 break;
8763 case 512:
8764 /* This allows re-using in particular table entries where only
8765 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
8766 if (ins->vex.evex)
8767 {
8768 case 256:
8769 vindex = 1;
8770 break;
8771 }
8772 /* Fall through. */
8773 default:
8774 abort ();
8775 break;
8776 }
8777
8778 dp = &vex_len_table[dp->op[1].bytemode][vindex];
8779 break;
8780
8781 case USE_EVEX_LEN_TABLE:
8782 if (!ins->vex.evex)
8783 abort ();
8784
8785 switch (ins->vex.length)
8786 {
8787 case 128:
8788 vindex = 0;
8789 break;
8790 case 256:
8791 vindex = 1;
8792 break;
8793 case 512:
8794 vindex = 2;
8795 break;
8796 default:
8797 abort ();
8798 break;
8799 }
8800
8801 dp = &evex_len_table[dp->op[1].bytemode][vindex];
8802 break;
8803
8804 case USE_XOP_8F_TABLE:
8805 if (!fetch_code (ins->info, ins->codep + 3))
8806 return &err_opcode;
8807 ins->rex = ~(*ins->codep >> 5) & 0x7;
8808
8809 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
8810 switch ((*ins->codep & 0x1f))
8811 {
8812 default:
8813 dp = &bad_opcode;
8814 return dp;
8815 case 0x8:
8816 vex_table_index = XOP_08;
8817 break;
8818 case 0x9:
8819 vex_table_index = XOP_09;
8820 break;
8821 case 0xa:
8822 vex_table_index = XOP_0A;
8823 break;
8824 }
8825 ins->codep++;
8826 ins->vex.w = *ins->codep & 0x80;
8827 if (ins->vex.w && ins->address_mode == mode_64bit)
8828 ins->rex |= REX_W;
8829
8830 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8831 if (ins->address_mode != mode_64bit)
8832 {
8833 /* In 16/32-bit mode REX_B is silently ignored. */
8834 ins->rex &= ~REX_B;
8835 }
8836
8837 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8838 switch ((*ins->codep & 0x3))
8839 {
8840 case 0:
8841 break;
8842 case 1:
8843 ins->vex.prefix = DATA_PREFIX_OPCODE;
8844 break;
8845 case 2:
8846 ins->vex.prefix = REPE_PREFIX_OPCODE;
8847 break;
8848 case 3:
8849 ins->vex.prefix = REPNE_PREFIX_OPCODE;
8850 break;
8851 }
8852 ins->need_vex = 3;
8853 ins->codep++;
8854 vindex = *ins->codep++;
8855 dp = &xop_table[vex_table_index][vindex];
8856
8857 ins->end_codep = ins->codep;
8858 if (!fetch_modrm (ins))
8859 return &err_opcode;
8860
8861 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
8862 having to decode the bits for every otherwise valid encoding. */
8863 if (ins->vex.prefix)
8864 return &bad_opcode;
8865 break;
8866
8867 case USE_VEX_C4_TABLE:
8868 /* VEX prefix. */
8869 if (!fetch_code (ins->info, ins->codep + 3))
8870 return &err_opcode;
8871 ins->rex = ~(*ins->codep >> 5) & 0x7;
8872 switch ((*ins->codep & 0x1f))
8873 {
8874 default:
8875 dp = &bad_opcode;
8876 return dp;
8877 case 0x1:
8878 vex_table_index = VEX_0F;
8879 break;
8880 case 0x2:
8881 vex_table_index = VEX_0F38;
8882 break;
8883 case 0x3:
8884 vex_table_index = VEX_0F3A;
8885 break;
8886 case 0x7:
8887 vex_table_index = VEX_MAP7;
8888 break;
8889 }
8890 ins->codep++;
8891 ins->vex.w = *ins->codep & 0x80;
8892 if (ins->address_mode == mode_64bit)
8893 {
8894 if (ins->vex.w)
8895 ins->rex |= REX_W;
8896 }
8897 else
8898 {
8899 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
8900 is ignored, other REX bits are 0 and the highest bit in
8901 VEX.vvvv is also ignored (but we mustn't clear it here). */
8902 ins->rex = 0;
8903 }
8904 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8905 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8906 switch ((*ins->codep & 0x3))
8907 {
8908 case 0:
8909 break;
8910 case 1:
8911 ins->vex.prefix = DATA_PREFIX_OPCODE;
8912 break;
8913 case 2:
8914 ins->vex.prefix = REPE_PREFIX_OPCODE;
8915 break;
8916 case 3:
8917 ins->vex.prefix = REPNE_PREFIX_OPCODE;
8918 break;
8919 }
8920 ins->need_vex = 3;
8921 ins->codep++;
8922 vindex = *ins->codep++;
8923 ins->condition_code = vindex & 0xf;
8924 if (vex_table_index != VEX_MAP7)
8925 dp = &vex_table[vex_table_index][vindex];
8926 else if (vindex == 0xf8)
8927 dp = &map7_f8_opcode;
8928 else
8929 dp = &bad_opcode;
8930 ins->end_codep = ins->codep;
8931 /* There is no MODRM byte for VEX0F 77. */
8932 if ((vex_table_index != VEX_0F || vindex != 0x77)
8933 && !fetch_modrm (ins))
8934 return &err_opcode;
8935 break;
8936
8937 case USE_VEX_C5_TABLE:
8938 /* VEX prefix. */
8939 if (!fetch_code (ins->info, ins->codep + 2))
8940 return &err_opcode;
8941 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
8942
8943 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
8944 VEX.vvvv is 1. */
8945 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8946 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8947 switch ((*ins->codep & 0x3))
8948 {
8949 case 0:
8950 break;
8951 case 1:
8952 ins->vex.prefix = DATA_PREFIX_OPCODE;
8953 break;
8954 case 2:
8955 ins->vex.prefix = REPE_PREFIX_OPCODE;
8956 break;
8957 case 3:
8958 ins->vex.prefix = REPNE_PREFIX_OPCODE;
8959 break;
8960 }
8961 ins->need_vex = 2;
8962 ins->codep++;
8963 vindex = *ins->codep++;
8964 dp = &vex_table[VEX_0F][vindex];
8965 ins->end_codep = ins->codep;
8966 /* There is no MODRM byte for VEX 77. */
8967 if (vindex != 0x77 && !fetch_modrm (ins))
8968 return &err_opcode;
8969 break;
8970
8971 case USE_VEX_W_TABLE:
8972 use_vex_w_table:
8973 if (!ins->need_vex)
8974 abort ();
8975
8976 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
8977 break;
8978
8979 case USE_EVEX_TABLE:
8980 ins->two_source_ops = false;
8981 /* EVEX prefix. */
8982 ins->vex.evex = true;
8983 if (!fetch_code (ins->info, ins->codep + 4))
8984 return &err_opcode;
8985 /* The first byte after 0x62. */
8986 if (*ins->codep & 0x8)
8987 ins->rex2 |= REX_B;
8988 if (!(*ins->codep & 0x10))
8989 ins->rex2 |= REX_R;
8990
8991 ins->rex = ~(*ins->codep >> 5) & 0x7;
8992 switch (*ins->codep & 0x7)
8993 {
8994 default:
8995 return &bad_opcode;
8996 case 0x1:
8997 vex_table_index = EVEX_0F;
8998 break;
8999 case 0x2:
9000 vex_table_index = EVEX_0F38;
9001 break;
9002 case 0x3:
9003 vex_table_index = EVEX_0F3A;
9004 break;
9005 case 0x4:
9006 vex_table_index = EVEX_MAP4;
9007 ins->evex_type = evex_from_legacy;
9008 if (ins->address_mode != mode_64bit)
9009 return &bad_opcode;
9010 ins->rex |= REX_OPCODE;
9011 break;
9012 case 0x5:
9013 vex_table_index = EVEX_MAP5;
9014 break;
9015 case 0x6:
9016 vex_table_index = EVEX_MAP6;
9017 break;
9018 case 0x7:
9019 vex_table_index = EVEX_MAP7;
9020 break;
9021 }
9022
9023 /* The second byte after 0x62. */
9024 ins->codep++;
9025 ins->vex.w = *ins->codep & 0x80;
9026 if (ins->vex.w && ins->address_mode == mode_64bit)
9027 ins->rex |= REX_W;
9028
9029 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9030
9031 if (!(*ins->codep & 0x4))
9032 ins->rex2 |= REX_X;
9033
9034 switch ((*ins->codep & 0x3))
9035 {
9036 case 0:
9037 break;
9038 case 1:
9039 ins->vex.prefix = DATA_PREFIX_OPCODE;
9040 break;
9041 case 2:
9042 ins->vex.prefix = REPE_PREFIX_OPCODE;
9043 break;
9044 case 3:
9045 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9046 break;
9047 }
9048
9049 /* The third byte after 0x62. */
9050 ins->codep++;
9051
9052 /* Remember the static rounding bits. */
9053 ins->vex.ll = (*ins->codep >> 5) & 3;
9054 ins->vex.b = *ins->codep & 0x10;
9055
9056 ins->vex.v = *ins->codep & 0x8;
9057 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9058 ins->vex.scc = *ins->codep & 0xf;
9059 ins->vex.zeroing = *ins->codep & 0x80;
9060 /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared
9061 when it's an evex_default one. */
9062 ins->vex.nf = *ins->codep & 0x4;
9063
9064 if (ins->address_mode != mode_64bit)
9065 {
9066 /* Report bad for !evex_default and when two fixed values of evex
9067 change.. */
9068 if (ins->evex_type != evex_default
9069 || (ins->rex2 & (REX_B | REX_X)))
9070 return &bad_opcode;
9071 /* In 16/32-bit mode silently ignore following bits. */
9072 ins->rex &= ~REX_B;
9073 ins->rex2 &= ~REX_R;
9074 }
9075
9076 ins->need_vex = 4;
9077
9078 ins->codep++;
9079 vindex = *ins->codep++;
9080 ins->condition_code = vindex & 0xf;
9081 if (vex_table_index != EVEX_MAP7)
9082 dp = &evex_table[vex_table_index][vindex];
9083 else if (vindex == 0xf8)
9084 dp = &map7_f8_opcode;
9085 else
9086 dp = &bad_opcode;
9087 ins->end_codep = ins->codep;
9088 if (!fetch_modrm (ins))
9089 return &err_opcode;
9090
9091 if (ins->modrm.mod == 3 && (ins->rex2 & REX_X))
9092 return &bad_opcode;
9093
9094 /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9095 which has the same encoding as vex.length == 128 and they can share
9096 the same processing with vex.length in OP_VEX. */
9097 if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9098 ins->vex.length = 512;
9099 else
9100 {
9101 switch (ins->vex.ll)
9102 {
9103 case 0x0:
9104 ins->vex.length = 128;
9105 break;
9106 case 0x1:
9107 ins->vex.length = 256;
9108 break;
9109 case 0x2:
9110 ins->vex.length = 512;
9111 break;
9112 default:
9113 return &bad_opcode;
9114 }
9115 }
9116 break;
9117
9118 case 0:
9119 dp = &bad_opcode;
9120 break;
9121
9122 default:
9123 abort ();
9124 }
9125
9126 if (dp->name != NULL)
9127 return dp;
9128 else
9129 return get_valid_dis386 (dp, ins);
9130 }
9131
9132 static bool
9133 get_sib (instr_info *ins, int sizeflag)
9134 {
9135 /* If modrm.mod == 3, operand must be register. */
9136 if (ins->need_modrm
9137 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9138 && ins->modrm.mod != 3
9139 && ins->modrm.rm == 4)
9140 {
9141 if (!fetch_code (ins->info, ins->codep + 2))
9142 return false;
9143 ins->sib.index = (ins->codep[1] >> 3) & 7;
9144 ins->sib.scale = (ins->codep[1] >> 6) & 3;
9145 ins->sib.base = ins->codep[1] & 7;
9146 ins->has_sib = true;
9147 }
9148 else
9149 ins->has_sib = false;
9150
9151 return true;
9152 }
9153
9154 /* Like oappend_with_style (below) but always with text style. */
9155
9156 static void
9157 oappend (instr_info *ins, const char *s)
9158 {
9159 oappend_with_style (ins, s, dis_style_text);
9160 }
9161
9162 /* Like oappend (above), but S is a string starting with '%'. In
9163 Intel syntax, the '%' is elided. */
9164
9165 static void
9166 oappend_register (instr_info *ins, const char *s)
9167 {
9168 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9169 }
9170
9171 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9172 STYLE is the default style to use in the fprintf_styled_func calls,
9173 however, FMT might include embedded style markers (see oappend_style),
9174 these embedded markers are not printed, but instead change the style
9175 used in the next fprintf_styled_func call. */
9176
9177 static void ATTRIBUTE_PRINTF_3
9178 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9179 const char *fmt, ...)
9180 {
9181 va_list ap;
9182 enum disassembler_style curr_style = style;
9183 const char *start, *curr;
9184 char staging_area[50];
9185
9186 va_start (ap, fmt);
9187 /* In particular print_insn()'s processing of op_txt[] can hand rather long
9188 strings here. Bypass vsnprintf() in such cases to avoid capacity issues
9189 with the staging area. */
9190 if (strcmp (fmt, "%s"))
9191 {
9192 int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9193
9194 va_end (ap);
9195
9196 if (res < 0)
9197 return;
9198
9199 if ((size_t) res >= sizeof (staging_area))
9200 abort ();
9201
9202 start = curr = staging_area;
9203 }
9204 else
9205 {
9206 start = curr = va_arg (ap, const char *);
9207 va_end (ap);
9208 }
9209
9210 do
9211 {
9212 if (*curr == '\0'
9213 || (*curr == STYLE_MARKER_CHAR
9214 && ISXDIGIT (*(curr + 1))
9215 && *(curr + 2) == STYLE_MARKER_CHAR))
9216 {
9217 /* Output content between our START position and CURR. */
9218 int len = curr - start;
9219 int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9220 "%.*s", len, start);
9221 if (n < 0)
9222 break;
9223
9224 if (*curr == '\0')
9225 break;
9226
9227 /* Skip over the initial STYLE_MARKER_CHAR. */
9228 ++curr;
9229
9230 /* Update the CURR_STYLE. As there are less than 16 styles, it
9231 is possible, that if the input is corrupted in some way, that
9232 we might set CURR_STYLE to an invalid value. Don't worry
9233 though, we check for this situation. */
9234 if (*curr >= '0' && *curr <= '9')
9235 curr_style = (enum disassembler_style) (*curr - '0');
9236 else if (*curr >= 'a' && *curr <= 'f')
9237 curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9238 else
9239 curr_style = dis_style_text;
9240
9241 /* Check for an invalid style having been selected. This should
9242 never happen, but it doesn't hurt to be a little paranoid. */
9243 if (curr_style > dis_style_comment_start)
9244 curr_style = dis_style_text;
9245
9246 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */
9247 curr += 2;
9248
9249 /* Reset the START to after the style marker. */
9250 start = curr;
9251 }
9252 else
9253 ++curr;
9254 }
9255 while (true);
9256 }
9257
9258 static int
9259 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9260 {
9261 const struct dis386 *dp;
9262 int i;
9263 int ret;
9264 char *op_txt[MAX_OPERANDS];
9265 int needcomma;
9266 bool intel_swap_2_3;
9267 int sizeflag, orig_sizeflag;
9268 const char *p;
9269 struct dis_private priv;
9270 int prefix_length;
9271 int op_count;
9272 instr_info ins = {
9273 .info = info,
9274 .intel_syntax = intel_syntax >= 0
9275 ? intel_syntax
9276 : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9277 .intel_mnemonic = !SYSV386_COMPAT,
9278 .op_index[0 ... MAX_OPERANDS - 1] = -1,
9279 .start_pc = pc,
9280 .start_codep = priv.the_buffer,
9281 .codep = priv.the_buffer,
9282 .obufp = ins.obuf,
9283 .last_lock_prefix = -1,
9284 .last_repz_prefix = -1,
9285 .last_repnz_prefix = -1,
9286 .last_data_prefix = -1,
9287 .last_addr_prefix = -1,
9288 .last_rex_prefix = -1,
9289 .last_rex2_prefix = -1,
9290 .last_seg_prefix = -1,
9291 .fwait_prefix = -1,
9292 };
9293 char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9294
9295 priv.orig_sizeflag = AFLAG | DFLAG;
9296 if ((info->mach & bfd_mach_i386_i386) != 0)
9297 ins.address_mode = mode_32bit;
9298 else if (info->mach == bfd_mach_i386_i8086)
9299 {
9300 ins.address_mode = mode_16bit;
9301 priv.orig_sizeflag = 0;
9302 }
9303 else
9304 ins.address_mode = mode_64bit;
9305
9306 for (p = info->disassembler_options; p != NULL;)
9307 {
9308 if (startswith (p, "amd64"))
9309 ins.isa64 = amd64;
9310 else if (startswith (p, "intel64"))
9311 ins.isa64 = intel64;
9312 else if (startswith (p, "x86-64"))
9313 {
9314 ins.address_mode = mode_64bit;
9315 priv.orig_sizeflag |= AFLAG | DFLAG;
9316 }
9317 else if (startswith (p, "i386"))
9318 {
9319 ins.address_mode = mode_32bit;
9320 priv.orig_sizeflag |= AFLAG | DFLAG;
9321 }
9322 else if (startswith (p, "i8086"))
9323 {
9324 ins.address_mode = mode_16bit;
9325 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9326 }
9327 else if (startswith (p, "intel"))
9328 {
9329 if (startswith (p + 5, "-mnemonic"))
9330 ins.intel_mnemonic = true;
9331 else
9332 ins.intel_syntax = 1;
9333 }
9334 else if (startswith (p, "att"))
9335 {
9336 ins.intel_syntax = 0;
9337 if (startswith (p + 3, "-mnemonic"))
9338 ins.intel_mnemonic = false;
9339 }
9340 else if (startswith (p, "addr"))
9341 {
9342 if (ins.address_mode == mode_64bit)
9343 {
9344 if (p[4] == '3' && p[5] == '2')
9345 priv.orig_sizeflag &= ~AFLAG;
9346 else if (p[4] == '6' && p[5] == '4')
9347 priv.orig_sizeflag |= AFLAG;
9348 }
9349 else
9350 {
9351 if (p[4] == '1' && p[5] == '6')
9352 priv.orig_sizeflag &= ~AFLAG;
9353 else if (p[4] == '3' && p[5] == '2')
9354 priv.orig_sizeflag |= AFLAG;
9355 }
9356 }
9357 else if (startswith (p, "data"))
9358 {
9359 if (p[4] == '1' && p[5] == '6')
9360 priv.orig_sizeflag &= ~DFLAG;
9361 else if (p[4] == '3' && p[5] == '2')
9362 priv.orig_sizeflag |= DFLAG;
9363 }
9364 else if (startswith (p, "suffix"))
9365 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9366
9367 p = strchr (p, ',');
9368 if (p != NULL)
9369 p++;
9370 }
9371
9372 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9373 {
9374 i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9375 return -1;
9376 }
9377
9378 if (ins.intel_syntax)
9379 {
9380 ins.open_char = '[';
9381 ins.close_char = ']';
9382 ins.separator_char = '+';
9383 ins.scale_char = '*';
9384 }
9385 else
9386 {
9387 ins.open_char = '(';
9388 ins.close_char = ')';
9389 ins.separator_char = ',';
9390 ins.scale_char = ',';
9391 }
9392
9393 /* The output looks better if we put 7 bytes on a line, since that
9394 puts most long word instructions on a single line. */
9395 info->bytes_per_line = 7;
9396
9397 info->private_data = &priv;
9398 priv.fetched = 0;
9399 priv.insn_start = pc;
9400
9401 for (i = 0; i < MAX_OPERANDS; ++i)
9402 {
9403 op_out[i][0] = 0;
9404 ins.op_out[i] = op_out[i];
9405 }
9406
9407 sizeflag = priv.orig_sizeflag;
9408
9409 switch (ckprefix (&ins))
9410 {
9411 case ckp_okay:
9412 break;
9413
9414 case ckp_bogus:
9415 /* Too many prefixes or unused REX prefixes. */
9416 for (i = 0;
9417 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9418 i++)
9419 i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9420 (i == 0 ? "" : " "),
9421 prefix_name (ins.address_mode, ins.all_prefixes[i],
9422 sizeflag));
9423 ret = i;
9424 goto out;
9425
9426 case ckp_fetch_error:
9427 goto fetch_error_out;
9428 }
9429
9430 ins.nr_prefixes = ins.codep - ins.start_codep;
9431
9432 if (!fetch_code (info, ins.codep + 1))
9433 {
9434 fetch_error_out:
9435 ret = fetch_error (&ins);
9436 goto out;
9437 }
9438
9439 ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9440
9441 if ((ins.prefixes & PREFIX_FWAIT)
9442 && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9443 {
9444 /* Handle ins.prefixes before fwait. */
9445 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9446 i++)
9447 i386_dis_printf (info, dis_style_mnemonic, "%s ",
9448 prefix_name (ins.address_mode, ins.all_prefixes[i],
9449 sizeflag));
9450 i386_dis_printf (info, dis_style_mnemonic, "fwait");
9451 ret = i + 1;
9452 goto out;
9453 }
9454
9455 /* REX2.M in rex2 prefix represents map0 or map1. */
9456 if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9457 {
9458 if (!ins.rex2)
9459 {
9460 ins.codep++;
9461 if (!fetch_code (info, ins.codep + 1))
9462 goto fetch_error_out;
9463 }
9464
9465 dp = &dis386_twobyte[*ins.codep];
9466 ins.need_modrm = twobyte_has_modrm[*ins.codep];
9467 }
9468 else
9469 {
9470 dp = &dis386[*ins.codep];
9471 ins.need_modrm = onebyte_has_modrm[*ins.codep];
9472 }
9473 ins.condition_code = *ins.codep & 0xf;
9474 ins.codep++;
9475
9476 /* Save sizeflag for printing the extra ins.prefixes later before updating
9477 it for mnemonic and operand processing. The prefix names depend
9478 only on the address mode. */
9479 orig_sizeflag = sizeflag;
9480 if (ins.prefixes & PREFIX_ADDR)
9481 sizeflag ^= AFLAG;
9482 if ((ins.prefixes & PREFIX_DATA))
9483 sizeflag ^= DFLAG;
9484
9485 ins.end_codep = ins.codep;
9486 if (ins.need_modrm && !fetch_modrm (&ins))
9487 goto fetch_error_out;
9488
9489 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9490 {
9491 if (!get_sib (&ins, sizeflag)
9492 || !dofloat (&ins, sizeflag))
9493 goto fetch_error_out;
9494 }
9495 else
9496 {
9497 dp = get_valid_dis386 (dp, &ins);
9498 if (dp == &err_opcode)
9499 goto fetch_error_out;
9500
9501 /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9502 is interpreted as the operand size override. */
9503 if (ins.evex_type == evex_from_legacy
9504 && ins.vex.prefix == DATA_PREFIX_OPCODE)
9505 sizeflag ^= DFLAG;
9506
9507 if(ins.evex_type == evex_default)
9508 ins.vex.nf = false;
9509 else
9510 /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest
9511 are cleared separately.) in mask_register_specifier and keep the low
9512 2 bits of mask_register_specifier to report errors for invalid cases
9513 . */
9514 ins.vex.mask_register_specifier &= 0x3;
9515
9516 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9517 {
9518 if (!get_sib (&ins, sizeflag))
9519 goto fetch_error_out;
9520 for (i = 0; i < MAX_OPERANDS; ++i)
9521 {
9522 ins.obufp = ins.op_out[i];
9523 ins.op_ad = MAX_OPERANDS - 1 - i;
9524 if (dp->op[i].rtn
9525 && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9526 goto fetch_error_out;
9527 /* For EVEX instruction after the last operand masking
9528 should be printed. */
9529 if (i == 0 && ins.vex.evex)
9530 {
9531 /* Don't print {%k0}. */
9532 if (ins.vex.mask_register_specifier)
9533 {
9534 const char *reg_name
9535 = att_names_mask[ins.vex.mask_register_specifier];
9536
9537 oappend (&ins, "{");
9538 oappend_register (&ins, reg_name);
9539 oappend (&ins, "}");
9540
9541 if (ins.vex.zeroing)
9542 oappend (&ins, "{z}");
9543 }
9544 else if (ins.vex.zeroing)
9545 {
9546 oappend (&ins, "{bad}");
9547 continue;
9548 }
9549
9550 /* Instructions with a mask register destination allow for
9551 zeroing-masking only (if any masking at all), which is
9552 _not_ expressed by EVEX.z. */
9553 if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9554 ins.illegal_masking = true;
9555
9556 /* S/G insns require a mask and don't allow
9557 zeroing-masking. */
9558 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9559 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9560 && (ins.vex.mask_register_specifier == 0
9561 || ins.vex.zeroing))
9562 ins.illegal_masking = true;
9563
9564 if (ins.illegal_masking)
9565 oappend (&ins, "/(bad)");
9566 }
9567 }
9568 /* vex.nf is cleared after being consumed. */
9569 if (ins.vex.nf)
9570 oappend (&ins, "{bad-nf}");
9571
9572 /* Check whether rounding control was enabled for an insn not
9573 supporting it, when evex.b is not treated as evex.nd. */
9574 if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9575 && !(ins.evex_used & EVEX_b_used))
9576 {
9577 for (i = 0; i < MAX_OPERANDS; ++i)
9578 {
9579 ins.obufp = ins.op_out[i];
9580 if (*ins.obufp)
9581 continue;
9582 oappend (&ins, names_rounding[ins.vex.ll]);
9583 oappend (&ins, "bad}");
9584 break;
9585 }
9586 }
9587 }
9588 }
9589
9590 /* Clear instruction information. */
9591 info->insn_info_valid = 0;
9592 info->branch_delay_insns = 0;
9593 info->data_size = 0;
9594 info->insn_type = dis_noninsn;
9595 info->target = 0;
9596 info->target2 = 0;
9597
9598 /* Reset jump operation indicator. */
9599 ins.op_is_jump = false;
9600 {
9601 int jump_detection = 0;
9602
9603 /* Extract flags. */
9604 for (i = 0; i < MAX_OPERANDS; ++i)
9605 {
9606 if ((dp->op[i].rtn == OP_J)
9607 || (dp->op[i].rtn == OP_indirE))
9608 jump_detection |= 1;
9609 else if ((dp->op[i].rtn == BND_Fixup)
9610 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9611 jump_detection |= 2;
9612 else if ((dp->op[i].bytemode == cond_jump_mode)
9613 || (dp->op[i].bytemode == loop_jcxz_mode))
9614 jump_detection |= 4;
9615 }
9616
9617 /* Determine if this is a jump or branch. */
9618 if ((jump_detection & 0x3) == 0x3)
9619 {
9620 ins.op_is_jump = true;
9621 if (jump_detection & 0x4)
9622 info->insn_type = dis_condbranch;
9623 else
9624 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9625 ? dis_jsr : dis_branch;
9626 }
9627 }
9628 /* The purpose of placing the check here is to wait for the EVEX prefix for
9629 conditional CMP and TEST to be consumed and cleared, and then make a
9630 unified judgment. Because they are both in map4, we can not distinguish
9631 EVEX prefix for conditional CMP and TEST from others during the
9632 EVEX prefix stage of parsing. */
9633 if (ins.evex_type == evex_from_legacy)
9634 {
9635 /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
9636 all bits of EVEX.vvvv and EVEX.V' must be 1. */
9637 if (!ins.vex.nd && (ins.vex.register_specifier || !ins.vex.v))
9638 {
9639 i386_dis_printf (info, dis_style_text, "(bad)");
9640 ret = ins.end_codep - priv.the_buffer;
9641 goto out;
9642 }
9643
9644 /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
9645 lower 2 bits of EVEX.aaa must be 0. */
9646 if ((ins.vex.mask_register_specifier & 0x3) != 0
9647 || ins.vex.ll != 0 || ins.vex.zeroing != 0)
9648 {
9649 i386_dis_printf (info, dis_style_text, "(bad)");
9650 ret = ins.end_codep - priv.the_buffer;
9651 goto out;
9652 }
9653 }
9654 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9655 are all 0s in inverted form. */
9656 if (ins.need_vex && ins.vex.register_specifier != 0)
9657 {
9658 i386_dis_printf (info, dis_style_text, "(bad)");
9659 ret = ins.end_codep - priv.the_buffer;
9660 goto out;
9661 }
9662
9663 if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
9664 && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
9665 {
9666 i386_dis_printf (info, dis_style_text, "(bad)");
9667 ret = ins.end_codep - priv.the_buffer;
9668 goto out;
9669 }
9670
9671 switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
9672 {
9673 case PREFIX_DATA:
9674 /* If only the data prefix is marked as mandatory, its absence renders
9675 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9676 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9677 {
9678 i386_dis_printf (info, dis_style_text, "(bad)");
9679 ret = ins.end_codep - priv.the_buffer;
9680 goto out;
9681 }
9682 ins.used_prefixes |= PREFIX_DATA;
9683 /* Fall through. */
9684 case PREFIX_OPCODE:
9685 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9686 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9687 used by putop and MMX/SSE operand and may be overridden by the
9688 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9689 separately. */
9690 if (((ins.need_vex
9691 ? ins.vex.prefix == REPE_PREFIX_OPCODE
9692 || ins.vex.prefix == REPNE_PREFIX_OPCODE
9693 : (ins.prefixes
9694 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9695 && (ins.used_prefixes
9696 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9697 || (((ins.need_vex
9698 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9699 : ((ins.prefixes
9700 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9701 == PREFIX_DATA))
9702 && (ins.used_prefixes & PREFIX_DATA) == 0))
9703 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9704 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9705 {
9706 i386_dis_printf (info, dis_style_text, "(bad)");
9707 ret = ins.end_codep - priv.the_buffer;
9708 goto out;
9709 }
9710 break;
9711
9712 case PREFIX_IGNORED:
9713 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9714 origins in all_prefixes. */
9715 ins.used_prefixes &= ~PREFIX_OPCODE;
9716 if (ins.last_data_prefix >= 0)
9717 ins.all_prefixes[ins.last_data_prefix] = 0x66;
9718 if (ins.last_repz_prefix >= 0)
9719 ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9720 if (ins.last_repnz_prefix >= 0)
9721 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9722 break;
9723
9724 case PREFIX_NP_OR_DATA:
9725 if (ins.vex.prefix == REPE_PREFIX_OPCODE
9726 || ins.vex.prefix == REPNE_PREFIX_OPCODE)
9727 {
9728 i386_dis_printf (info, dis_style_text, "(bad)");
9729 ret = ins.end_codep - priv.the_buffer;
9730 goto out;
9731 }
9732 break;
9733
9734 case NO_PREFIX:
9735 if (ins.vex.prefix)
9736 {
9737 i386_dis_printf (info, dis_style_text, "(bad)");
9738 ret = ins.end_codep - priv.the_buffer;
9739 goto out;
9740 }
9741 break;
9742 }
9743
9744 /* Check if the REX prefix is used. */
9745 if ((ins.rex ^ ins.rex_used) == 0
9746 && !ins.need_vex && ins.last_rex_prefix >= 0)
9747 ins.all_prefixes[ins.last_rex_prefix] = 0;
9748
9749 /* Check if the REX2 prefix is used. */
9750 if (ins.last_rex2_prefix >= 0
9751 && ((ins.rex2 & REX2_SPECIAL)
9752 || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
9753 && (ins.rex ^ ins.rex_used) == 0
9754 && (ins.rex2 & 7))))
9755 ins.all_prefixes[ins.last_rex2_prefix] = 0;
9756
9757 /* Check if the SEG prefix is used. */
9758 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9759 | PREFIX_FS | PREFIX_GS)) != 0
9760 && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9761 ins.all_prefixes[ins.last_seg_prefix] = 0;
9762
9763 /* Check if the ADDR prefix is used. */
9764 if ((ins.prefixes & PREFIX_ADDR) != 0
9765 && (ins.used_prefixes & PREFIX_ADDR) != 0)
9766 ins.all_prefixes[ins.last_addr_prefix] = 0;
9767
9768 /* Check if the DATA prefix is used. */
9769 if ((ins.prefixes & PREFIX_DATA) != 0
9770 && (ins.used_prefixes & PREFIX_DATA) != 0
9771 && !ins.need_vex)
9772 ins.all_prefixes[ins.last_data_prefix] = 0;
9773
9774 /* Print the extra ins.prefixes. */
9775 prefix_length = 0;
9776 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9777 if (ins.all_prefixes[i])
9778 {
9779 const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
9780 orig_sizeflag);
9781
9782 if (name == NULL)
9783 abort ();
9784 prefix_length += strlen (name) + 1;
9785 if (ins.all_prefixes[i] == REX2_OPCODE)
9786 i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
9787 (unsigned int) ins.rex2_payload);
9788 else
9789 i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
9790 }
9791
9792 /* Check maximum code length. */
9793 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9794 {
9795 i386_dis_printf (info, dis_style_text, "(bad)");
9796 ret = MAX_CODE_LENGTH;
9797 goto out;
9798 }
9799
9800 /* Calculate the number of operands this instruction has. */
9801 op_count = 0;
9802 for (i = 0; i < MAX_OPERANDS; ++i)
9803 if (*ins.op_out[i] != '\0')
9804 ++op_count;
9805
9806 /* Calculate the number of spaces to print after the mnemonic. */
9807 ins.obufp = ins.mnemonicendp;
9808 if (op_count > 0)
9809 {
9810 i = strlen (ins.obuf) + prefix_length;
9811 if (i < 7)
9812 i = 7 - i;
9813 else
9814 i = 1;
9815 }
9816 else
9817 i = 0;
9818
9819 /* Print the instruction mnemonic along with any trailing whitespace. */
9820 i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9821
9822 /* The enter and bound instructions are printed with operands in the same
9823 order as the intel book; everything else is printed in reverse order. */
9824 intel_swap_2_3 = false;
9825 if (ins.intel_syntax || ins.two_source_ops)
9826 {
9827 for (i = 0; i < MAX_OPERANDS; ++i)
9828 op_txt[i] = ins.op_out[i];
9829
9830 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9831 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9832 {
9833 op_txt[2] = ins.op_out[3];
9834 op_txt[3] = ins.op_out[2];
9835 intel_swap_2_3 = true;
9836 }
9837
9838 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9839 {
9840 bool riprel;
9841
9842 ins.op_ad = ins.op_index[i];
9843 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9844 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9845 riprel = ins.op_riprel[i];
9846 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9847 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9848 }
9849 }
9850 else
9851 {
9852 for (i = 0; i < MAX_OPERANDS; ++i)
9853 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9854 }
9855
9856 needcomma = 0;
9857 for (i = 0; i < MAX_OPERANDS; ++i)
9858 if (*op_txt[i])
9859 {
9860 /* In Intel syntax embedded rounding / SAE are not separate operands.
9861 Instead they're attached to the prior register operand. Simply
9862 suppress emission of the comma to achieve that effect. */
9863 switch (i & -(ins.intel_syntax && dp))
9864 {
9865 case 2:
9866 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9867 needcomma = 0;
9868 break;
9869 case 3:
9870 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9871 needcomma = 0;
9872 break;
9873 }
9874 if (needcomma)
9875 i386_dis_printf (info, dis_style_text, ",");
9876 if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9877 {
9878 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9879
9880 if (ins.op_is_jump)
9881 {
9882 info->insn_info_valid = 1;
9883 info->branch_delay_insns = 0;
9884 info->data_size = 0;
9885 info->target = target;
9886 info->target2 = 0;
9887 }
9888 (*info->print_address_func) (target, info);
9889 }
9890 else
9891 i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
9892 needcomma = 1;
9893 }
9894
9895 for (i = 0; i < MAX_OPERANDS; i++)
9896 if (ins.op_index[i] != -1 && ins.op_riprel[i])
9897 {
9898 i386_dis_printf (info, dis_style_comment_start, " # ");
9899 (*info->print_address_func)
9900 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9901 + ins.op_address[ins.op_index[i]]),
9902 info);
9903 break;
9904 }
9905 ret = ins.codep - priv.the_buffer;
9906 out:
9907 info->private_data = NULL;
9908 return ret;
9909 }
9910
9911 /* Here for backwards compatibility. When gdb stops using
9912 print_insn_i386_att and print_insn_i386_intel these functions can
9913 disappear, and print_insn_i386 be merged into print_insn. */
9914 int
9915 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9916 {
9917 return print_insn (pc, info, 0);
9918 }
9919
9920 int
9921 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9922 {
9923 return print_insn (pc, info, 1);
9924 }
9925
9926 int
9927 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9928 {
9929 return print_insn (pc, info, -1);
9930 }
9931
9932 static const char *float_mem[] = {
9933 /* d8 */
9934 "fadd{s|}",
9935 "fmul{s|}",
9936 "fcom{s|}",
9937 "fcomp{s|}",
9938 "fsub{s|}",
9939 "fsubr{s|}",
9940 "fdiv{s|}",
9941 "fdivr{s|}",
9942 /* d9 */
9943 "fld{s|}",
9944 "(bad)",
9945 "fst{s|}",
9946 "fstp{s|}",
9947 "fldenv{C|C}",
9948 "fldcw",
9949 "fNstenv{C|C}",
9950 "fNstcw",
9951 /* da */
9952 "fiadd{l|}",
9953 "fimul{l|}",
9954 "ficom{l|}",
9955 "ficomp{l|}",
9956 "fisub{l|}",
9957 "fisubr{l|}",
9958 "fidiv{l|}",
9959 "fidivr{l|}",
9960 /* db */
9961 "fild{l|}",
9962 "fisttp{l|}",
9963 "fist{l|}",
9964 "fistp{l|}",
9965 "(bad)",
9966 "fld{t|}",
9967 "(bad)",
9968 "fstp{t|}",
9969 /* dc */
9970 "fadd{l|}",
9971 "fmul{l|}",
9972 "fcom{l|}",
9973 "fcomp{l|}",
9974 "fsub{l|}",
9975 "fsubr{l|}",
9976 "fdiv{l|}",
9977 "fdivr{l|}",
9978 /* dd */
9979 "fld{l|}",
9980 "fisttp{ll|}",
9981 "fst{l||}",
9982 "fstp{l|}",
9983 "frstor{C|C}",
9984 "(bad)",
9985 "fNsave{C|C}",
9986 "fNstsw",
9987 /* de */
9988 "fiadd{s|}",
9989 "fimul{s|}",
9990 "ficom{s|}",
9991 "ficomp{s|}",
9992 "fisub{s|}",
9993 "fisubr{s|}",
9994 "fidiv{s|}",
9995 "fidivr{s|}",
9996 /* df */
9997 "fild{s|}",
9998 "fisttp{s|}",
9999 "fist{s|}",
10000 "fistp{s|}",
10001 "fbld",
10002 "fild{ll|}",
10003 "fbstp",
10004 "fistp{ll|}",
10005 };
10006
10007 static const unsigned char float_mem_mode[] = {
10008 /* d8 */
10009 d_mode,
10010 d_mode,
10011 d_mode,
10012 d_mode,
10013 d_mode,
10014 d_mode,
10015 d_mode,
10016 d_mode,
10017 /* d9 */
10018 d_mode,
10019 0,
10020 d_mode,
10021 d_mode,
10022 0,
10023 w_mode,
10024 0,
10025 w_mode,
10026 /* da */
10027 d_mode,
10028 d_mode,
10029 d_mode,
10030 d_mode,
10031 d_mode,
10032 d_mode,
10033 d_mode,
10034 d_mode,
10035 /* db */
10036 d_mode,
10037 d_mode,
10038 d_mode,
10039 d_mode,
10040 0,
10041 t_mode,
10042 0,
10043 t_mode,
10044 /* dc */
10045 q_mode,
10046 q_mode,
10047 q_mode,
10048 q_mode,
10049 q_mode,
10050 q_mode,
10051 q_mode,
10052 q_mode,
10053 /* dd */
10054 q_mode,
10055 q_mode,
10056 q_mode,
10057 q_mode,
10058 0,
10059 0,
10060 0,
10061 w_mode,
10062 /* de */
10063 w_mode,
10064 w_mode,
10065 w_mode,
10066 w_mode,
10067 w_mode,
10068 w_mode,
10069 w_mode,
10070 w_mode,
10071 /* df */
10072 w_mode,
10073 w_mode,
10074 w_mode,
10075 w_mode,
10076 t_mode,
10077 q_mode,
10078 t_mode,
10079 q_mode
10080 };
10081
10082 #define ST { OP_ST, 0 }
10083 #define STi { OP_STi, 0 }
10084
10085 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10086 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10087 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10088 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10089 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10090 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10091 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10092 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10093 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10094
10095 static const struct dis386 float_reg[][8] = {
10096 /* d8 */
10097 {
10098 { "fadd", { ST, STi }, 0 },
10099 { "fmul", { ST, STi }, 0 },
10100 { "fcom", { STi }, 0 },
10101 { "fcomp", { STi }, 0 },
10102 { "fsub", { ST, STi }, 0 },
10103 { "fsubr", { ST, STi }, 0 },
10104 { "fdiv", { ST, STi }, 0 },
10105 { "fdivr", { ST, STi }, 0 },
10106 },
10107 /* d9 */
10108 {
10109 { "fld", { STi }, 0 },
10110 { "fxch", { STi }, 0 },
10111 { FGRPd9_2 },
10112 { Bad_Opcode },
10113 { FGRPd9_4 },
10114 { FGRPd9_5 },
10115 { FGRPd9_6 },
10116 { FGRPd9_7 },
10117 },
10118 /* da */
10119 {
10120 { "fcmovb", { ST, STi }, 0 },
10121 { "fcmove", { ST, STi }, 0 },
10122 { "fcmovbe",{ ST, STi }, 0 },
10123 { "fcmovu", { ST, STi }, 0 },
10124 { Bad_Opcode },
10125 { FGRPda_5 },
10126 { Bad_Opcode },
10127 { Bad_Opcode },
10128 },
10129 /* db */
10130 {
10131 { "fcmovnb",{ ST, STi }, 0 },
10132 { "fcmovne",{ ST, STi }, 0 },
10133 { "fcmovnbe",{ ST, STi }, 0 },
10134 { "fcmovnu",{ ST, STi }, 0 },
10135 { FGRPdb_4 },
10136 { "fucomi", { ST, STi }, 0 },
10137 { "fcomi", { ST, STi }, 0 },
10138 { Bad_Opcode },
10139 },
10140 /* dc */
10141 {
10142 { "fadd", { STi, ST }, 0 },
10143 { "fmul", { STi, ST }, 0 },
10144 { Bad_Opcode },
10145 { Bad_Opcode },
10146 { "fsub{!M|r}", { STi, ST }, 0 },
10147 { "fsub{M|}", { STi, ST }, 0 },
10148 { "fdiv{!M|r}", { STi, ST }, 0 },
10149 { "fdiv{M|}", { STi, ST }, 0 },
10150 },
10151 /* dd */
10152 {
10153 { "ffree", { STi }, 0 },
10154 { Bad_Opcode },
10155 { "fst", { STi }, 0 },
10156 { "fstp", { STi }, 0 },
10157 { "fucom", { STi }, 0 },
10158 { "fucomp", { STi }, 0 },
10159 { Bad_Opcode },
10160 { Bad_Opcode },
10161 },
10162 /* de */
10163 {
10164 { "faddp", { STi, ST }, 0 },
10165 { "fmulp", { STi, ST }, 0 },
10166 { Bad_Opcode },
10167 { FGRPde_3 },
10168 { "fsub{!M|r}p", { STi, ST }, 0 },
10169 { "fsub{M|}p", { STi, ST }, 0 },
10170 { "fdiv{!M|r}p", { STi, ST }, 0 },
10171 { "fdiv{M|}p", { STi, ST }, 0 },
10172 },
10173 /* df */
10174 {
10175 { "ffreep", { STi }, 0 },
10176 { Bad_Opcode },
10177 { Bad_Opcode },
10178 { Bad_Opcode },
10179 { FGRPdf_4 },
10180 { "fucomip", { ST, STi }, 0 },
10181 { "fcomip", { ST, STi }, 0 },
10182 { Bad_Opcode },
10183 },
10184 };
10185
10186 static const char *const fgrps[][8] = {
10187 /* Bad opcode 0 */
10188 {
10189 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10190 },
10191
10192 /* d9_2 1 */
10193 {
10194 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10195 },
10196
10197 /* d9_4 2 */
10198 {
10199 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10200 },
10201
10202 /* d9_5 3 */
10203 {
10204 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10205 },
10206
10207 /* d9_6 4 */
10208 {
10209 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10210 },
10211
10212 /* d9_7 5 */
10213 {
10214 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10215 },
10216
10217 /* da_5 6 */
10218 {
10219 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10220 },
10221
10222 /* db_4 7 */
10223 {
10224 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10225 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10226 },
10227
10228 /* de_3 8 */
10229 {
10230 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10231 },
10232
10233 /* df_4 9 */
10234 {
10235 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10236 },
10237 };
10238
10239 static const char *const oszc_flags[16] = {
10240 " {dfv=}", " {dfv=cf}", " {dfv=zf}", " {dfv=zf, cf}", " {dfv=sf}",
10241 " {dfv=sf, cf}", " {dfv=sf, zf}", " {dfv=sf, zf, cf}", " {dfv=of}",
10242 " {dfv=of, cf}", " {dfv=of, zf}", " {dfv=of, zf, cf}", " {dfv=of, sf}",
10243 " {dfv=of, sf, cf}", " {dfv=of, sf, zf}", " {dfv=of, sf, zf, cf}"
10244 };
10245
10246 static const char *const scc_suffix[16] = {
10247 "o", "no", "b", "ae", "e", "ne", "be", "a", "s", "ns", "t", "f",
10248 "l", "ge", "le", "g"
10249 };
10250
10251 static void
10252 swap_operand (instr_info *ins)
10253 {
10254 ins->mnemonicendp[0] = '.';
10255 ins->mnemonicendp[1] = 's';
10256 ins->mnemonicendp[2] = '\0';
10257 ins->mnemonicendp += 2;
10258 }
10259
10260 static bool
10261 dofloat (instr_info *ins, int sizeflag)
10262 {
10263 const struct dis386 *dp;
10264 unsigned char floatop = ins->codep[-1];
10265
10266 if (ins->modrm.mod != 3)
10267 {
10268 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10269
10270 putop (ins, float_mem[fp_indx], sizeflag);
10271 ins->obufp = ins->op_out[0];
10272 ins->op_ad = 2;
10273 return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10274 }
10275 /* Skip mod/rm byte. */
10276 MODRM_CHECK;
10277 ins->codep++;
10278
10279 dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10280 if (dp->name == NULL)
10281 {
10282 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10283
10284 /* Instruction fnstsw is only one with strange arg. */
10285 if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10286 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10287 }
10288 else
10289 {
10290 putop (ins, dp->name, sizeflag);
10291
10292 ins->obufp = ins->op_out[0];
10293 ins->op_ad = 2;
10294 if (dp->op[0].rtn
10295 && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10296 return false;
10297
10298 ins->obufp = ins->op_out[1];
10299 ins->op_ad = 1;
10300 if (dp->op[1].rtn
10301 && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10302 return false;
10303 }
10304 return true;
10305 }
10306
10307 static bool
10308 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10309 int sizeflag ATTRIBUTE_UNUSED)
10310 {
10311 oappend_register (ins, "%st");
10312 return true;
10313 }
10314
10315 static bool
10316 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10317 int sizeflag ATTRIBUTE_UNUSED)
10318 {
10319 char scratch[8];
10320 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10321
10322 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10323 abort ();
10324 oappend_register (ins, scratch);
10325 return true;
10326 }
10327
10328 /* Capital letters in template are macros. */
10329 static int
10330 putop (instr_info *ins, const char *in_template, int sizeflag)
10331 {
10332 const char *p;
10333 int alt = 0;
10334 int cond = 1;
10335 unsigned int l = 0, len = 0;
10336 char last[4];
10337 bool evex_printed = false;
10338
10339 /* We don't want to add any prefix or suffix to (bad), so return early. */
10340 if (!strncmp (in_template, "(bad)", 5))
10341 {
10342 oappend (ins, "(bad)");
10343 *ins->obufp = 0;
10344 ins->mnemonicendp = ins->obufp;
10345 return 0;
10346 }
10347
10348 for (p = in_template; *p; p++)
10349 {
10350 if (len > l)
10351 {
10352 if (l >= sizeof (last) || !ISUPPER (*p))
10353 abort ();
10354 last[l++] = *p;
10355 continue;
10356 }
10357 switch (*p)
10358 {
10359 default:
10360 if (ins->evex_type == evex_from_legacy && !ins->vex.nd
10361 && !(ins->rex2 & 7) && !evex_printed)
10362 {
10363 oappend (ins, "{evex} ");
10364 evex_printed = true;
10365 }
10366 *ins->obufp++ = *p;
10367 break;
10368 case '%':
10369 len++;
10370 break;
10371 case '!':
10372 cond = 0;
10373 break;
10374 case '{':
10375 if (ins->intel_syntax)
10376 {
10377 while (*++p != '|')
10378 if (*p == '}' || *p == '\0')
10379 abort ();
10380 alt = 1;
10381 }
10382 break;
10383 case '|':
10384 while (*++p != '}')
10385 {
10386 if (*p == '\0')
10387 abort ();
10388 }
10389 break;
10390 case '}':
10391 alt = 0;
10392 break;
10393 case 'A':
10394 if (ins->intel_syntax)
10395 break;
10396 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10397 || (sizeflag & SUFFIX_ALWAYS))
10398 *ins->obufp++ = 'b';
10399 break;
10400 case 'B':
10401 if (l == 0)
10402 {
10403 case_B:
10404 if (ins->intel_syntax)
10405 break;
10406 if (sizeflag & SUFFIX_ALWAYS)
10407 *ins->obufp++ = 'b';
10408 }
10409 else if (l == 1 && last[0] == 'L')
10410 {
10411 if (ins->address_mode == mode_64bit
10412 && !(ins->prefixes & PREFIX_ADDR))
10413 {
10414 *ins->obufp++ = 'a';
10415 *ins->obufp++ = 'b';
10416 *ins->obufp++ = 's';
10417 }
10418
10419 goto case_B;
10420 }
10421 else
10422 abort ();
10423 break;
10424 case 'C':
10425 if (l == 1 && last[0] == 'C')
10426 {
10427 /* Condition code (taken from the map-0 Jcc entries). */
10428 for (const char *q = dis386[0x70 | ins->condition_code].name + 1;
10429 ISLOWER(*q); ++q)
10430 *ins->obufp++ = *q;
10431 break;
10432 }
10433 else if (l == 1 && last[0] == 'S')
10434 {
10435 /* Add scc suffix. */
10436 oappend (ins, scc_suffix[ins->vex.scc]);
10437
10438 /* For SCC insns, the ND bit is required to be set to 0. */
10439 if (ins->vex.nd)
10440 oappend (ins, "(bad)");
10441
10442 /* These bits have been consumed and should be cleared or restored
10443 to default values. */
10444 ins->vex.v = 1;
10445 ins->vex.nf = false;
10446 ins->vex.mask_register_specifier = 0;
10447 break;
10448 }
10449
10450 if (l)
10451 abort ();
10452 if (ins->intel_syntax && !alt)
10453 break;
10454 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10455 {
10456 if (sizeflag & DFLAG)
10457 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10458 else
10459 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10460 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10461 }
10462 break;
10463 case 'D':
10464 if (l == 1)
10465 {
10466 switch (last[0])
10467 {
10468 case 'X':
10469 if (!ins->vex.evex || ins->vex.w)
10470 *ins->obufp++ = 'd';
10471 else
10472 oappend (ins, "{bad}");
10473 break;
10474 default:
10475 abort ();
10476 }
10477 break;
10478 }
10479 if (l)
10480 abort ();
10481 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10482 break;
10483 USED_REX (REX_W);
10484 if (ins->modrm.mod == 3)
10485 {
10486 if (ins->rex & REX_W)
10487 *ins->obufp++ = 'q';
10488 else
10489 {
10490 if (sizeflag & DFLAG)
10491 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10492 else
10493 *ins->obufp++ = 'w';
10494 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10495 }
10496 }
10497 else
10498 *ins->obufp++ = 'w';
10499 break;
10500 case 'E':
10501 if (l == 1)
10502 {
10503 switch (last[0])
10504 {
10505 case 'X':
10506 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10507 || (ins->rex2 & 7)
10508 || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10509 || !ins->vex.v || ins->vex.mask_register_specifier)
10510 break;
10511 /* AVX512 extends a number of V*D insns to also have V*Q variants,
10512 merely distinguished by EVEX.W. Look for a use of the
10513 respective macro. */
10514 if (ins->vex.w)
10515 {
10516 const char *pct = strchr (p + 1, '%');
10517
10518 if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10519 break;
10520 }
10521 *ins->obufp++ = '{';
10522 *ins->obufp++ = 'e';
10523 *ins->obufp++ = 'v';
10524 *ins->obufp++ = 'e';
10525 *ins->obufp++ = 'x';
10526 *ins->obufp++ = '}';
10527 *ins->obufp++ = ' ';
10528 break;
10529 case 'N':
10530 /* Skip printing {evex} for some special instructions in MAP4. */
10531 evex_printed = true;
10532 break;
10533 default:
10534 abort ();
10535 }
10536 break;
10537 }
10538 /* For jcxz/jecxz */
10539 if (ins->address_mode == mode_64bit)
10540 {
10541 if (sizeflag & AFLAG)
10542 *ins->obufp++ = 'r';
10543 else
10544 *ins->obufp++ = 'e';
10545 }
10546 else
10547 if (sizeflag & AFLAG)
10548 *ins->obufp++ = 'e';
10549 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10550 break;
10551 case 'F':
10552 if (l == 0)
10553 {
10554 if (ins->intel_syntax)
10555 break;
10556 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10557 {
10558 if (sizeflag & AFLAG)
10559 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10560 else
10561 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10562 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10563 }
10564 }
10565 else if (l == 1 && last[0] == 'C')
10566 {
10567 if (ins->vex.nd && !ins->vex.nf)
10568 break;
10569 *ins->obufp++ = 'c';
10570 *ins->obufp++ = 'f';
10571 /* Skip printing {evex} */
10572 evex_printed = true;
10573 }
10574 else if (l == 1 && last[0] == 'N')
10575 {
10576 if (ins->vex.nf)
10577 {
10578 oappend (ins, "{nf} ");
10579 /* This bit needs to be cleared after it is consumed. */
10580 ins->vex.nf = false;
10581 evex_printed = true;
10582 }
10583 else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7)
10584 && ins->vex.v)
10585 {
10586 oappend (ins, "{evex} ");
10587 evex_printed = true;
10588 }
10589 }
10590 else if (l == 1 && last[0] == 'D')
10591 {
10592 /* Get oszc flags value from register_specifier. */
10593 int oszc_value = ~ins->vex.register_specifier & 0xf;
10594
10595 /* Add {dfv=of, sf, zf, cf} flags. */
10596 oappend (ins, oszc_flags[oszc_value]);
10597
10598 /* These bits have been consumed and should be cleared. */
10599 ins->vex.register_specifier = 0;
10600 }
10601 else
10602 abort ();
10603 break;
10604 case 'G':
10605 if (ins->intel_syntax || (ins->obufp[-1] != 's'
10606 && !(sizeflag & SUFFIX_ALWAYS)))
10607 break;
10608 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10609 *ins->obufp++ = 'l';
10610 else
10611 *ins->obufp++ = 'w';
10612 if (!(ins->rex & REX_W))
10613 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10614 break;
10615 case 'H':
10616 if (l == 0)
10617 {
10618 if (ins->intel_syntax)
10619 break;
10620 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10621 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10622 {
10623 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10624 *ins->obufp++ = ',';
10625 *ins->obufp++ = 'p';
10626
10627 /* Set active_seg_prefix even if not set in 64-bit mode
10628 because here it is a valid branch hint. */
10629 if (ins->prefixes & PREFIX_DS)
10630 {
10631 ins->active_seg_prefix = PREFIX_DS;
10632 *ins->obufp++ = 't';
10633 }
10634 else
10635 {
10636 ins->active_seg_prefix = PREFIX_CS;
10637 *ins->obufp++ = 'n';
10638 }
10639 }
10640 }
10641 else if (l == 1 && last[0] == 'X')
10642 {
10643 if (!ins->vex.w)
10644 *ins->obufp++ = 'h';
10645 else
10646 oappend (ins, "{bad}");
10647 }
10648 else
10649 abort ();
10650 break;
10651 case 'K':
10652 USED_REX (REX_W);
10653 if (ins->rex & REX_W)
10654 *ins->obufp++ = 'q';
10655 else
10656 *ins->obufp++ = 'd';
10657 break;
10658 case 'L':
10659 if (ins->intel_syntax)
10660 break;
10661 if (sizeflag & SUFFIX_ALWAYS)
10662 {
10663 if (ins->rex & REX_W)
10664 *ins->obufp++ = 'q';
10665 else
10666 *ins->obufp++ = 'l';
10667 }
10668 break;
10669 case 'M':
10670 if (ins->intel_mnemonic != cond)
10671 *ins->obufp++ = 'r';
10672 break;
10673 case 'N':
10674 if ((ins->prefixes & PREFIX_FWAIT) == 0)
10675 *ins->obufp++ = 'n';
10676 else
10677 ins->used_prefixes |= PREFIX_FWAIT;
10678 break;
10679 case 'O':
10680 USED_REX (REX_W);
10681 if (ins->rex & REX_W)
10682 *ins->obufp++ = 'o';
10683 else if (ins->intel_syntax && (sizeflag & DFLAG))
10684 *ins->obufp++ = 'q';
10685 else
10686 *ins->obufp++ = 'd';
10687 if (!(ins->rex & REX_W))
10688 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10689 break;
10690 case '@':
10691 if (ins->address_mode == mode_64bit
10692 && (ins->isa64 == intel64 || (ins->rex & REX_W)
10693 || !(ins->prefixes & PREFIX_DATA)))
10694 {
10695 if (sizeflag & SUFFIX_ALWAYS)
10696 *ins->obufp++ = 'q';
10697 break;
10698 }
10699 /* Fall through. */
10700 case 'P':
10701 if (l == 0)
10702 {
10703 if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
10704 {
10705 /* For pushp and popp, p is printed and do not print {rex2}
10706 for them. */
10707 *ins->obufp++ = 'p';
10708 ins->rex2 |= REX2_SPECIAL;
10709 break;
10710 }
10711
10712 /* For "!P" print nothing else in Intel syntax. */
10713 if (!cond && ins->intel_syntax)
10714 break;
10715
10716 if ((ins->modrm.mod == 3 || !cond)
10717 && !(sizeflag & SUFFIX_ALWAYS))
10718 break;
10719 /* Fall through. */
10720 case 'T':
10721 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10722 || ((sizeflag & SUFFIX_ALWAYS)
10723 && ins->address_mode != mode_64bit))
10724 {
10725 *ins->obufp++ = (sizeflag & DFLAG)
10726 ? ins->intel_syntax ? 'd' : 'l' : 'w';
10727 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10728 }
10729 else if (sizeflag & SUFFIX_ALWAYS)
10730 *ins->obufp++ = 'q';
10731 }
10732 else if (l == 1 && last[0] == 'L')
10733 {
10734 if ((ins->prefixes & PREFIX_DATA)
10735 || (ins->rex & REX_W)
10736 || (sizeflag & SUFFIX_ALWAYS))
10737 {
10738 USED_REX (REX_W);
10739 if (ins->rex & REX_W)
10740 *ins->obufp++ = 'q';
10741 else
10742 {
10743 if (sizeflag & DFLAG)
10744 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10745 else
10746 *ins->obufp++ = 'w';
10747 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10748 }
10749 }
10750 }
10751 else
10752 abort ();
10753 break;
10754 case 'Q':
10755 if (l == 0)
10756 {
10757 if (ins->intel_syntax && !alt)
10758 break;
10759 USED_REX (REX_W);
10760 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10761 || (sizeflag & SUFFIX_ALWAYS))
10762 {
10763 if (ins->rex & REX_W)
10764 *ins->obufp++ = 'q';
10765 else
10766 {
10767 if (sizeflag & DFLAG)
10768 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10769 else
10770 *ins->obufp++ = 'w';
10771 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10772 }
10773 }
10774 }
10775 else if (l == 1 && last[0] == 'D')
10776 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10777 else if (l == 1 && last[0] == 'L')
10778 {
10779 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10780 : ins->address_mode != mode_64bit)
10781 break;
10782 if ((ins->rex & REX_W))
10783 {
10784 USED_REX (REX_W);
10785 *ins->obufp++ = 'q';
10786 }
10787 else if ((ins->address_mode == mode_64bit && cond)
10788 || (sizeflag & SUFFIX_ALWAYS))
10789 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10790 }
10791 else
10792 abort ();
10793 break;
10794 case 'R':
10795 USED_REX (REX_W);
10796 if (ins->rex & REX_W)
10797 *ins->obufp++ = 'q';
10798 else if (sizeflag & DFLAG)
10799 {
10800 if (ins->intel_syntax)
10801 *ins->obufp++ = 'd';
10802 else
10803 *ins->obufp++ = 'l';
10804 }
10805 else
10806 *ins->obufp++ = 'w';
10807 if (ins->intel_syntax && !p[1]
10808 && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10809 *ins->obufp++ = 'e';
10810 if (!(ins->rex & REX_W))
10811 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10812 break;
10813 case 'S':
10814 if (l == 0)
10815 {
10816 case_S:
10817 if (ins->intel_syntax)
10818 break;
10819 if (sizeflag & SUFFIX_ALWAYS)
10820 {
10821 if (ins->rex & REX_W)
10822 *ins->obufp++ = 'q';
10823 else
10824 {
10825 if (sizeflag & DFLAG)
10826 *ins->obufp++ = 'l';
10827 else
10828 *ins->obufp++ = 'w';
10829 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10830 }
10831 }
10832 break;
10833 }
10834 if (l != 1)
10835 abort ();
10836 switch (last[0])
10837 {
10838 case 'L':
10839 if (ins->address_mode == mode_64bit
10840 && !(ins->prefixes & PREFIX_ADDR))
10841 {
10842 *ins->obufp++ = 'a';
10843 *ins->obufp++ = 'b';
10844 *ins->obufp++ = 's';
10845 }
10846
10847 goto case_S;
10848 case 'X':
10849 if (!ins->vex.evex || !ins->vex.w)
10850 *ins->obufp++ = 's';
10851 else
10852 oappend (ins, "{bad}");
10853 break;
10854 default:
10855 abort ();
10856 }
10857 break;
10858 case 'U':
10859 if (l == 1 && (last[0] == 'Z'))
10860 {
10861 /* Although IMUL/SETcc does not support NDD, the EVEX.ND bit is
10862 used to control whether its destination register has its upper
10863 bits zeroed. */
10864 if (ins->vex.nd)
10865 oappend (ins, "zu");
10866 }
10867 else
10868 abort ();
10869 break;
10870 case 'V':
10871 if (l == 0)
10872 {
10873 if (ins->need_vex)
10874 *ins->obufp++ = 'v';
10875 }
10876 else if (l == 1)
10877 {
10878 switch (last[0])
10879 {
10880 case 'X':
10881 if (ins->vex.evex)
10882 break;
10883 *ins->obufp++ = '{';
10884 *ins->obufp++ = 'v';
10885 *ins->obufp++ = 'e';
10886 *ins->obufp++ = 'x';
10887 *ins->obufp++ = '}';
10888 *ins->obufp++ = ' ';
10889 break;
10890 case 'L':
10891 if (ins->rex & REX_W)
10892 {
10893 *ins->obufp++ = 'a';
10894 *ins->obufp++ = 'b';
10895 *ins->obufp++ = 's';
10896 }
10897 goto case_S;
10898 default:
10899 abort ();
10900 }
10901 }
10902 else
10903 abort ();
10904 break;
10905 case 'W':
10906 if (l == 0)
10907 {
10908 /* operand size flag for cwtl, cbtw */
10909 USED_REX (REX_W);
10910 if (ins->rex & REX_W)
10911 {
10912 if (ins->intel_syntax)
10913 *ins->obufp++ = 'd';
10914 else
10915 *ins->obufp++ = 'l';
10916 }
10917 else if (sizeflag & DFLAG)
10918 *ins->obufp++ = 'w';
10919 else
10920 *ins->obufp++ = 'b';
10921 if (!(ins->rex & REX_W))
10922 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10923 }
10924 else if (l == 1)
10925 {
10926 if (!ins->need_vex)
10927 abort ();
10928 if (last[0] == 'X')
10929 *ins->obufp++ = ins->vex.w ? 'd': 's';
10930 else if (last[0] == 'B')
10931 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10932 else if (last[0] == 'S')
10933 {
10934 if (ins->modrm.mod == 3 && (sizeflag & SUFFIX_ALWAYS))
10935 {
10936 *ins->obufp++ = '.';
10937 *ins->obufp++ = 's';
10938 }
10939 }
10940 else
10941 abort ();
10942 }
10943 else
10944 abort ();
10945 break;
10946 case 'X':
10947 if (l != 0)
10948 abort ();
10949 if (ins->need_vex
10950 ? ins->vex.prefix == DATA_PREFIX_OPCODE
10951 : ins->prefixes & PREFIX_DATA)
10952 {
10953 *ins->obufp++ = 'd';
10954 ins->used_prefixes |= PREFIX_DATA;
10955 }
10956 else
10957 *ins->obufp++ = 's';
10958 break;
10959 case 'Y':
10960 if (l == 0)
10961 {
10962 if (ins->vex.mask_register_specifier)
10963 ins->illegal_masking = true;
10964 }
10965 else if (l == 1 && last[0] == 'X')
10966 {
10967 if (!ins->need_vex)
10968 break;
10969 if (ins->intel_syntax
10970 || ((ins->modrm.mod == 3 || ins->vex.b)
10971 && !(sizeflag & SUFFIX_ALWAYS)))
10972 break;
10973 switch (ins->vex.length)
10974 {
10975 case 128:
10976 *ins->obufp++ = 'x';
10977 break;
10978 case 256:
10979 *ins->obufp++ = 'y';
10980 break;
10981 case 512:
10982 if (!ins->vex.evex)
10983 default:
10984 abort ();
10985 }
10986 }
10987 else
10988 abort ();
10989 break;
10990 case 'Z':
10991 if (l == 0)
10992 {
10993 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10994 ins->modrm.mod = 3;
10995 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10996 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10997 }
10998 else if (l == 1 && last[0] == 'X')
10999 {
11000 if (!ins->vex.evex)
11001 abort ();
11002 if (ins->intel_syntax
11003 || ((ins->modrm.mod == 3 || ins->vex.b)
11004 && !(sizeflag & SUFFIX_ALWAYS)))
11005 break;
11006 switch (ins->vex.length)
11007 {
11008 case 128:
11009 *ins->obufp++ = 'x';
11010 break;
11011 case 256:
11012 *ins->obufp++ = 'y';
11013 break;
11014 case 512:
11015 *ins->obufp++ = 'z';
11016 break;
11017 default:
11018 abort ();
11019 }
11020 }
11021 else
11022 abort ();
11023 break;
11024 case '^':
11025 if (ins->intel_syntax)
11026 break;
11027 if (ins->isa64 == intel64 && (ins->rex & REX_W))
11028 {
11029 USED_REX (REX_W);
11030 *ins->obufp++ = 'q';
11031 break;
11032 }
11033 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11034 {
11035 if (sizeflag & DFLAG)
11036 *ins->obufp++ = 'l';
11037 else
11038 *ins->obufp++ = 'w';
11039 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11040 }
11041 break;
11042 }
11043
11044 if (len == l)
11045 len = l = 0;
11046 }
11047 *ins->obufp = 0;
11048 ins->mnemonicendp = ins->obufp;
11049 return 0;
11050 }
11051
11052 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that
11053 the buffer pointed to by INS->obufp has space. A style marker is made
11054 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11055 digit, followed by another STYLE_MARKER_CHAR. This function assumes
11056 that the number of styles is not greater than 16. */
11057
11058 static void
11059 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11060 {
11061 unsigned num = (unsigned) style;
11062
11063 /* We currently assume that STYLE can be encoded as a single hex
11064 character. If more styles are added then this might start to fail,
11065 and we'll need to expand this code. */
11066 if (num > 0xf)
11067 abort ();
11068
11069 *ins->obufp++ = STYLE_MARKER_CHAR;
11070 *ins->obufp++ = (num < 10 ? ('0' + num)
11071 : ((num < 16) ? ('a' + (num - 10)) : '0'));
11072 *ins->obufp++ = STYLE_MARKER_CHAR;
11073
11074 /* This final null character is not strictly necessary, after inserting a
11075 style marker we should always be inserting some additional content.
11076 However, having the buffer null terminated doesn't cost much, and make
11077 it easier to debug what's going on. Also, if we do ever forget to add
11078 any additional content after this style marker, then the buffer will
11079 still be well formed. */
11080 *ins->obufp = '\0';
11081 }
11082
11083 static void
11084 oappend_with_style (instr_info *ins, const char *s,
11085 enum disassembler_style style)
11086 {
11087 oappend_insert_style (ins, style);
11088 ins->obufp = stpcpy (ins->obufp, s);
11089 }
11090
11091 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11092 the style for the character as STYLE. */
11093
11094 static void
11095 oappend_char_with_style (instr_info *ins, const char c,
11096 enum disassembler_style style)
11097 {
11098 oappend_insert_style (ins, style);
11099 *ins->obufp++ = c;
11100 *ins->obufp = '\0';
11101 }
11102
11103 /* Like oappend_char_with_style, but always uses dis_style_text. */
11104
11105 static void
11106 oappend_char (instr_info *ins, const char c)
11107 {
11108 oappend_char_with_style (ins, c, dis_style_text);
11109 }
11110
11111 static void
11112 append_seg (instr_info *ins)
11113 {
11114 /* Only print the active segment register. */
11115 if (!ins->active_seg_prefix)
11116 return;
11117
11118 ins->used_prefixes |= ins->active_seg_prefix;
11119 switch (ins->active_seg_prefix)
11120 {
11121 case PREFIX_CS:
11122 oappend_register (ins, att_names_seg[1]);
11123 break;
11124 case PREFIX_DS:
11125 oappend_register (ins, att_names_seg[3]);
11126 break;
11127 case PREFIX_SS:
11128 oappend_register (ins, att_names_seg[2]);
11129 break;
11130 case PREFIX_ES:
11131 oappend_register (ins, att_names_seg[0]);
11132 break;
11133 case PREFIX_FS:
11134 oappend_register (ins, att_names_seg[4]);
11135 break;
11136 case PREFIX_GS:
11137 oappend_register (ins, att_names_seg[5]);
11138 break;
11139 default:
11140 break;
11141 }
11142 oappend_char (ins, ':');
11143 }
11144
11145 static void
11146 print_operand_value (instr_info *ins, bfd_vma disp,
11147 enum disassembler_style style)
11148 {
11149 char tmp[30];
11150
11151 if (ins->address_mode != mode_64bit)
11152 disp &= 0xffffffff;
11153 sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11154 oappend_with_style (ins, tmp, style);
11155 }
11156
11157 /* Like oappend, but called for immediate operands. */
11158
11159 static void
11160 oappend_immediate (instr_info *ins, bfd_vma imm)
11161 {
11162 if (!ins->intel_syntax)
11163 oappend_char_with_style (ins, '$', dis_style_immediate);
11164 print_operand_value (ins, imm, dis_style_immediate);
11165 }
11166
11167 /* Put DISP in BUF as signed hex number. */
11168
11169 static void
11170 print_displacement (instr_info *ins, bfd_signed_vma val)
11171 {
11172 char tmp[30];
11173
11174 if (val < 0)
11175 {
11176 oappend_char_with_style (ins, '-', dis_style_address_offset);
11177 val = (bfd_vma) 0 - val;
11178
11179 /* Check for possible overflow. */
11180 if (val < 0)
11181 {
11182 switch (ins->address_mode)
11183 {
11184 case mode_64bit:
11185 oappend_with_style (ins, "0x8000000000000000",
11186 dis_style_address_offset);
11187 break;
11188 case mode_32bit:
11189 oappend_with_style (ins, "0x80000000",
11190 dis_style_address_offset);
11191 break;
11192 case mode_16bit:
11193 oappend_with_style (ins, "0x8000",
11194 dis_style_address_offset);
11195 break;
11196 }
11197 return;
11198 }
11199 }
11200
11201 sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11202 oappend_with_style (ins, tmp, dis_style_address_offset);
11203 }
11204
11205 static void
11206 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11207 {
11208 /* Check if there is a broadcast, when evex.b is not treated as evex.nd. */
11209 if (ins->vex.b && ins->evex_type == evex_default)
11210 {
11211 if (!ins->vex.no_broadcast)
11212 switch (bytemode)
11213 {
11214 case x_mode:
11215 case evex_half_bcst_xmmq_mode:
11216 if (ins->vex.w)
11217 oappend (ins, "QWORD BCST ");
11218 else
11219 oappend (ins, "DWORD BCST ");
11220 break;
11221 case xh_mode:
11222 case evex_half_bcst_xmmqh_mode:
11223 case evex_half_bcst_xmmqdh_mode:
11224 oappend (ins, "WORD BCST ");
11225 break;
11226 default:
11227 ins->vex.no_broadcast = true;
11228 break;
11229 }
11230 return;
11231 }
11232 switch (bytemode)
11233 {
11234 case b_mode:
11235 case b_swap_mode:
11236 case db_mode:
11237 oappend (ins, "BYTE PTR ");
11238 break;
11239 case w_mode:
11240 case w_swap_mode:
11241 case dw_mode:
11242 oappend (ins, "WORD PTR ");
11243 break;
11244 case indir_v_mode:
11245 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11246 {
11247 oappend (ins, "QWORD PTR ");
11248 break;
11249 }
11250 /* Fall through. */
11251 case stack_v_mode:
11252 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11253 || (ins->rex & REX_W)))
11254 {
11255 oappend (ins, "QWORD PTR ");
11256 break;
11257 }
11258 /* Fall through. */
11259 case v_mode:
11260 case v_swap_mode:
11261 case dq_mode:
11262 USED_REX (REX_W);
11263 if (ins->rex & REX_W)
11264 oappend (ins, "QWORD PTR ");
11265 else if (bytemode == dq_mode)
11266 oappend (ins, "DWORD PTR ");
11267 else
11268 {
11269 if (sizeflag & DFLAG)
11270 oappend (ins, "DWORD PTR ");
11271 else
11272 oappend (ins, "WORD PTR ");
11273 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11274 }
11275 break;
11276 case z_mode:
11277 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11278 *ins->obufp++ = 'D';
11279 oappend (ins, "WORD PTR ");
11280 if (!(ins->rex & REX_W))
11281 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11282 break;
11283 case a_mode:
11284 if (sizeflag & DFLAG)
11285 oappend (ins, "QWORD PTR ");
11286 else
11287 oappend (ins, "DWORD PTR ");
11288 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11289 break;
11290 case movsxd_mode:
11291 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11292 oappend (ins, "WORD PTR ");
11293 else
11294 oappend (ins, "DWORD PTR ");
11295 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11296 break;
11297 case d_mode:
11298 case d_swap_mode:
11299 oappend (ins, "DWORD PTR ");
11300 break;
11301 case q_mode:
11302 case q_swap_mode:
11303 oappend (ins, "QWORD PTR ");
11304 break;
11305 case m_mode:
11306 if (ins->address_mode == mode_64bit)
11307 oappend (ins, "QWORD PTR ");
11308 else
11309 oappend (ins, "DWORD PTR ");
11310 break;
11311 case f_mode:
11312 if (sizeflag & DFLAG)
11313 oappend (ins, "FWORD PTR ");
11314 else
11315 oappend (ins, "DWORD PTR ");
11316 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11317 break;
11318 case t_mode:
11319 oappend (ins, "TBYTE PTR ");
11320 break;
11321 case x_mode:
11322 case xh_mode:
11323 case x_swap_mode:
11324 case evex_x_gscat_mode:
11325 case evex_x_nobcst_mode:
11326 case bw_unit_mode:
11327 if (ins->need_vex)
11328 {
11329 switch (ins->vex.length)
11330 {
11331 case 128:
11332 oappend (ins, "XMMWORD PTR ");
11333 break;
11334 case 256:
11335 oappend (ins, "YMMWORD PTR ");
11336 break;
11337 case 512:
11338 oappend (ins, "ZMMWORD PTR ");
11339 break;
11340 default:
11341 abort ();
11342 }
11343 }
11344 else
11345 oappend (ins, "XMMWORD PTR ");
11346 break;
11347 case xmm_mode:
11348 oappend (ins, "XMMWORD PTR ");
11349 break;
11350 case ymm_mode:
11351 oappend (ins, "YMMWORD PTR ");
11352 break;
11353 case xmmq_mode:
11354 case evex_half_bcst_xmmqh_mode:
11355 case evex_half_bcst_xmmq_mode:
11356 switch (ins->vex.length)
11357 {
11358 case 0:
11359 case 128:
11360 oappend (ins, "QWORD PTR ");
11361 break;
11362 case 256:
11363 oappend (ins, "XMMWORD PTR ");
11364 break;
11365 case 512:
11366 oappend (ins, "YMMWORD PTR ");
11367 break;
11368 default:
11369 abort ();
11370 }
11371 break;
11372 case xmmdw_mode:
11373 if (!ins->need_vex)
11374 abort ();
11375
11376 switch (ins->vex.length)
11377 {
11378 case 128:
11379 oappend (ins, "WORD PTR ");
11380 break;
11381 case 256:
11382 oappend (ins, "DWORD PTR ");
11383 break;
11384 case 512:
11385 oappend (ins, "QWORD PTR ");
11386 break;
11387 default:
11388 abort ();
11389 }
11390 break;
11391 case xmmqd_mode:
11392 case evex_half_bcst_xmmqdh_mode:
11393 if (!ins->need_vex)
11394 abort ();
11395
11396 switch (ins->vex.length)
11397 {
11398 case 128:
11399 oappend (ins, "DWORD PTR ");
11400 break;
11401 case 256:
11402 oappend (ins, "QWORD PTR ");
11403 break;
11404 case 512:
11405 oappend (ins, "XMMWORD PTR ");
11406 break;
11407 default:
11408 abort ();
11409 }
11410 break;
11411 case ymmq_mode:
11412 if (!ins->need_vex)
11413 abort ();
11414
11415 switch (ins->vex.length)
11416 {
11417 case 128:
11418 oappend (ins, "QWORD PTR ");
11419 break;
11420 case 256:
11421 oappend (ins, "YMMWORD PTR ");
11422 break;
11423 case 512:
11424 oappend (ins, "ZMMWORD PTR ");
11425 break;
11426 default:
11427 abort ();
11428 }
11429 break;
11430 case o_mode:
11431 oappend (ins, "OWORD PTR ");
11432 break;
11433 case vex_vsib_d_w_dq_mode:
11434 case vex_vsib_q_w_dq_mode:
11435 if (!ins->need_vex)
11436 abort ();
11437 if (ins->vex.w)
11438 oappend (ins, "QWORD PTR ");
11439 else
11440 oappend (ins, "DWORD PTR ");
11441 break;
11442 case mask_bd_mode:
11443 if (!ins->need_vex || ins->vex.length != 128)
11444 abort ();
11445 if (ins->vex.w)
11446 oappend (ins, "DWORD PTR ");
11447 else
11448 oappend (ins, "BYTE PTR ");
11449 break;
11450 case mask_mode:
11451 if (!ins->need_vex)
11452 abort ();
11453 if (ins->vex.w)
11454 oappend (ins, "QWORD PTR ");
11455 else
11456 oappend (ins, "WORD PTR ");
11457 break;
11458 case v_bnd_mode:
11459 case v_bndmk_mode:
11460 default:
11461 break;
11462 }
11463 }
11464
11465 static void
11466 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11467 int bytemode, int sizeflag)
11468 {
11469 const char (*names)[8];
11470
11471 /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11472 as the consumer will inspect it only for the destination operand. */
11473 if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11474 ins->illegal_masking = true;
11475
11476 USED_REX (rexmask);
11477 if (ins->rex & rexmask)
11478 reg += 8;
11479 if (ins->rex2 & rexmask)
11480 reg += 16;
11481
11482 switch (bytemode)
11483 {
11484 case b_mode:
11485 case b_swap_mode:
11486 if (reg & 4)
11487 USED_REX (0);
11488 if (ins->rex || ins->rex2)
11489 names = att_names8rex;
11490 else
11491 names = att_names8;
11492 break;
11493 case w_mode:
11494 names = att_names16;
11495 break;
11496 case d_mode:
11497 case dw_mode:
11498 case db_mode:
11499 names = att_names32;
11500 break;
11501 case q_mode:
11502 names = att_names64;
11503 break;
11504 case m_mode:
11505 case v_bnd_mode:
11506 names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11507 break;
11508 case bnd_mode:
11509 case bnd_swap_mode:
11510 if (reg > 0x3)
11511 {
11512 oappend (ins, "(bad)");
11513 return;
11514 }
11515 names = att_names_bnd;
11516 break;
11517 case indir_v_mode:
11518 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11519 {
11520 names = att_names64;
11521 break;
11522 }
11523 /* Fall through. */
11524 case stack_v_mode:
11525 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11526 || (ins->rex & REX_W)))
11527 {
11528 names = att_names64;
11529 break;
11530 }
11531 bytemode = v_mode;
11532 /* Fall through. */
11533 case v_mode:
11534 case v_swap_mode:
11535 case dq_mode:
11536 USED_REX (REX_W);
11537 if (ins->rex & REX_W)
11538 names = att_names64;
11539 else if (bytemode != v_mode && bytemode != v_swap_mode)
11540 names = att_names32;
11541 else
11542 {
11543 if (sizeflag & DFLAG)
11544 names = att_names32;
11545 else
11546 names = att_names16;
11547 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11548 }
11549 break;
11550 case movsxd_mode:
11551 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11552 names = att_names16;
11553 else
11554 names = att_names32;
11555 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11556 break;
11557 case va_mode:
11558 names = (ins->address_mode == mode_64bit
11559 ? att_names64 : att_names32);
11560 if (!(ins->prefixes & PREFIX_ADDR))
11561 names = (ins->address_mode == mode_16bit
11562 ? att_names16 : names);
11563 else
11564 {
11565 /* Remove "addr16/addr32". */
11566 ins->all_prefixes[ins->last_addr_prefix] = 0;
11567 names = (ins->address_mode != mode_32bit
11568 ? att_names32 : att_names16);
11569 ins->used_prefixes |= PREFIX_ADDR;
11570 }
11571 break;
11572 case mask_bd_mode:
11573 case mask_mode:
11574 if (reg > 0x7)
11575 {
11576 oappend (ins, "(bad)");
11577 return;
11578 }
11579 names = att_names_mask;
11580 break;
11581 case 0:
11582 return;
11583 default:
11584 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11585 return;
11586 }
11587 oappend_register (ins, names[reg]);
11588 }
11589
11590 static bool
11591 get8s (instr_info *ins, bfd_vma *res)
11592 {
11593 if (!fetch_code (ins->info, ins->codep + 1))
11594 return false;
11595 *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11596 return true;
11597 }
11598
11599 static bool
11600 get16 (instr_info *ins, bfd_vma *res)
11601 {
11602 if (!fetch_code (ins->info, ins->codep + 2))
11603 return false;
11604 *res = *ins->codep++;
11605 *res |= (bfd_vma) *ins->codep++ << 8;
11606 return true;
11607 }
11608
11609 static bool
11610 get16s (instr_info *ins, bfd_vma *res)
11611 {
11612 if (!get16 (ins, res))
11613 return false;
11614 *res = (*res ^ 0x8000) - 0x8000;
11615 return true;
11616 }
11617
11618 static bool
11619 get32 (instr_info *ins, bfd_vma *res)
11620 {
11621 if (!fetch_code (ins->info, ins->codep + 4))
11622 return false;
11623 *res = *ins->codep++;
11624 *res |= (bfd_vma) *ins->codep++ << 8;
11625 *res |= (bfd_vma) *ins->codep++ << 16;
11626 *res |= (bfd_vma) *ins->codep++ << 24;
11627 return true;
11628 }
11629
11630 static bool
11631 get32s (instr_info *ins, bfd_vma *res)
11632 {
11633 if (!get32 (ins, res))
11634 return false;
11635
11636 *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11637
11638 return true;
11639 }
11640
11641 static bool
11642 get64 (instr_info *ins, uint64_t *res)
11643 {
11644 unsigned int a;
11645 unsigned int b;
11646
11647 if (!fetch_code (ins->info, ins->codep + 8))
11648 return false;
11649 a = *ins->codep++;
11650 a |= (unsigned int) *ins->codep++ << 8;
11651 a |= (unsigned int) *ins->codep++ << 16;
11652 a |= (unsigned int) *ins->codep++ << 24;
11653 b = *ins->codep++;
11654 b |= (unsigned int) *ins->codep++ << 8;
11655 b |= (unsigned int) *ins->codep++ << 16;
11656 b |= (unsigned int) *ins->codep++ << 24;
11657 *res = a + ((uint64_t) b << 32);
11658 return true;
11659 }
11660
11661 static void
11662 set_op (instr_info *ins, bfd_vma op, bool riprel)
11663 {
11664 ins->op_index[ins->op_ad] = ins->op_ad;
11665 if (ins->address_mode == mode_64bit)
11666 ins->op_address[ins->op_ad] = op;
11667 else /* Mask to get a 32-bit address. */
11668 ins->op_address[ins->op_ad] = op & 0xffffffff;
11669 ins->op_riprel[ins->op_ad] = riprel;
11670 }
11671
11672 static bool
11673 BadOp (instr_info *ins)
11674 {
11675 /* Throw away prefixes and 1st. opcode byte. */
11676 struct dis_private *priv = ins->info->private_data;
11677
11678 ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
11679 ins->obufp = stpcpy (ins->obufp, "(bad)");
11680 return true;
11681 }
11682
11683 static bool
11684 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
11685 int sizeflag ATTRIBUTE_UNUSED)
11686 {
11687 if (ins->modrm.mod != 3)
11688 return BadOp (ins);
11689
11690 /* Skip mod/rm byte. */
11691 MODRM_CHECK;
11692 ins->codep++;
11693 ins->has_skipped_modrm = true;
11694 return true;
11695 }
11696
11697 static bool
11698 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11699 {
11700 int add = (ins->rex & REX_B) ? 8 : 0;
11701 int riprel = 0;
11702 int shift;
11703
11704 add += (ins->rex2 & REX_B) ? 16 : 0;
11705
11706 /* Handles EVEX other than APX EVEX-promoted instructions. */
11707 if (ins->vex.evex && ins->evex_type == evex_default)
11708 {
11709
11710 /* Zeroing-masking is invalid for memory destinations. Set the flag
11711 uniformly, as the consumer will inspect it only for the destination
11712 operand. */
11713 if (ins->vex.zeroing)
11714 ins->illegal_masking = true;
11715
11716 switch (bytemode)
11717 {
11718 case dw_mode:
11719 case w_mode:
11720 case w_swap_mode:
11721 shift = 1;
11722 break;
11723 case db_mode:
11724 case b_mode:
11725 shift = 0;
11726 break;
11727 case dq_mode:
11728 if (ins->address_mode != mode_64bit)
11729 {
11730 case d_mode:
11731 case d_swap_mode:
11732 shift = 2;
11733 break;
11734 }
11735 /* fall through */
11736 case vex_vsib_d_w_dq_mode:
11737 case vex_vsib_q_w_dq_mode:
11738 case evex_x_gscat_mode:
11739 shift = ins->vex.w ? 3 : 2;
11740 break;
11741 case xh_mode:
11742 case evex_half_bcst_xmmqh_mode:
11743 case evex_half_bcst_xmmqdh_mode:
11744 if (ins->vex.b)
11745 {
11746 shift = ins->vex.w ? 2 : 1;
11747 break;
11748 }
11749 /* Fall through. */
11750 case x_mode:
11751 case evex_half_bcst_xmmq_mode:
11752 if (ins->vex.b)
11753 {
11754 shift = ins->vex.w ? 3 : 2;
11755 break;
11756 }
11757 /* Fall through. */
11758 case xmmqd_mode:
11759 case xmmdw_mode:
11760 case xmmq_mode:
11761 case ymmq_mode:
11762 case evex_x_nobcst_mode:
11763 case x_swap_mode:
11764 switch (ins->vex.length)
11765 {
11766 case 128:
11767 shift = 4;
11768 break;
11769 case 256:
11770 shift = 5;
11771 break;
11772 case 512:
11773 shift = 6;
11774 break;
11775 default:
11776 abort ();
11777 }
11778 /* Make necessary corrections to shift for modes that need it. */
11779 if (bytemode == xmmq_mode
11780 || bytemode == evex_half_bcst_xmmqh_mode
11781 || bytemode == evex_half_bcst_xmmq_mode
11782 || (bytemode == ymmq_mode && ins->vex.length == 128))
11783 shift -= 1;
11784 else if (bytemode == xmmqd_mode
11785 || bytemode == evex_half_bcst_xmmqdh_mode)
11786 shift -= 2;
11787 else if (bytemode == xmmdw_mode)
11788 shift -= 3;
11789 break;
11790 case ymm_mode:
11791 shift = 5;
11792 break;
11793 case xmm_mode:
11794 shift = 4;
11795 break;
11796 case q_mode:
11797 case q_swap_mode:
11798 shift = 3;
11799 break;
11800 case bw_unit_mode:
11801 shift = ins->vex.w ? 1 : 0;
11802 break;
11803 default:
11804 abort ();
11805 }
11806 }
11807 else
11808 shift = 0;
11809
11810 USED_REX (REX_B);
11811 if (ins->intel_syntax)
11812 intel_operand_size (ins, bytemode, sizeflag);
11813 append_seg (ins);
11814
11815 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11816 {
11817 /* 32/64 bit address mode */
11818 bfd_vma disp = 0;
11819 int havedisp;
11820 int havebase;
11821 int needindex;
11822 int needaddr32;
11823 int base, rbase;
11824 int vindex = 0;
11825 int scale = 0;
11826 int addr32flag = !((sizeflag & AFLAG)
11827 || bytemode == v_bnd_mode
11828 || bytemode == v_bndmk_mode
11829 || bytemode == bnd_mode
11830 || bytemode == bnd_swap_mode);
11831 bool check_gather = false;
11832 const char (*indexes)[8] = NULL;
11833
11834 havebase = 1;
11835 base = ins->modrm.rm;
11836
11837 if (base == 4)
11838 {
11839 vindex = ins->sib.index;
11840 USED_REX (REX_X);
11841 if (ins->rex & REX_X)
11842 vindex += 8;
11843 switch (bytemode)
11844 {
11845 case vex_vsib_d_w_dq_mode:
11846 case vex_vsib_q_w_dq_mode:
11847 if (!ins->need_vex)
11848 abort ();
11849 if (ins->vex.evex)
11850 {
11851 /* S/G EVEX insns require EVEX.X4 not to be set. */
11852 if (ins->rex2 & REX_X)
11853 {
11854 oappend (ins, "(bad)");
11855 return true;
11856 }
11857
11858 if (!ins->vex.v)
11859 vindex += 16;
11860 check_gather = ins->obufp == ins->op_out[1];
11861 }
11862
11863 switch (ins->vex.length)
11864 {
11865 case 128:
11866 indexes = att_names_xmm;
11867 break;
11868 case 256:
11869 if (!ins->vex.w
11870 || bytemode == vex_vsib_q_w_dq_mode)
11871 indexes = att_names_ymm;
11872 else
11873 indexes = att_names_xmm;
11874 break;
11875 case 512:
11876 if (!ins->vex.w
11877 || bytemode == vex_vsib_q_w_dq_mode)
11878 indexes = att_names_zmm;
11879 else
11880 indexes = att_names_ymm;
11881 break;
11882 default:
11883 abort ();
11884 }
11885 break;
11886 default:
11887 if (ins->rex2 & REX_X)
11888 vindex += 16;
11889
11890 if (vindex != 4)
11891 indexes = ins->address_mode == mode_64bit && !addr32flag
11892 ? att_names64 : att_names32;
11893 break;
11894 }
11895 scale = ins->sib.scale;
11896 base = ins->sib.base;
11897 ins->codep++;
11898 }
11899 else
11900 {
11901 /* Check for mandatory SIB. */
11902 if (bytemode == vex_vsib_d_w_dq_mode
11903 || bytemode == vex_vsib_q_w_dq_mode
11904 || bytemode == vex_sibmem_mode)
11905 {
11906 oappend (ins, "(bad)");
11907 return true;
11908 }
11909 }
11910 rbase = base + add;
11911
11912 switch (ins->modrm.mod)
11913 {
11914 case 0:
11915 if (base == 5)
11916 {
11917 havebase = 0;
11918 if (ins->address_mode == mode_64bit && !ins->has_sib)
11919 riprel = 1;
11920 if (!get32s (ins, &disp))
11921 return false;
11922 if (riprel && bytemode == v_bndmk_mode)
11923 {
11924 oappend (ins, "(bad)");
11925 return true;
11926 }
11927 }
11928 break;
11929 case 1:
11930 if (!get8s (ins, &disp))
11931 return false;
11932 if (ins->vex.evex && shift > 0)
11933 disp <<= shift;
11934 break;
11935 case 2:
11936 if (!get32s (ins, &disp))
11937 return false;
11938 break;
11939 }
11940
11941 needindex = 0;
11942 needaddr32 = 0;
11943 if (ins->has_sib
11944 && !havebase
11945 && !indexes
11946 && ins->address_mode != mode_16bit)
11947 {
11948 if (ins->address_mode == mode_64bit)
11949 {
11950 if (addr32flag)
11951 {
11952 /* Without base nor index registers, zero-extend the
11953 lower 32-bit displacement to 64 bits. */
11954 disp &= 0xffffffff;
11955 needindex = 1;
11956 }
11957 needaddr32 = 1;
11958 }
11959 else
11960 {
11961 /* In 32-bit mode, we need index register to tell [offset]
11962 from [eiz*1 + offset]. */
11963 needindex = 1;
11964 }
11965 }
11966
11967 havedisp = (havebase
11968 || needindex
11969 || (ins->has_sib && (indexes || scale != 0)));
11970
11971 if (!ins->intel_syntax)
11972 if (ins->modrm.mod != 0 || base == 5)
11973 {
11974 if (havedisp || riprel)
11975 print_displacement (ins, disp);
11976 else
11977 print_operand_value (ins, disp, dis_style_address_offset);
11978 if (riprel)
11979 {
11980 set_op (ins, disp, true);
11981 oappend_char (ins, '(');
11982 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11983 dis_style_register);
11984 oappend_char (ins, ')');
11985 }
11986 }
11987
11988 if ((havebase || indexes || needindex || needaddr32 || riprel)
11989 && (ins->address_mode != mode_64bit
11990 || ((bytemode != v_bnd_mode)
11991 && (bytemode != v_bndmk_mode)
11992 && (bytemode != bnd_mode)
11993 && (bytemode != bnd_swap_mode))))
11994 ins->used_prefixes |= PREFIX_ADDR;
11995
11996 if (havedisp || (ins->intel_syntax && riprel))
11997 {
11998 oappend_char (ins, ins->open_char);
11999 if (ins->intel_syntax && riprel)
12000 {
12001 set_op (ins, disp, true);
12002 oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12003 dis_style_register);
12004 }
12005 if (havebase)
12006 oappend_register
12007 (ins,
12008 (ins->address_mode == mode_64bit && !addr32flag
12009 ? att_names64 : att_names32)[rbase]);
12010 if (ins->has_sib)
12011 {
12012 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12013 print index to tell base + index from base. */
12014 if (scale != 0
12015 || needindex
12016 || indexes
12017 || (havebase && base != ESP_REG_NUM))
12018 {
12019 if (!ins->intel_syntax || havebase)
12020 oappend_char (ins, ins->separator_char);
12021 if (indexes)
12022 {
12023 if (ins->address_mode == mode_64bit || vindex < 16)
12024 oappend_register (ins, indexes[vindex]);
12025 else
12026 oappend (ins, "(bad)");
12027 }
12028 else
12029 oappend_register (ins,
12030 ins->address_mode == mode_64bit
12031 && !addr32flag
12032 ? att_index64
12033 : att_index32);
12034
12035 oappend_char (ins, ins->scale_char);
12036 oappend_char_with_style (ins, '0' + (1 << scale),
12037 dis_style_immediate);
12038 }
12039 }
12040 if (ins->intel_syntax
12041 && (disp || ins->modrm.mod != 0 || base == 5))
12042 {
12043 if (!havedisp || (bfd_signed_vma) disp >= 0)
12044 oappend_char (ins, '+');
12045 if (havedisp)
12046 print_displacement (ins, disp);
12047 else
12048 print_operand_value (ins, disp, dis_style_address_offset);
12049 }
12050
12051 oappend_char (ins, ins->close_char);
12052
12053 if (check_gather)
12054 {
12055 /* Both XMM/YMM/ZMM registers must be distinct. */
12056 int modrm_reg = ins->modrm.reg;
12057
12058 if (ins->rex & REX_R)
12059 modrm_reg += 8;
12060 if (ins->rex2 & REX_R)
12061 modrm_reg += 16;
12062 if (vindex == modrm_reg)
12063 oappend (ins, "/(bad)");
12064 }
12065 }
12066 else if (ins->intel_syntax)
12067 {
12068 if (ins->modrm.mod != 0 || base == 5)
12069 {
12070 if (!ins->active_seg_prefix)
12071 {
12072 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12073 oappend (ins, ":");
12074 }
12075 print_operand_value (ins, disp, dis_style_text);
12076 }
12077 }
12078 }
12079 else if (bytemode == v_bnd_mode
12080 || bytemode == v_bndmk_mode
12081 || bytemode == bnd_mode
12082 || bytemode == bnd_swap_mode
12083 || bytemode == vex_vsib_d_w_dq_mode
12084 || bytemode == vex_vsib_q_w_dq_mode)
12085 {
12086 oappend (ins, "(bad)");
12087 return true;
12088 }
12089 else
12090 {
12091 /* 16 bit address mode */
12092 bfd_vma disp = 0;
12093
12094 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12095 switch (ins->modrm.mod)
12096 {
12097 case 0:
12098 if (ins->modrm.rm == 6)
12099 {
12100 case 2:
12101 if (!get16s (ins, &disp))
12102 return false;
12103 }
12104 break;
12105 case 1:
12106 if (!get8s (ins, &disp))
12107 return false;
12108 if (ins->vex.evex && shift > 0)
12109 disp <<= shift;
12110 break;
12111 }
12112
12113 if (!ins->intel_syntax)
12114 if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12115 print_displacement (ins, disp);
12116
12117 if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12118 {
12119 oappend_char (ins, ins->open_char);
12120 oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12121 : att_index16[ins->modrm.rm]);
12122 if (ins->intel_syntax
12123 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12124 {
12125 if ((bfd_signed_vma) disp >= 0)
12126 oappend_char (ins, '+');
12127 print_displacement (ins, disp);
12128 }
12129
12130 oappend_char (ins, ins->close_char);
12131 }
12132 else if (ins->intel_syntax)
12133 {
12134 if (!ins->active_seg_prefix)
12135 {
12136 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12137 oappend (ins, ":");
12138 }
12139 print_operand_value (ins, disp & 0xffff, dis_style_text);
12140 }
12141 }
12142 if (ins->vex.b && ins->evex_type == evex_default)
12143 {
12144 ins->evex_used |= EVEX_b_used;
12145
12146 /* Broadcast can only ever be valid for memory sources. */
12147 if (ins->obufp == ins->op_out[0])
12148 ins->vex.no_broadcast = true;
12149
12150 if (!ins->vex.no_broadcast
12151 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12152 {
12153 if (bytemode == xh_mode)
12154 {
12155 switch (ins->vex.length)
12156 {
12157 case 128:
12158 oappend (ins, "{1to8}");
12159 break;
12160 case 256:
12161 oappend (ins, "{1to16}");
12162 break;
12163 case 512:
12164 oappend (ins, "{1to32}");
12165 break;
12166 default:
12167 abort ();
12168 }
12169 }
12170 else if (bytemode == q_mode
12171 || bytemode == ymmq_mode)
12172 ins->vex.no_broadcast = true;
12173 else if (ins->vex.w
12174 || bytemode == evex_half_bcst_xmmqdh_mode
12175 || bytemode == evex_half_bcst_xmmq_mode)
12176 {
12177 switch (ins->vex.length)
12178 {
12179 case 128:
12180 oappend (ins, "{1to2}");
12181 break;
12182 case 256:
12183 oappend (ins, "{1to4}");
12184 break;
12185 case 512:
12186 oappend (ins, "{1to8}");
12187 break;
12188 default:
12189 abort ();
12190 }
12191 }
12192 else if (bytemode == x_mode
12193 || bytemode == evex_half_bcst_xmmqh_mode)
12194 {
12195 switch (ins->vex.length)
12196 {
12197 case 128:
12198 oappend (ins, "{1to4}");
12199 break;
12200 case 256:
12201 oappend (ins, "{1to8}");
12202 break;
12203 case 512:
12204 oappend (ins, "{1to16}");
12205 break;
12206 default:
12207 abort ();
12208 }
12209 }
12210 else
12211 ins->vex.no_broadcast = true;
12212 }
12213 if (ins->vex.no_broadcast)
12214 oappend (ins, "{bad}");
12215 }
12216
12217 return true;
12218 }
12219
12220 static bool
12221 OP_E (instr_info *ins, int bytemode, int sizeflag)
12222 {
12223 /* Skip mod/rm byte. */
12224 MODRM_CHECK;
12225 if (!ins->has_skipped_modrm)
12226 {
12227 ins->codep++;
12228 ins->has_skipped_modrm = true;
12229 }
12230
12231 if (ins->modrm.mod == 3)
12232 {
12233 if ((sizeflag & SUFFIX_ALWAYS)
12234 && (bytemode == b_swap_mode
12235 || bytemode == bnd_swap_mode
12236 || bytemode == v_swap_mode))
12237 swap_operand (ins);
12238
12239 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12240 return true;
12241 }
12242
12243 /* Masking is invalid for insns with GPR-like memory destination. Set the
12244 flag uniformly, as the consumer will inspect it only for the destination
12245 operand. */
12246 if (ins->vex.mask_register_specifier)
12247 ins->illegal_masking = true;
12248
12249 return OP_E_memory (ins, bytemode, sizeflag);
12250 }
12251
12252 static bool
12253 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12254 {
12255 if (ins->modrm.mod == 3 && bytemode == f_mode)
12256 /* bad lcall/ljmp */
12257 return BadOp (ins);
12258 if (!ins->intel_syntax)
12259 oappend (ins, "*");
12260 return OP_E (ins, bytemode, sizeflag);
12261 }
12262
12263 static bool
12264 OP_G (instr_info *ins, int bytemode, int sizeflag)
12265 {
12266 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12267 return true;
12268 }
12269
12270 static bool
12271 OP_REG (instr_info *ins, int code, int sizeflag)
12272 {
12273 const char *s;
12274 int add = 0;
12275
12276 switch (code)
12277 {
12278 case es_reg: case ss_reg: case cs_reg:
12279 case ds_reg: case fs_reg: case gs_reg:
12280 oappend_register (ins, att_names_seg[code - es_reg]);
12281 return true;
12282 }
12283
12284 USED_REX (REX_B);
12285 if (ins->rex & REX_B)
12286 add = 8;
12287 if (ins->rex2 & REX_B)
12288 add += 16;
12289
12290 switch (code)
12291 {
12292 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12293 case sp_reg: case bp_reg: case si_reg: case di_reg:
12294 s = att_names16[code - ax_reg + add];
12295 break;
12296 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12297 USED_REX (0);
12298 /* Fall through. */
12299 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12300 if (ins->rex)
12301 s = att_names8rex[code - al_reg + add];
12302 else
12303 s = att_names8[code - al_reg];
12304 break;
12305 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12306 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12307 if (ins->address_mode == mode_64bit
12308 && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12309 {
12310 s = att_names64[code - rAX_reg + add];
12311 break;
12312 }
12313 code += eAX_reg - rAX_reg;
12314 /* Fall through. */
12315 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12316 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12317 USED_REX (REX_W);
12318 if (ins->rex & REX_W)
12319 s = att_names64[code - eAX_reg + add];
12320 else
12321 {
12322 if (sizeflag & DFLAG)
12323 s = att_names32[code - eAX_reg + add];
12324 else
12325 s = att_names16[code - eAX_reg + add];
12326 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12327 }
12328 break;
12329 default:
12330 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12331 return true;
12332 }
12333 oappend_register (ins, s);
12334 return true;
12335 }
12336
12337 static bool
12338 OP_IMREG (instr_info *ins, int code, int sizeflag)
12339 {
12340 const char *s;
12341
12342 switch (code)
12343 {
12344 case indir_dx_reg:
12345 if (!ins->intel_syntax)
12346 {
12347 oappend (ins, "(%dx)");
12348 return true;
12349 }
12350 s = att_names16[dx_reg - ax_reg];
12351 break;
12352 case al_reg: case cl_reg:
12353 s = att_names8[code - al_reg];
12354 break;
12355 case eAX_reg:
12356 USED_REX (REX_W);
12357 if (ins->rex & REX_W)
12358 {
12359 s = *att_names64;
12360 break;
12361 }
12362 /* Fall through. */
12363 case z_mode_ax_reg:
12364 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12365 s = *att_names32;
12366 else
12367 s = *att_names16;
12368 if (!(ins->rex & REX_W))
12369 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12370 break;
12371 default:
12372 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12373 return true;
12374 }
12375 oappend_register (ins, s);
12376 return true;
12377 }
12378
12379 static bool
12380 OP_I (instr_info *ins, int bytemode, int sizeflag)
12381 {
12382 bfd_vma op;
12383
12384 switch (bytemode)
12385 {
12386 case b_mode:
12387 if (!fetch_code (ins->info, ins->codep + 1))
12388 return false;
12389 op = *ins->codep++;
12390 break;
12391 case v_mode:
12392 USED_REX (REX_W);
12393 if (ins->rex & REX_W)
12394 {
12395 if (!get32s (ins, &op))
12396 return false;
12397 }
12398 else
12399 {
12400 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12401 if (sizeflag & DFLAG)
12402 {
12403 case d_mode:
12404 if (!get32 (ins, &op))
12405 return false;
12406 }
12407 else
12408 {
12409 /* Fall through. */
12410 case w_mode:
12411 if (!get16 (ins, &op))
12412 return false;
12413 }
12414 }
12415 break;
12416 case const_1_mode:
12417 if (ins->intel_syntax)
12418 oappend_with_style (ins, "1", dis_style_immediate);
12419 else
12420 oappend_with_style (ins, "$1", dis_style_immediate);
12421 return true;
12422 default:
12423 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12424 return true;
12425 }
12426
12427 oappend_immediate (ins, op);
12428 return true;
12429 }
12430
12431 static bool
12432 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12433 {
12434 uint64_t op;
12435
12436 if (bytemode != v_mode || ins->address_mode != mode_64bit
12437 || !(ins->rex & REX_W))
12438 return OP_I (ins, bytemode, sizeflag);
12439
12440 USED_REX (REX_W);
12441
12442 if (!get64 (ins, &op))
12443 return false;
12444
12445 oappend_immediate (ins, op);
12446 return true;
12447 }
12448
12449 static bool
12450 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12451 {
12452 bfd_vma op;
12453
12454 switch (bytemode)
12455 {
12456 case b_mode:
12457 case b_T_mode:
12458 if (!get8s (ins, &op))
12459 return false;
12460 if (bytemode == b_T_mode)
12461 {
12462 if (ins->address_mode != mode_64bit
12463 || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12464 {
12465 /* The operand-size prefix is overridden by a REX prefix. */
12466 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12467 op &= 0xffffffff;
12468 else
12469 op &= 0xffff;
12470 }
12471 }
12472 else
12473 {
12474 if (!(ins->rex & REX_W))
12475 {
12476 if (sizeflag & DFLAG)
12477 op &= 0xffffffff;
12478 else
12479 op &= 0xffff;
12480 }
12481 }
12482 break;
12483 case v_mode:
12484 /* The operand-size prefix is overridden by a REX prefix. */
12485 if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12486 {
12487 if (!get16 (ins, &op))
12488 return false;
12489 }
12490 else if (!get32s (ins, &op))
12491 return false;
12492 break;
12493 default:
12494 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12495 return true;
12496 }
12497
12498 oappend_immediate (ins, op);
12499 return true;
12500 }
12501
12502 static bool
12503 OP_J (instr_info *ins, int bytemode, int sizeflag)
12504 {
12505 bfd_vma disp;
12506 bfd_vma mask = -1;
12507 bfd_vma segment = 0;
12508
12509 switch (bytemode)
12510 {
12511 case b_mode:
12512 if (!get8s (ins, &disp))
12513 return false;
12514 break;
12515 case v_mode:
12516 case dqw_mode:
12517 if ((sizeflag & DFLAG)
12518 || (ins->address_mode == mode_64bit
12519 && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12520 || (ins->rex & REX_W))))
12521 {
12522 if (!get32s (ins, &disp))
12523 return false;
12524 }
12525 else
12526 {
12527 if (!get16s (ins, &disp))
12528 return false;
12529 /* In 16bit mode, address is wrapped around at 64k within
12530 the same segment. Otherwise, a data16 prefix on a jump
12531 instruction means that the pc is masked to 16 bits after
12532 the displacement is added! */
12533 mask = 0xffff;
12534 if ((ins->prefixes & PREFIX_DATA) == 0)
12535 segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12536 & ~((bfd_vma) 0xffff));
12537 }
12538 if (ins->address_mode != mode_64bit
12539 || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12540 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12541 break;
12542 default:
12543 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12544 return true;
12545 }
12546 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12547 | segment;
12548 set_op (ins, disp, false);
12549 print_operand_value (ins, disp, dis_style_text);
12550 return true;
12551 }
12552
12553 static bool
12554 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12555 {
12556 if (bytemode == w_mode)
12557 {
12558 oappend_register (ins, att_names_seg[ins->modrm.reg]);
12559 return true;
12560 }
12561 return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12562 }
12563
12564 static bool
12565 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12566 {
12567 bfd_vma seg, offset;
12568 int res;
12569 char scratch[24];
12570
12571 if (sizeflag & DFLAG)
12572 {
12573 if (!get32 (ins, &offset))
12574 return false;;
12575 }
12576 else if (!get16 (ins, &offset))
12577 return false;
12578 if (!get16 (ins, &seg))
12579 return false;;
12580 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12581
12582 res = snprintf (scratch, ARRAY_SIZE (scratch),
12583 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12584 (unsigned) seg, (unsigned) offset);
12585 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12586 abort ();
12587 oappend (ins, scratch);
12588 return true;
12589 }
12590
12591 static bool
12592 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12593 {
12594 bfd_vma off;
12595
12596 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12597 intel_operand_size (ins, bytemode, sizeflag);
12598 append_seg (ins);
12599
12600 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12601 {
12602 if (!get32 (ins, &off))
12603 return false;
12604 }
12605 else
12606 {
12607 if (!get16 (ins, &off))
12608 return false;
12609 }
12610
12611 if (ins->intel_syntax)
12612 {
12613 if (!ins->active_seg_prefix)
12614 {
12615 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12616 oappend (ins, ":");
12617 }
12618 }
12619 print_operand_value (ins, off, dis_style_address_offset);
12620 return true;
12621 }
12622
12623 static bool
12624 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12625 {
12626 uint64_t off;
12627
12628 if (ins->address_mode != mode_64bit
12629 || (ins->prefixes & PREFIX_ADDR))
12630 return OP_OFF (ins, bytemode, sizeflag);
12631
12632 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12633 intel_operand_size (ins, bytemode, sizeflag);
12634 append_seg (ins);
12635
12636 if (!get64 (ins, &off))
12637 return false;
12638
12639 if (ins->intel_syntax)
12640 {
12641 if (!ins->active_seg_prefix)
12642 {
12643 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12644 oappend (ins, ":");
12645 }
12646 }
12647 print_operand_value (ins, off, dis_style_address_offset);
12648 return true;
12649 }
12650
12651 static void
12652 ptr_reg (instr_info *ins, int code, int sizeflag)
12653 {
12654 const char *s;
12655
12656 *ins->obufp++ = ins->open_char;
12657 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12658 if (ins->address_mode == mode_64bit)
12659 {
12660 if (!(sizeflag & AFLAG))
12661 s = att_names32[code - eAX_reg];
12662 else
12663 s = att_names64[code - eAX_reg];
12664 }
12665 else if (sizeflag & AFLAG)
12666 s = att_names32[code - eAX_reg];
12667 else
12668 s = att_names16[code - eAX_reg];
12669 oappend_register (ins, s);
12670 oappend_char (ins, ins->close_char);
12671 }
12672
12673 static bool
12674 OP_ESreg (instr_info *ins, int code, int sizeflag)
12675 {
12676 if (ins->intel_syntax)
12677 {
12678 switch (ins->codep[-1])
12679 {
12680 case 0x6d: /* insw/insl */
12681 intel_operand_size (ins, z_mode, sizeflag);
12682 break;
12683 case 0xa5: /* movsw/movsl/movsq */
12684 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12685 case 0xab: /* stosw/stosl */
12686 case 0xaf: /* scasw/scasl */
12687 intel_operand_size (ins, v_mode, sizeflag);
12688 break;
12689 default:
12690 intel_operand_size (ins, b_mode, sizeflag);
12691 }
12692 }
12693 oappend_register (ins, att_names_seg[0]);
12694 oappend_char (ins, ':');
12695 ptr_reg (ins, code, sizeflag);
12696 return true;
12697 }
12698
12699 static bool
12700 OP_DSreg (instr_info *ins, int code, int sizeflag)
12701 {
12702 if (ins->intel_syntax)
12703 {
12704 switch (ins->codep[-1])
12705 {
12706 case 0x6f: /* outsw/outsl */
12707 intel_operand_size (ins, z_mode, sizeflag);
12708 break;
12709 case 0xa5: /* movsw/movsl/movsq */
12710 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12711 case 0xad: /* lodsw/lodsl/lodsq */
12712 intel_operand_size (ins, v_mode, sizeflag);
12713 break;
12714 default:
12715 intel_operand_size (ins, b_mode, sizeflag);
12716 }
12717 }
12718 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12719 default segment register DS is printed. */
12720 if (!ins->active_seg_prefix)
12721 ins->active_seg_prefix = PREFIX_DS;
12722 append_seg (ins);
12723 ptr_reg (ins, code, sizeflag);
12724 return true;
12725 }
12726
12727 static bool
12728 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12729 int sizeflag ATTRIBUTE_UNUSED)
12730 {
12731 int add, res;
12732 char scratch[8];
12733
12734 if (ins->rex & REX_R)
12735 {
12736 USED_REX (REX_R);
12737 add = 8;
12738 }
12739 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12740 {
12741 ins->all_prefixes[ins->last_lock_prefix] = 0;
12742 ins->used_prefixes |= PREFIX_LOCK;
12743 add = 8;
12744 }
12745 else
12746 add = 0;
12747 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12748 ins->modrm.reg + add);
12749 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12750 abort ();
12751 oappend_register (ins, scratch);
12752 return true;
12753 }
12754
12755 static bool
12756 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12757 int sizeflag ATTRIBUTE_UNUSED)
12758 {
12759 int add, res;
12760 char scratch[8];
12761
12762 USED_REX (REX_R);
12763 if (ins->rex & REX_R)
12764 add = 8;
12765 else
12766 add = 0;
12767 res = snprintf (scratch, ARRAY_SIZE (scratch),
12768 ins->intel_syntax ? "dr%d" : "%%db%d",
12769 ins->modrm.reg + add);
12770 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12771 abort ();
12772 oappend (ins, scratch);
12773 return true;
12774 }
12775
12776 static bool
12777 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12778 int sizeflag ATTRIBUTE_UNUSED)
12779 {
12780 int res;
12781 char scratch[8];
12782
12783 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12784 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12785 abort ();
12786 oappend_register (ins, scratch);
12787 return true;
12788 }
12789
12790 static bool
12791 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12792 int sizeflag ATTRIBUTE_UNUSED)
12793 {
12794 int reg = ins->modrm.reg;
12795 const char (*names)[8];
12796
12797 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12798 if (ins->prefixes & PREFIX_DATA)
12799 {
12800 names = att_names_xmm;
12801 USED_REX (REX_R);
12802 if (ins->rex & REX_R)
12803 reg += 8;
12804 }
12805 else
12806 names = att_names_mm;
12807 oappend_register (ins, names[reg]);
12808 return true;
12809 }
12810
12811 static void
12812 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12813 {
12814 const char (*names)[8];
12815
12816 if (bytemode == xmmq_mode
12817 || bytemode == evex_half_bcst_xmmqh_mode
12818 || bytemode == evex_half_bcst_xmmq_mode)
12819 {
12820 switch (ins->vex.length)
12821 {
12822 case 0:
12823 case 128:
12824 case 256:
12825 names = att_names_xmm;
12826 break;
12827 case 512:
12828 names = att_names_ymm;
12829 ins->evex_used |= EVEX_len_used;
12830 break;
12831 default:
12832 abort ();
12833 }
12834 }
12835 else if (bytemode == ymm_mode)
12836 names = att_names_ymm;
12837 else if (bytemode == tmm_mode)
12838 {
12839 if (reg >= 8)
12840 {
12841 oappend (ins, "(bad)");
12842 return;
12843 }
12844 names = att_names_tmm;
12845 }
12846 else if (ins->need_vex
12847 && bytemode != xmm_mode
12848 && bytemode != scalar_mode
12849 && bytemode != xmmdw_mode
12850 && bytemode != xmmqd_mode
12851 && bytemode != evex_half_bcst_xmmqdh_mode
12852 && bytemode != w_swap_mode
12853 && bytemode != b_mode
12854 && bytemode != w_mode
12855 && bytemode != d_mode
12856 && bytemode != q_mode)
12857 {
12858 ins->evex_used |= EVEX_len_used;
12859 switch (ins->vex.length)
12860 {
12861 case 128:
12862 names = att_names_xmm;
12863 break;
12864 case 256:
12865 if (ins->vex.w
12866 || bytemode != vex_vsib_q_w_dq_mode)
12867 names = att_names_ymm;
12868 else
12869 names = att_names_xmm;
12870 break;
12871 case 512:
12872 if (ins->vex.w
12873 || bytemode != vex_vsib_q_w_dq_mode)
12874 names = att_names_zmm;
12875 else
12876 names = att_names_ymm;
12877 break;
12878 default:
12879 abort ();
12880 }
12881 }
12882 else
12883 names = att_names_xmm;
12884 oappend_register (ins, names[reg]);
12885 }
12886
12887 static bool
12888 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12889 {
12890 unsigned int reg = ins->modrm.reg;
12891
12892 USED_REX (REX_R);
12893 if (ins->rex & REX_R)
12894 reg += 8;
12895 if (ins->vex.evex)
12896 {
12897 if (ins->rex2 & REX_R)
12898 reg += 16;
12899 }
12900
12901 if (bytemode == tmm_mode)
12902 ins->modrm.reg = reg;
12903 else if (bytemode == scalar_mode)
12904 ins->vex.no_broadcast = true;
12905
12906 print_vector_reg (ins, reg, bytemode);
12907 return true;
12908 }
12909
12910 static bool
12911 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12912 {
12913 int reg;
12914 const char (*names)[8];
12915
12916 if (ins->modrm.mod != 3)
12917 {
12918 if (ins->intel_syntax
12919 && (bytemode == v_mode || bytemode == v_swap_mode))
12920 {
12921 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12922 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12923 }
12924 return OP_E (ins, bytemode, sizeflag);
12925 }
12926
12927 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12928 swap_operand (ins);
12929
12930 /* Skip mod/rm byte. */
12931 MODRM_CHECK;
12932 ins->codep++;
12933 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12934 reg = ins->modrm.rm;
12935 if (ins->prefixes & PREFIX_DATA)
12936 {
12937 names = att_names_xmm;
12938 USED_REX (REX_B);
12939 if (ins->rex & REX_B)
12940 reg += 8;
12941 }
12942 else
12943 names = att_names_mm;
12944 oappend_register (ins, names[reg]);
12945 return true;
12946 }
12947
12948 /* cvt* are the only instructions in sse2 which have
12949 both SSE and MMX operands and also have 0x66 prefix
12950 in their opcode. 0x66 was originally used to differentiate
12951 between SSE and MMX instruction(operands). So we have to handle the
12952 cvt* separately using OP_EMC and OP_MXC */
12953 static bool
12954 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12955 {
12956 if (ins->modrm.mod != 3)
12957 {
12958 if (ins->intel_syntax && bytemode == v_mode)
12959 {
12960 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12961 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12962 }
12963 return OP_E (ins, bytemode, sizeflag);
12964 }
12965
12966 /* Skip mod/rm byte. */
12967 MODRM_CHECK;
12968 ins->codep++;
12969 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12970 oappend_register (ins, att_names_mm[ins->modrm.rm]);
12971 return true;
12972 }
12973
12974 static bool
12975 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12976 int sizeflag ATTRIBUTE_UNUSED)
12977 {
12978 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12979 oappend_register (ins, att_names_mm[ins->modrm.reg]);
12980 return true;
12981 }
12982
12983 static bool
12984 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12985 {
12986 int reg;
12987
12988 /* Skip mod/rm byte. */
12989 MODRM_CHECK;
12990 ins->codep++;
12991
12992 if (bytemode == dq_mode)
12993 bytemode = ins->vex.w ? q_mode : d_mode;
12994
12995 if (ins->modrm.mod != 3)
12996 return OP_E_memory (ins, bytemode, sizeflag);
12997
12998 reg = ins->modrm.rm;
12999 USED_REX (REX_B);
13000 if (ins->rex & REX_B)
13001 reg += 8;
13002 if (ins->rex2 & REX_B)
13003 reg += 16;
13004 if (ins->vex.evex)
13005 {
13006 USED_REX (REX_X);
13007 if ((ins->rex & REX_X))
13008 reg += 16;
13009 }
13010
13011 if ((sizeflag & SUFFIX_ALWAYS)
13012 && (bytemode == x_swap_mode
13013 || bytemode == w_swap_mode
13014 || bytemode == d_swap_mode
13015 || bytemode == q_swap_mode))
13016 swap_operand (ins);
13017
13018 if (bytemode == tmm_mode)
13019 ins->modrm.rm = reg;
13020
13021 print_vector_reg (ins, reg, bytemode);
13022 return true;
13023 }
13024
13025 static bool
13026 OP_R (instr_info *ins, int bytemode, int sizeflag)
13027 {
13028 if (ins->modrm.mod != 3)
13029 return BadOp (ins);
13030
13031 switch (bytemode)
13032 {
13033 case d_mode:
13034 case dq_mode:
13035 case q_mode:
13036 case mask_mode:
13037 return OP_E (ins, bytemode, sizeflag);
13038 case q_mm_mode:
13039 return OP_EM (ins, x_mode, sizeflag);
13040 case xmm_mode:
13041 if (ins->vex.length <= 128)
13042 break;
13043 return BadOp (ins);
13044 }
13045
13046 return OP_EX (ins, bytemode, sizeflag);
13047 }
13048
13049 static bool
13050 OP_M (instr_info *ins, int bytemode, int sizeflag)
13051 {
13052 /* Skip mod/rm byte. */
13053 MODRM_CHECK;
13054 ins->codep++;
13055
13056 if (ins->modrm.mod == 3)
13057 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13058 return BadOp (ins);
13059
13060 if (bytemode == x_mode)
13061 ins->vex.no_broadcast = true;
13062
13063 return OP_E_memory (ins, bytemode, sizeflag);
13064 }
13065
13066 static bool
13067 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13068 {
13069 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13070 return BadOp (ins);
13071 return OP_E (ins, bytemode, sizeflag);
13072 }
13073
13074 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13075 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13076
13077 static bool
13078 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13079 {
13080 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13081 {
13082 ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13083 return true;
13084 }
13085 if (opnd == 0)
13086 return OP_REG (ins, eAX_reg, sizeflag);
13087 return OP_IMREG (ins, eAX_reg, sizeflag);
13088 }
13089
13090 static const char *const Suffix3DNow[] = {
13091 /* 00 */ NULL, NULL, NULL, NULL,
13092 /* 04 */ NULL, NULL, NULL, NULL,
13093 /* 08 */ NULL, NULL, NULL, NULL,
13094 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13095 /* 10 */ NULL, NULL, NULL, NULL,
13096 /* 14 */ NULL, NULL, NULL, NULL,
13097 /* 18 */ NULL, NULL, NULL, NULL,
13098 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13099 /* 20 */ NULL, NULL, NULL, NULL,
13100 /* 24 */ NULL, NULL, NULL, NULL,
13101 /* 28 */ NULL, NULL, NULL, NULL,
13102 /* 2C */ NULL, NULL, NULL, NULL,
13103 /* 30 */ NULL, NULL, NULL, NULL,
13104 /* 34 */ NULL, NULL, NULL, NULL,
13105 /* 38 */ NULL, NULL, NULL, NULL,
13106 /* 3C */ NULL, NULL, NULL, NULL,
13107 /* 40 */ NULL, NULL, NULL, NULL,
13108 /* 44 */ NULL, NULL, NULL, NULL,
13109 /* 48 */ NULL, NULL, NULL, NULL,
13110 /* 4C */ NULL, NULL, NULL, NULL,
13111 /* 50 */ NULL, NULL, NULL, NULL,
13112 /* 54 */ NULL, NULL, NULL, NULL,
13113 /* 58 */ NULL, NULL, NULL, NULL,
13114 /* 5C */ NULL, NULL, NULL, NULL,
13115 /* 60 */ NULL, NULL, NULL, NULL,
13116 /* 64 */ NULL, NULL, NULL, NULL,
13117 /* 68 */ NULL, NULL, NULL, NULL,
13118 /* 6C */ NULL, NULL, NULL, NULL,
13119 /* 70 */ NULL, NULL, NULL, NULL,
13120 /* 74 */ NULL, NULL, NULL, NULL,
13121 /* 78 */ NULL, NULL, NULL, NULL,
13122 /* 7C */ NULL, NULL, NULL, NULL,
13123 /* 80 */ NULL, NULL, NULL, NULL,
13124 /* 84 */ NULL, NULL, NULL, NULL,
13125 /* 88 */ NULL, NULL, "pfnacc", NULL,
13126 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13127 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13128 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13129 /* 98 */ NULL, NULL, "pfsub", NULL,
13130 /* 9C */ NULL, NULL, "pfadd", NULL,
13131 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13132 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13133 /* A8 */ NULL, NULL, "pfsubr", NULL,
13134 /* AC */ NULL, NULL, "pfacc", NULL,
13135 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13136 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13137 /* B8 */ NULL, NULL, NULL, "pswapd",
13138 /* BC */ NULL, NULL, NULL, "pavgusb",
13139 /* C0 */ NULL, NULL, NULL, NULL,
13140 /* C4 */ NULL, NULL, NULL, NULL,
13141 /* C8 */ NULL, NULL, NULL, NULL,
13142 /* CC */ NULL, NULL, NULL, NULL,
13143 /* D0 */ NULL, NULL, NULL, NULL,
13144 /* D4 */ NULL, NULL, NULL, NULL,
13145 /* D8 */ NULL, NULL, NULL, NULL,
13146 /* DC */ NULL, NULL, NULL, NULL,
13147 /* E0 */ NULL, NULL, NULL, NULL,
13148 /* E4 */ NULL, NULL, NULL, NULL,
13149 /* E8 */ NULL, NULL, NULL, NULL,
13150 /* EC */ NULL, NULL, NULL, NULL,
13151 /* F0 */ NULL, NULL, NULL, NULL,
13152 /* F4 */ NULL, NULL, NULL, NULL,
13153 /* F8 */ NULL, NULL, NULL, NULL,
13154 /* FC */ NULL, NULL, NULL, NULL,
13155 };
13156
13157 static bool
13158 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13159 int sizeflag ATTRIBUTE_UNUSED)
13160 {
13161 const char *mnemonic;
13162
13163 if (!fetch_code (ins->info, ins->codep + 1))
13164 return false;
13165 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13166 place where an 8-bit immediate would normally go. ie. the last
13167 byte of the instruction. */
13168 ins->obufp = ins->mnemonicendp;
13169 mnemonic = Suffix3DNow[*ins->codep++];
13170 if (mnemonic)
13171 ins->obufp = stpcpy (ins->obufp, mnemonic);
13172 else
13173 {
13174 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13175 of the opcode (0x0f0f) and the opcode suffix, we need to do
13176 all the ins->modrm processing first, and don't know until now that
13177 we have a bad opcode. This necessitates some cleaning up. */
13178 ins->op_out[0][0] = '\0';
13179 ins->op_out[1][0] = '\0';
13180 BadOp (ins);
13181 }
13182 ins->mnemonicendp = ins->obufp;
13183 return true;
13184 }
13185
13186 static const struct op simd_cmp_op[] =
13187 {
13188 { STRING_COMMA_LEN ("eq") },
13189 { STRING_COMMA_LEN ("lt") },
13190 { STRING_COMMA_LEN ("le") },
13191 { STRING_COMMA_LEN ("unord") },
13192 { STRING_COMMA_LEN ("neq") },
13193 { STRING_COMMA_LEN ("nlt") },
13194 { STRING_COMMA_LEN ("nle") },
13195 { STRING_COMMA_LEN ("ord") }
13196 };
13197
13198 static const struct op vex_cmp_op[] =
13199 {
13200 { STRING_COMMA_LEN ("eq_uq") },
13201 { STRING_COMMA_LEN ("nge") },
13202 { STRING_COMMA_LEN ("ngt") },
13203 { STRING_COMMA_LEN ("false") },
13204 { STRING_COMMA_LEN ("neq_oq") },
13205 { STRING_COMMA_LEN ("ge") },
13206 { STRING_COMMA_LEN ("gt") },
13207 { STRING_COMMA_LEN ("true") },
13208 { STRING_COMMA_LEN ("eq_os") },
13209 { STRING_COMMA_LEN ("lt_oq") },
13210 { STRING_COMMA_LEN ("le_oq") },
13211 { STRING_COMMA_LEN ("unord_s") },
13212 { STRING_COMMA_LEN ("neq_us") },
13213 { STRING_COMMA_LEN ("nlt_uq") },
13214 { STRING_COMMA_LEN ("nle_uq") },
13215 { STRING_COMMA_LEN ("ord_s") },
13216 { STRING_COMMA_LEN ("eq_us") },
13217 { STRING_COMMA_LEN ("nge_uq") },
13218 { STRING_COMMA_LEN ("ngt_uq") },
13219 { STRING_COMMA_LEN ("false_os") },
13220 { STRING_COMMA_LEN ("neq_os") },
13221 { STRING_COMMA_LEN ("ge_oq") },
13222 { STRING_COMMA_LEN ("gt_oq") },
13223 { STRING_COMMA_LEN ("true_us") },
13224 };
13225
13226 static bool
13227 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13228 int sizeflag ATTRIBUTE_UNUSED)
13229 {
13230 unsigned int cmp_type;
13231
13232 if (!fetch_code (ins->info, ins->codep + 1))
13233 return false;
13234 cmp_type = *ins->codep++;
13235 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13236 {
13237 char suffix[3];
13238 char *p = ins->mnemonicendp - 2;
13239 suffix[0] = p[0];
13240 suffix[1] = p[1];
13241 suffix[2] = '\0';
13242 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13243 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13244 }
13245 else if (ins->need_vex
13246 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13247 {
13248 char suffix[3];
13249 char *p = ins->mnemonicendp - 2;
13250 suffix[0] = p[0];
13251 suffix[1] = p[1];
13252 suffix[2] = '\0';
13253 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13254 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13255 ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13256 }
13257 else
13258 {
13259 /* We have a reserved extension byte. Output it directly. */
13260 oappend_immediate (ins, cmp_type);
13261 }
13262 return true;
13263 }
13264
13265 static bool
13266 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13267 {
13268 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13269 if (!ins->intel_syntax)
13270 {
13271 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13272 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13273 if (bytemode == eBX_reg)
13274 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13275 ins->two_source_ops = true;
13276 }
13277 /* Skip mod/rm byte. */
13278 MODRM_CHECK;
13279 ins->codep++;
13280 return true;
13281 }
13282
13283 static bool
13284 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13285 int sizeflag ATTRIBUTE_UNUSED)
13286 {
13287 /* monitor %{e,r,}ax,%ecx,%edx" */
13288 if (!ins->intel_syntax)
13289 {
13290 const char (*names)[8] = (ins->address_mode == mode_64bit
13291 ? att_names64 : att_names32);
13292
13293 if (ins->prefixes & PREFIX_ADDR)
13294 {
13295 /* Remove "addr16/addr32". */
13296 ins->all_prefixes[ins->last_addr_prefix] = 0;
13297 names = (ins->address_mode != mode_32bit
13298 ? att_names32 : att_names16);
13299 ins->used_prefixes |= PREFIX_ADDR;
13300 }
13301 else if (ins->address_mode == mode_16bit)
13302 names = att_names16;
13303 strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13304 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13305 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13306 ins->two_source_ops = true;
13307 }
13308 /* Skip mod/rm byte. */
13309 MODRM_CHECK;
13310 ins->codep++;
13311 return true;
13312 }
13313
13314 static bool
13315 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13316 {
13317 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13318 lods and stos. */
13319 if (ins->prefixes & PREFIX_REPZ)
13320 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13321
13322 switch (bytemode)
13323 {
13324 case al_reg:
13325 case eAX_reg:
13326 case indir_dx_reg:
13327 return OP_IMREG (ins, bytemode, sizeflag);
13328 case eDI_reg:
13329 return OP_ESreg (ins, bytemode, sizeflag);
13330 case eSI_reg:
13331 return OP_DSreg (ins, bytemode, sizeflag);
13332 default:
13333 abort ();
13334 break;
13335 }
13336 return true;
13337 }
13338
13339 static bool
13340 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13341 int sizeflag ATTRIBUTE_UNUSED)
13342 {
13343 if (ins->isa64 != amd64)
13344 return true;
13345
13346 ins->obufp = ins->obuf;
13347 BadOp (ins);
13348 ins->mnemonicendp = ins->obufp;
13349 ++ins->codep;
13350 return true;
13351 }
13352
13353 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13354 "bnd". */
13355
13356 static bool
13357 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13358 int sizeflag ATTRIBUTE_UNUSED)
13359 {
13360 if (ins->prefixes & PREFIX_REPNZ)
13361 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13362 return true;
13363 }
13364
13365 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13366 "notrack". */
13367
13368 static bool
13369 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13370 int sizeflag ATTRIBUTE_UNUSED)
13371 {
13372 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13373 we've seen a PREFIX_DS. */
13374 if ((ins->prefixes & PREFIX_DS) != 0
13375 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13376 {
13377 /* NOTRACK prefix is only valid on indirect branch instructions.
13378 NB: DATA prefix is unsupported for Intel64. */
13379 ins->active_seg_prefix = 0;
13380 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13381 }
13382 return true;
13383 }
13384
13385 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13386 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13387 */
13388
13389 static bool
13390 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13391 {
13392 if (ins->modrm.mod != 3
13393 && (ins->prefixes & PREFIX_LOCK) != 0)
13394 {
13395 if (ins->prefixes & PREFIX_REPZ)
13396 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13397 if (ins->prefixes & PREFIX_REPNZ)
13398 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13399 }
13400
13401 return OP_E (ins, bytemode, sizeflag);
13402 }
13403
13404 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13405 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13406 */
13407
13408 static bool
13409 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13410 {
13411 if (ins->modrm.mod != 3)
13412 {
13413 if (ins->prefixes & PREFIX_REPZ)
13414 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13415 if (ins->prefixes & PREFIX_REPNZ)
13416 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13417 }
13418
13419 return OP_E (ins, bytemode, sizeflag);
13420 }
13421
13422 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13423 "xrelease" for memory operand. No check for LOCK prefix. */
13424
13425 static bool
13426 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13427 {
13428 if (ins->modrm.mod != 3
13429 && ins->last_repz_prefix > ins->last_repnz_prefix
13430 && (ins->prefixes & PREFIX_REPZ) != 0)
13431 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13432
13433 return OP_E (ins, bytemode, sizeflag);
13434 }
13435
13436 static bool
13437 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13438 {
13439 USED_REX (REX_W);
13440 if (ins->rex & REX_W)
13441 {
13442 /* Change cmpxchg8b to cmpxchg16b. */
13443 char *p = ins->mnemonicendp - 2;
13444 ins->mnemonicendp = stpcpy (p, "16b");
13445 bytemode = o_mode;
13446 }
13447 else if ((ins->prefixes & PREFIX_LOCK) != 0)
13448 {
13449 if (ins->prefixes & PREFIX_REPZ)
13450 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13451 if (ins->prefixes & PREFIX_REPNZ)
13452 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13453 }
13454
13455 return OP_M (ins, bytemode, sizeflag);
13456 }
13457
13458 static bool
13459 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13460 {
13461 const char (*names)[8] = att_names_xmm;
13462
13463 if (ins->need_vex)
13464 {
13465 switch (ins->vex.length)
13466 {
13467 case 128:
13468 break;
13469 case 256:
13470 names = att_names_ymm;
13471 break;
13472 default:
13473 abort ();
13474 }
13475 }
13476 oappend_register (ins, names[reg]);
13477 return true;
13478 }
13479
13480 static bool
13481 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13482 {
13483 /* Add proper suffix to "fxsave" and "fxrstor". */
13484 USED_REX (REX_W);
13485 if (ins->rex & REX_W)
13486 {
13487 char *p = ins->mnemonicendp;
13488 *p++ = '6';
13489 *p++ = '4';
13490 *p = '\0';
13491 ins->mnemonicendp = p;
13492 }
13493 return OP_M (ins, bytemode, sizeflag);
13494 }
13495
13496 /* Display the destination register operand for instructions with
13497 VEX. */
13498
13499 static bool
13500 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13501 {
13502 int reg, modrm_reg, sib_index = -1;
13503 const char (*names)[8];
13504
13505 if (!ins->need_vex)
13506 return true;
13507
13508 if (ins->evex_type == evex_from_legacy)
13509 {
13510 ins->evex_used |= EVEX_b_used;
13511 if (!ins->vex.nd)
13512 return true;
13513 }
13514
13515 reg = ins->vex.register_specifier;
13516 ins->vex.register_specifier = 0;
13517 if (ins->address_mode != mode_64bit)
13518 {
13519 if (ins->vex.evex && !ins->vex.v)
13520 {
13521 oappend (ins, "(bad)");
13522 return true;
13523 }
13524
13525 reg &= 7;
13526 }
13527 else if (ins->vex.evex && !ins->vex.v)
13528 reg += 16;
13529
13530 switch (bytemode)
13531 {
13532 case scalar_mode:
13533 oappend_register (ins, att_names_xmm[reg]);
13534 return true;
13535
13536 case vex_vsib_d_w_dq_mode:
13537 case vex_vsib_q_w_dq_mode:
13538 /* This must be the 3rd operand. */
13539 if (ins->obufp != ins->op_out[2])
13540 abort ();
13541 if (ins->vex.length == 128
13542 || (bytemode != vex_vsib_d_w_dq_mode
13543 && !ins->vex.w))
13544 oappend_register (ins, att_names_xmm[reg]);
13545 else
13546 oappend_register (ins, att_names_ymm[reg]);
13547
13548 /* All 3 XMM/YMM registers must be distinct. */
13549 modrm_reg = ins->modrm.reg;
13550 if (ins->rex & REX_R)
13551 modrm_reg += 8;
13552
13553 if (ins->has_sib && ins->modrm.rm == 4)
13554 {
13555 sib_index = ins->sib.index;
13556 if (ins->rex & REX_X)
13557 sib_index += 8;
13558 }
13559
13560 if (reg == modrm_reg || reg == sib_index)
13561 strcpy (ins->obufp, "/(bad)");
13562 if (modrm_reg == sib_index || modrm_reg == reg)
13563 strcat (ins->op_out[0], "/(bad)");
13564 if (sib_index == modrm_reg || sib_index == reg)
13565 strcat (ins->op_out[1], "/(bad)");
13566
13567 return true;
13568
13569 case tmm_mode:
13570 /* All 3 TMM registers must be distinct. */
13571 if (reg >= 8)
13572 oappend (ins, "(bad)");
13573 else
13574 {
13575 /* This must be the 3rd operand. */
13576 if (ins->obufp != ins->op_out[2])
13577 abort ();
13578 oappend_register (ins, att_names_tmm[reg]);
13579 if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13580 strcpy (ins->obufp, "/(bad)");
13581 }
13582
13583 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13584 || ins->modrm.rm == reg)
13585 {
13586 if (ins->modrm.reg <= 8
13587 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13588 strcat (ins->op_out[0], "/(bad)");
13589 if (ins->modrm.rm <= 8
13590 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13591 strcat (ins->op_out[1], "/(bad)");
13592 }
13593
13594 return true;
13595 }
13596
13597 switch (ins->vex.length)
13598 {
13599 case 128:
13600 switch (bytemode)
13601 {
13602 case x_mode:
13603 names = att_names_xmm;
13604 ins->evex_used |= EVEX_len_used;
13605 break;
13606 case v_mode:
13607 case dq_mode:
13608 if (ins->rex & REX_W)
13609 names = att_names64;
13610 else if (bytemode == v_mode
13611 && !(sizeflag & DFLAG))
13612 names = att_names16;
13613 else
13614 names = att_names32;
13615 break;
13616 case b_mode:
13617 names = att_names8rex;
13618 break;
13619 case q_mode:
13620 names = att_names64;
13621 break;
13622 case mask_bd_mode:
13623 case mask_mode:
13624 if (reg > 0x7)
13625 {
13626 oappend (ins, "(bad)");
13627 return true;
13628 }
13629 names = att_names_mask;
13630 break;
13631 default:
13632 abort ();
13633 return true;
13634 }
13635 break;
13636 case 256:
13637 switch (bytemode)
13638 {
13639 case x_mode:
13640 names = att_names_ymm;
13641 ins->evex_used |= EVEX_len_used;
13642 break;
13643 case mask_bd_mode:
13644 case mask_mode:
13645 if (reg <= 0x7)
13646 {
13647 names = att_names_mask;
13648 break;
13649 }
13650 /* Fall through. */
13651 default:
13652 /* See PR binutils/20893 for a reproducer. */
13653 oappend (ins, "(bad)");
13654 return true;
13655 }
13656 break;
13657 case 512:
13658 names = att_names_zmm;
13659 ins->evex_used |= EVEX_len_used;
13660 break;
13661 default:
13662 abort ();
13663 break;
13664 }
13665 oappend_register (ins, names[reg]);
13666 return true;
13667 }
13668
13669 static bool
13670 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13671 {
13672 if (ins->modrm.mod == 3)
13673 return OP_VEX (ins, bytemode, sizeflag);
13674 return true;
13675 }
13676
13677 static bool
13678 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13679 {
13680 OP_VEX (ins, bytemode, sizeflag);
13681
13682 if (ins->vex.w)
13683 {
13684 /* Swap 2nd and 3rd operands. */
13685 char *tmp = ins->op_out[2];
13686
13687 ins->op_out[2] = ins->op_out[1];
13688 ins->op_out[1] = tmp;
13689 }
13690 return true;
13691 }
13692
13693 static bool
13694 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13695 {
13696 int reg;
13697 const char (*names)[8] = att_names_xmm;
13698
13699 if (!fetch_code (ins->info, ins->codep + 1))
13700 return false;
13701 reg = *ins->codep++;
13702
13703 if (bytemode != x_mode && bytemode != scalar_mode)
13704 abort ();
13705
13706 reg >>= 4;
13707 if (ins->address_mode != mode_64bit)
13708 reg &= 7;
13709
13710 if (bytemode == x_mode && ins->vex.length == 256)
13711 names = att_names_ymm;
13712
13713 oappend_register (ins, names[reg]);
13714
13715 if (ins->vex.w)
13716 {
13717 /* Swap 3rd and 4th operands. */
13718 char *tmp = ins->op_out[3];
13719
13720 ins->op_out[3] = ins->op_out[2];
13721 ins->op_out[2] = tmp;
13722 }
13723 return true;
13724 }
13725
13726 static bool
13727 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13728 int sizeflag ATTRIBUTE_UNUSED)
13729 {
13730 oappend_immediate (ins, ins->codep[-1] & 0xf);
13731 return true;
13732 }
13733
13734 static bool
13735 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13736 int sizeflag ATTRIBUTE_UNUSED)
13737 {
13738 unsigned int cmp_type;
13739
13740 if (!ins->vex.evex)
13741 abort ();
13742
13743 if (!fetch_code (ins->info, ins->codep + 1))
13744 return false;
13745 cmp_type = *ins->codep++;
13746 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13747 If it's the case, print suffix, otherwise - print the immediate. */
13748 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13749 && cmp_type != 3
13750 && cmp_type != 7)
13751 {
13752 char suffix[3];
13753 char *p = ins->mnemonicendp - 2;
13754
13755 /* vpcmp* can have both one- and two-lettered suffix. */
13756 if (p[0] == 'p')
13757 {
13758 p++;
13759 suffix[0] = p[0];
13760 suffix[1] = '\0';
13761 }
13762 else
13763 {
13764 suffix[0] = p[0];
13765 suffix[1] = p[1];
13766 suffix[2] = '\0';
13767 }
13768
13769 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13770 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13771 }
13772 else
13773 {
13774 /* We have a reserved extension byte. Output it directly. */
13775 oappend_immediate (ins, cmp_type);
13776 }
13777 return true;
13778 }
13779
13780 static const struct op xop_cmp_op[] =
13781 {
13782 { STRING_COMMA_LEN ("lt") },
13783 { STRING_COMMA_LEN ("le") },
13784 { STRING_COMMA_LEN ("gt") },
13785 { STRING_COMMA_LEN ("ge") },
13786 { STRING_COMMA_LEN ("eq") },
13787 { STRING_COMMA_LEN ("neq") },
13788 { STRING_COMMA_LEN ("false") },
13789 { STRING_COMMA_LEN ("true") }
13790 };
13791
13792 static bool
13793 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13794 int sizeflag ATTRIBUTE_UNUSED)
13795 {
13796 unsigned int cmp_type;
13797
13798 if (!fetch_code (ins->info, ins->codep + 1))
13799 return false;
13800 cmp_type = *ins->codep++;
13801 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13802 {
13803 char suffix[3];
13804 char *p = ins->mnemonicendp - 2;
13805
13806 /* vpcom* can have both one- and two-lettered suffix. */
13807 if (p[0] == 'm')
13808 {
13809 p++;
13810 suffix[0] = p[0];
13811 suffix[1] = '\0';
13812 }
13813 else
13814 {
13815 suffix[0] = p[0];
13816 suffix[1] = p[1];
13817 suffix[2] = '\0';
13818 }
13819
13820 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13821 ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13822 }
13823 else
13824 {
13825 /* We have a reserved extension byte. Output it directly. */
13826 oappend_immediate (ins, cmp_type);
13827 }
13828 return true;
13829 }
13830
13831 static const struct op pclmul_op[] =
13832 {
13833 { STRING_COMMA_LEN ("lql") },
13834 { STRING_COMMA_LEN ("hql") },
13835 { STRING_COMMA_LEN ("lqh") },
13836 { STRING_COMMA_LEN ("hqh") }
13837 };
13838
13839 static bool
13840 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13841 int sizeflag ATTRIBUTE_UNUSED)
13842 {
13843 unsigned int pclmul_type;
13844
13845 if (!fetch_code (ins->info, ins->codep + 1))
13846 return false;
13847 pclmul_type = *ins->codep++;
13848 switch (pclmul_type)
13849 {
13850 case 0x10:
13851 pclmul_type = 2;
13852 break;
13853 case 0x11:
13854 pclmul_type = 3;
13855 break;
13856 default:
13857 break;
13858 }
13859 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13860 {
13861 char suffix[4];
13862 char *p = ins->mnemonicendp - 3;
13863 suffix[0] = p[0];
13864 suffix[1] = p[1];
13865 suffix[2] = p[2];
13866 suffix[3] = '\0';
13867 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13868 ins->mnemonicendp += pclmul_op[pclmul_type].len;
13869 }
13870 else
13871 {
13872 /* We have a reserved extension byte. Output it directly. */
13873 oappend_immediate (ins, pclmul_type);
13874 }
13875 return true;
13876 }
13877
13878 static bool
13879 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13880 {
13881 /* Add proper suffix to "movsxd". */
13882 char *p = ins->mnemonicendp;
13883
13884 switch (bytemode)
13885 {
13886 case movsxd_mode:
13887 if (!ins->intel_syntax)
13888 {
13889 USED_REX (REX_W);
13890 if (ins->rex & REX_W)
13891 {
13892 *p++ = 'l';
13893 *p++ = 'q';
13894 break;
13895 }
13896 }
13897
13898 *p++ = 'x';
13899 *p++ = 'd';
13900 break;
13901 default:
13902 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13903 break;
13904 }
13905
13906 ins->mnemonicendp = p;
13907 *p = '\0';
13908 return OP_E (ins, bytemode, sizeflag);
13909 }
13910
13911 static bool
13912 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13913 {
13914 unsigned int reg = ins->vex.register_specifier;
13915 unsigned int modrm_reg = ins->modrm.reg;
13916 unsigned int modrm_rm = ins->modrm.rm;
13917
13918 /* Calc destination register number. */
13919 if (ins->rex & REX_R)
13920 modrm_reg += 8;
13921 if (ins->rex2 & REX_R)
13922 modrm_reg += 16;
13923
13924 /* Calc src1 register number. */
13925 if (ins->address_mode != mode_64bit)
13926 reg &= 7;
13927 else if (ins->vex.evex && !ins->vex.v)
13928 reg += 16;
13929
13930 /* Calc src2 register number. */
13931 if (ins->modrm.mod == 3)
13932 {
13933 if (ins->rex & REX_B)
13934 modrm_rm += 8;
13935 if (ins->rex & REX_X)
13936 modrm_rm += 16;
13937 }
13938
13939 /* Destination and source registers must be distinct, output bad if
13940 dest == src1 or dest == src2. */
13941 if (modrm_reg == reg
13942 || (ins->modrm.mod == 3
13943 && modrm_reg == modrm_rm))
13944 {
13945 oappend (ins, "(bad)");
13946 return true;
13947 }
13948 return OP_XMM (ins, bytemode, sizeflag);
13949 }
13950
13951 static bool
13952 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13953 {
13954 if (ins->modrm.mod != 3 || !ins->vex.b)
13955 return true;
13956
13957 switch (bytemode)
13958 {
13959 case evex_rounding_64_mode:
13960 if (ins->address_mode != mode_64bit || !ins->vex.w)
13961 return true;
13962 /* Fall through. */
13963 case evex_rounding_mode:
13964 ins->evex_used |= EVEX_b_used;
13965 oappend (ins, names_rounding[ins->vex.ll]);
13966 break;
13967 case evex_sae_mode:
13968 ins->evex_used |= EVEX_b_used;
13969 oappend (ins, "{");
13970 break;
13971 default:
13972 abort ();
13973 }
13974 oappend (ins, "sae}");
13975 return true;
13976 }
13977
13978 static bool
13979 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
13980 {
13981 if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
13982 {
13983 if (ins->intel_syntax)
13984 {
13985 ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
13986 }
13987 else
13988 {
13989 USED_REX (REX_W);
13990 if (ins->rex & REX_W)
13991 ins->mnemonicendp = stpcpy (ins->obuf, "nopq ");
13992 else
13993 {
13994 if (sizeflag & DFLAG)
13995 ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
13996 else
13997 ins->mnemonicendp = stpcpy (ins->obuf, "nopw ");
13998 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13999 }
14000 }
14001 bytemode = v_mode;
14002 }
14003
14004 return OP_M (ins, bytemode, sizeflag);
14005 }
14006
14007 static bool
14008 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
14009 {
14010 if (ins->modrm.mod != 3)
14011 return true;
14012
14013 unsigned int vvvv_reg = ins->vex.register_specifier
14014 | (!ins->vex.v << 4);
14015 unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
14016 + (ins->rex2 & REX_B ? 16 : 0);
14017
14018 /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */
14019 if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
14020 || (!ins->modrm.reg
14021 && vvvv_reg == rm_reg))
14022 {
14023 oappend (ins, "(bad)");
14024 return true;
14025 }
14026
14027 return OP_VEX (ins, bytemode, sizeflag);
14028 }
14029
14030 static bool
14031 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
14032 {
14033 if (ins->last_rex2_prefix >= 0)
14034 {
14035 uint64_t op;
14036
14037 if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
14038 || (ins->rex & REX_W) != 0x0)
14039 {
14040 oappend (ins, "(bad)");
14041 return true;
14042 }
14043
14044 if (bytemode == eAX_reg)
14045 return true;
14046
14047 if (!get64 (ins, &op))
14048 return false;
14049
14050 ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
14051 ins->rex2 |= REX2_SPECIAL;
14052 oappend_immediate (ins, op);
14053
14054 return true;
14055 }
14056
14057 if (bytemode == eAX_reg)
14058 return OP_IMREG (ins, bytemode, sizeflag);
14059 return OP_OFF64 (ins, bytemode, sizeflag);
14060 }
14061
14062 static bool
14063 CFCMOV_Fixup (instr_info *ins, int opnd, int sizeflag)
14064 {
14065 /* EVEX.NF is used as a direction bit in the 2-operand case to reverse the
14066 source and destination operands. */
14067 bool dstmem = !ins->vex.nd && ins->vex.nf;
14068
14069 if (opnd == 0)
14070 {
14071 if (dstmem)
14072 return OP_E (ins, v_swap_mode, sizeflag);
14073 return OP_G (ins, v_mode, sizeflag);
14074 }
14075
14076 /* These bits have been consumed and should be cleared. */
14077 ins->vex.nf = false;
14078 ins->vex.mask_register_specifier = 0;
14079
14080 if (dstmem)
14081 return OP_G (ins, v_mode, sizeflag);
14082 return OP_E (ins, v_mode, sizeflag);
14083 }
The GNU Binutils are a collection of binary tools.