| blob | 418458c366572ce9696b5b010998e8fca64f51e3 |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
32 /* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34 #define RELOC_SECTION(HTAB, NAME) \
37 /* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39 #define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
44 /* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46 #define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
51 /* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53 #define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
58 #define elf_info_to_howto NULL
59 #define elf_info_to_howto_rel elf32_arm_info_to_howto
61 #define ARM_ELF_ABI_VERSION 0
62 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64 /* The Adjusted Place, as defined by AAELF. */
65 #define Pa(X) ((X) & 0xfffffffc)
72 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
73 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
74 in that slot. */
77 {
78 /* No relocation. */
107 /* 32 bit absolute */
122 /* standard 32bit pc-relative reloc */
137 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
152 /* 16 bit absolute */
167 /* 12 bit absolute */
196 /* 8 bit absolute */
295 /* BLX instruction for the ARM. */
310 /* BLX instruction for the Thumb. */
325 /* Dynamic TLS relocations. */
369 /* Relocs used in ARM Linux */
833 /* These are declared as 13-bit signed relocations because we can
834 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
835 versa. */
892 /* Group relocations. */
1272 /* End of group relocations. */
1486 /* GNU extension to record C++ vtable member usage */
1501 /* GNU extension to record C++ vtable hierarchy */
1544 /* TLS relocations */
1657 /* 112-127 private relocations. */
1675 /* R_ARM_ME_TOO, obsolete. */
1745 /* Relocations for Armv8.1-M Mainline. */
1785 };
1787 /* 160 onwards: */
1789 {
1894 };
1896 /* 249-255 extended, currently unused, relocations: */
1898 {
1954 };
1958 {
1971 }
1973 static bfd_boolean
1976 {
1981 {
1982 /* xgettext:c-format */
1987 }
1989 }
1991 struct elf32_arm_reloc_map
1992 {
1993 bfd_reloc_code_real_type bfd_reloc_val;
1995 };
1997 /* All entries in this list must also be present in elf32_arm_howto_table. */
1999 {
2100 };
2104 bfd_reloc_code_real_type code)
2105 {
2113 }
2118 {
2137 }
2139 /* Support for core dump NOTE sections. */
2141 static bfd_boolean
2143 {
2148 {
2153 /* pr_cursig */
2156 /* pr_pid */
2159 /* pr_reg */
2164 }
2166 /* Make a ".reg/999" section. */
2169 }
2171 static bfd_boolean
2173 {
2175 {
2186 }
2188 /* Note that for some reason, a spurious space is tacked
2189 onto the end of the args in some (at least one anyway)
2190 implementations, so strip it off if it exists. */
2191 {
2197 }
2200 }
2205 {
2207 {
2212 {
2219 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2220 DIAGNOSTIC_PUSH;
2221 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2222 -Wstringop-truncation:
2223 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2224 */
2225 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2226 #endif
2228 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2229 DIAGNOSTIC_POP;
2230 #endif
2235 }
2238 {
2257 }
2258 }
2259 }
2261 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2263 #define TARGET_BIG_SYM arm_elf32_be_vec
2266 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2267 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2268 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2273 /* In lieu of proper flags, assume all EABIv4 or later objects are
2274 interworkable. */
2275 #define INTERWORK_FLAG(abfd) \
2276 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2277 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2278 || ((abfd)->flags & BFD_LINKER_CREATED))
2280 /* The linker script knows the section names for placement.
2281 The entry_names are used to do simple name mangling on the stubs.
2282 Given a function name, and its type, the stub can be found. The
2283 name can be changed. The only requirement is the %s be present. */
2303 /* The name of the dynamic interpreter. This is put in the .interp
2304 section. */
2307 /* FDPIC default stack size. */
2308 #define DEFAULT_STACK_SIZE 0x8000
2311 {
2315 };
2318 {
2326 + dl_tlsdesc_lazy_resolver(GOT) */
2328 };
2330 /* ARM FDPIC PLT entry. */
2331 /* The last 5 words contain PLT lazy fragment code and data. */
2333 {
2344 };
2346 /* Thumb FDPIC PLT entry. */
2347 /* The last 5 words contain PLT lazy fragment code and data. */
2349 {
2360 };
2362 #ifdef FOUR_WORD_PLT
2364 /* The first entry in a procedure linkage table looks like
2365 this. It is set up so that any shared library function that is
2366 called before the relocation has been set up calls the dynamic
2367 linker first. */
2369 {
2374 };
2376 /* Subsequent entries in a procedure linkage table look like
2377 this. */
2379 {
2384 };
2388 /* The first entry in a procedure linkage table looks like
2389 this. It is set up so that any shared library function that is
2390 called before the relocation has been set up calls the dynamic
2391 linker first. */
2393 {
2399 };
2401 /* By default subsequent entries in a procedure linkage table look like
2402 this. Offsets that don't fit into 28 bits will cause link error. */
2404 {
2408 };
2410 /* When explicitly asked, we'll use this "long" entry format
2411 which can cope with arbitrary displacements. */
2413 {
2418 };
2424 /* The first entry in a procedure linkage table looks like this.
2425 It is set up so that any shared library function that is called before the
2426 relocation has been set up calls the dynamic linker first. */
2428 {
2429 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2430 an instruction maybe encoded to one or two array elements. */
2433 /* add lr, pc */
2436 };
2438 /* Subsequent entries in a procedure linkage table for thumb only target
2439 look like this. */
2441 {
2442 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2443 an instruction maybe encoded to one or two array elements. */
2448 /* nop */
2449 };
2451 /* The format of the first entry in the procedure linkage table
2452 for a VxWorks executable. */
2454 {
2459 };
2461 /* The format of subsequent entries in a VxWorks executable. */
2463 {
2470 };
2472 /* The format of entries in a VxWorks shared library. */
2474 {
2481 };
2483 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2484 #define PLT_THUMB_STUB_SIZE 4
2486 {
2489 };
2491 /* The entries in a PLT when using a DLL-based target with multiple
2492 address spaces. */
2494 {
2497 };
2499 /* The first entry in a procedure linkage table looks like
2500 this. It is set up so that any shared library function that is
2501 called before the relocation has been set up calls the dynamic
2502 linker first. */
2504 {
2505 /* First bundle: */
2510 /* Second bundle: */
2515 /* Third bundle: */
2519 /* .Lplt_tail: */
2521 /* Fourth bundle: */
2526 };
2527 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2529 /* Subsequent entries in a procedure linkage table look like this. */
2531 {
2536 };
2538 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2539 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2540 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2541 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2542 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2543 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2544 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2545 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2547 enum stub_insn_type
2548 {
2550 THUMB32_TYPE,
2551 ARM_TYPE,
2552 DATA_TYPE
2553 };
2555 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2556 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2557 is inserted in arm_build_one_stub(). */
2558 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2559 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2560 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2561 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2562 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2563 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2564 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2565 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2568 {
2569 bfd_vma data;
2575 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2576 to reach the stub if necessary. */
2578 {
2581 };
2583 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2584 available. */
2586 {
2590 };
2592 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2594 {
2602 };
2604 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2606 {
2609 };
2611 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2612 M-profile architectures. */
2614 {
2618 };
2620 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2621 allowed. */
2623 {
2629 };
2631 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2632 available. */
2634 {
2639 };
2641 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2642 one, when the destination is close enough. */
2644 {
2648 };
2650 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2651 blx to reach the stub if necessary. */
2653 {
2657 };
2659 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2660 blx to reach the stub if necessary. We can not add into pc;
2661 it is not guaranteed to mode switch (different in ARMv6 and
2662 ARMv7). */
2664 {
2669 };
2671 /* V4T ARM -> ARM long branch stub, PIC. */
2673 {
2678 };
2680 /* V4T Thumb -> ARM long branch stub, PIC. */
2682 {
2688 };
2690 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2691 architectures. */
2693 {
2701 };
2703 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2704 allowed. */
2706 {
2713 };
2715 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2716 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2718 {
2722 };
2724 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2725 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2727 {
2733 };
2735 /* NaCl ARM -> ARM long branch stub. */
2737 {
2746 };
2748 /* NaCl ARM -> ARM long branch stub, PIC. */
2750 {
2759 };
2761 /* Stub used for transition to secure state (aka SG veneer). */
2763 {
2766 };
2769 /* Cortex-A8 erratum-workaround stubs. */
2771 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2772 can't use a conditional branch to reach this stub). */
2775 {
2779 };
2781 /* Stub used for b.w and bl.w instructions. */
2784 {
2786 };
2789 {
2791 };
2793 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2794 instruction (which switches to ARM mode) to point to this stub. Jump to the
2795 real destination using an ARM-mode branch. */
2798 {
2800 };
2802 /* For each section group there can be a specially created linker section
2803 to hold the stubs for that group. The name of the stub section is based
2804 upon the name of another section within that group with the suffix below
2805 applied.
2807 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2808 create what appeared to be a linker stub section when it actually
2809 contained user code/data. For example, consider this fragment:
2811 const char * stubborn_problems[] = { "np" };
2813 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2814 section called:
2816 .data.rel.local.stubborn_problems
2818 This then causes problems in arm32_arm_build_stubs() as it triggers:
2820 // Ignore non-stub sections.
2821 if (!strstr (stub_sec->name, STUB_SUFFIX))
2822 continue;
2824 And so the section would be ignored instead of being processed. Hence
2825 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2826 C identifier. */
2829 /* One entry per long/short branch stub defined above. */
2830 #define DEF_STUBS \
2831 DEF_STUB(long_branch_any_any) \
2832 DEF_STUB(long_branch_v4t_arm_thumb) \
2833 DEF_STUB(long_branch_thumb_only) \
2834 DEF_STUB(long_branch_v4t_thumb_thumb) \
2835 DEF_STUB(long_branch_v4t_thumb_arm) \
2836 DEF_STUB(short_branch_v4t_thumb_arm) \
2837 DEF_STUB(long_branch_any_arm_pic) \
2838 DEF_STUB(long_branch_any_thumb_pic) \
2839 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2840 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2841 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2842 DEF_STUB(long_branch_thumb_only_pic) \
2843 DEF_STUB(long_branch_any_tls_pic) \
2844 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2845 DEF_STUB(long_branch_arm_nacl) \
2846 DEF_STUB(long_branch_arm_nacl_pic) \
2847 DEF_STUB(cmse_branch_thumb_only) \
2848 DEF_STUB(a8_veneer_b_cond) \
2849 DEF_STUB(a8_veneer_b) \
2850 DEF_STUB(a8_veneer_bl) \
2851 DEF_STUB(a8_veneer_blx) \
2852 DEF_STUB(long_branch_thumb2_only) \
2853 DEF_STUB(long_branch_thumb2_only_pure)
2855 #define DEF_STUB(x) arm_stub_##x,
2856 enum elf32_arm_stub_type
2857 {
2858 arm_stub_none,
2859 DEF_STUBS
2860 max_stub_type
2861 };
2862 #undef DEF_STUB
2864 /* Note the first a8_veneer type. */
2868 {
2873 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2875 {
2877 DEF_STUBS
2878 };
2880 struct elf32_arm_stub_hash_entry
2881 {
2882 /* Base hash table entry structure. */
2885 /* The stub section. */
2888 /* Offset within stub_sec of the beginning of this stub. */
2889 bfd_vma stub_offset;
2891 /* Given the symbol's value and its section we can determine its final
2892 value when building the stubs (so the stub knows where to jump). */
2893 bfd_vma target_value;
2896 /* Same as above but for the source of the branch to the stub. Used for
2897 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2898 such, source section does not need to be recorded since Cortex-A8 erratum
2899 workaround stubs are only generated when both source and target are in the
2900 same section. */
2901 bfd_vma source_value;
2903 /* The instruction which caused this stub to be generated (only valid for
2904 Cortex-A8 erratum workaround stubs at present). */
2907 /* The stub type. */
2909 /* Its encoding size in bytes. */
2911 /* Its template. */
2913 /* The size of the template (number of entries). */
2916 /* The symbol table entry, if any, that this was derived from. */
2919 /* Type of branch. */
2922 /* Where this stub is being called from, or, in the case of combined
2923 stub sections, the first input section in the group. */
2926 /* The name for the local symbol at the start of this stub. The
2927 stub name in the hash table has to be unique; this does not, so
2928 it can be friendlier. */
2930 };
2932 /* Used to build a map of a section. This is required for mixed-endian
2933 code/data. */
2936 {
2937 bfd_vma vma;
2939 }
2940 elf32_arm_section_map;
2942 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2945 {
2946 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2947 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2948 VFP11_ERRATUM_ARM_VENEER,
2949 VFP11_ERRATUM_THUMB_VENEER
2950 }
2951 elf32_vfp11_erratum_type;
2954 {
2956 bfd_vma vma;
2957 union
2958 {
2959 struct
2960 {
2964 struct
2965 {
2970 elf32_vfp11_erratum_type type;
2971 }
2972 elf32_vfp11_erratum_list;
2974 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2975 veneer. */
2977 {
2978 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2979 STM32L4XX_ERRATUM_VENEER
2980 }
2981 elf32_stm32l4xx_erratum_type;
2984 {
2986 bfd_vma vma;
2987 union
2988 {
2989 struct
2990 {
2994 struct
2995 {
3000 elf32_stm32l4xx_erratum_type type;
3001 }
3002 elf32_stm32l4xx_erratum_list;
3005 {
3006 DELETE_EXIDX_ENTRY,
3007 INSERT_EXIDX_CANTUNWIND_AT_END
3008 }
3009 arm_unwind_edit_type;
3011 /* A (sorted) list of edits to apply to an unwind table. */
3013 {
3014 arm_unwind_edit_type type;
3015 /* Note: we sometimes want to insert an unwind entry corresponding to a
3016 section different from the one we're currently writing out, so record the
3017 (text) section this edit relates to here. */
3021 }
3022 arm_unwind_table_edit;
3025 {
3026 /* Information about mapping symbols. */
3031 /* Information about CPU errata. */
3037 /* Information about unwind tables. */
3038 union
3039 {
3040 /* Unwind info attached to a text section. */
3041 struct
3042 {
3046 /* Unwind info attached to an .ARM.exidx section. */
3047 struct
3048 {
3053 }
3054 _arm_elf_section_data;
3056 #define elf32_arm_section_data(sec) \
3057 ((_arm_elf_section_data *) elf_section_data (sec))
3059 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3060 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3061 so may be created multiple times: we use an array of these entries whilst
3062 relaxing which we can refresh easily, then create stubs for each potentially
3063 erratum-triggering instruction once we've settled on a solution. */
3065 struct a8_erratum_fix
3066 {
3069 bfd_vma offset;
3070 bfd_vma target_offset;
3075 };
3077 /* A table of relocs applied to branches which might trigger Cortex-A8
3078 erratum. */
3080 struct a8_erratum_reloc
3081 {
3082 bfd_vma from;
3083 bfd_vma destination;
3088 bfd_boolean non_a8_stub;
3089 };
3091 /* The size of the thread control block. */
3092 #define TCB_SIZE 8
3094 /* ARM-specific information about a PLT entry, over and above the usual
3095 gotplt_union. */
3096 struct arm_plt_info
3097 {
3098 /* We reference count Thumb references to a PLT entry separately,
3099 so that we can emit the Thumb trampoline only if needed. */
3100 bfd_signed_vma thumb_refcount;
3102 /* Some references from Thumb code may be eliminated by BL->BLX
3103 conversion, so record them separately. */
3104 bfd_signed_vma maybe_thumb_refcount;
3106 /* How many of the recorded PLT accesses were from non-call relocations.
3107 This information is useful when deciding whether anything takes the
3108 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3109 non-call references to the function should resolve directly to the
3110 real runtime target. */
3113 /* Since PLT entries have variable size if the Thumb prologue is
3114 used, we need to record the index into .got.plt instead of
3115 recomputing it from the PLT offset. */
3116 bfd_signed_vma got_offset;
3117 };
3119 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3120 struct arm_local_iplt_info
3121 {
3122 /* The information that is usually found in the generic ELF part of
3123 the hash table entry. */
3126 /* The information that is usually found in the ARM-specific part of
3127 the hash table entry. */
3130 /* A list of all potential dynamic relocations against this symbol. */
3132 };
3134 /* Structure to handle FDPIC support for local functions. */
3139 };
3141 struct elf_arm_obj_tdata
3142 {
3145 /* tls_type for each local got entry. */
3148 /* GOTPLT entries for TLS descriptors. */
3151 /* Information for local symbols that need entries in .iplt. */
3154 /* Zero to warn when linking objects with incompatible enum sizes. */
3157 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3160 /* Maintains FDPIC counters and funcdesc info. */
3162 };
3164 #define elf_arm_tdata(bfd) \
3165 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3167 #define elf32_arm_local_got_tls_type(bfd) \
3168 (elf_arm_tdata (bfd)->local_got_tls_type)
3170 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3171 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3173 #define elf32_arm_local_iplt(bfd) \
3174 (elf_arm_tdata (bfd)->local_iplt)
3176 #define elf32_arm_local_fdpic_cnts(bfd) \
3177 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3179 #define is_arm_elf(bfd) \
3180 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3181 && elf_tdata (bfd) != NULL \
3182 && elf_object_id (bfd) == ARM_ELF_DATA)
3184 static bfd_boolean
3186 {
3188 ARM_ELF_DATA);
3189 }
3191 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3193 /* Structure to handle FDPIC support for extern functions. */
3200 };
3202 /* Arm ELF linker hash entry. */
3203 struct elf32_arm_link_hash_entry
3204 {
3207 /* Track dynamic relocs copied for this symbol. */
3210 /* ARM-specific PLT information. */
3213 #define GOT_UNKNOWN 0
3214 #define GOT_NORMAL 1
3215 #define GOT_TLS_GD 2
3216 #define GOT_TLS_IE 4
3217 #define GOT_TLS_GDESC 8
3218 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3221 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3226 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3227 starting at the end of the jump table. */
3228 bfd_vma tlsdesc_got;
3230 /* The symbol marking the real symbol location for exported thumb
3231 symbols with Arm stubs. */
3234 /* A pointer to the most recently used stub hash entry against this
3235 symbol. */
3238 /* Counter for FDPIC relocations against this symbol. */
3240 };
3242 /* Traverse an arm ELF linker hash table. */
3243 #define elf32_arm_link_hash_traverse(table, func, info) \
3244 (elf_link_hash_traverse \
3245 (&(table)->root, \
3246 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
3247 (info)))
3249 /* Get the ARM elf linker hash table from a link_info structure. */
3250 #define elf32_arm_hash_table(info) \
3251 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3252 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
3254 #define arm_stub_hash_lookup(table, string, create, copy) \
3255 ((struct elf32_arm_stub_hash_entry *) \
3256 bfd_hash_lookup ((table), (string), (create), (copy)))
3258 /* Array to keep track of which stub sections have been created, and
3259 information on stub grouping. */
3260 struct map_stub
3261 {
3262 /* This is the section to which stubs in the group will be
3263 attached. */
3265 /* The stub section. */
3267 };
3269 #define elf32_arm_compute_jump_table_size(htab) \
3270 ((htab)->next_tls_desc_index * 4)
3272 /* ARM ELF linker hash table. */
3273 struct elf32_arm_link_hash_table
3274 {
3275 /* The main hash table. */
3278 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3279 bfd_size_type thumb_glue_size;
3281 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3282 bfd_size_type arm_glue_size;
3284 /* The size in bytes of section containing the ARMv4 BX veneers. */
3285 bfd_size_type bx_glue_size;
3287 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3288 veneer has been populated. */
3291 /* The size in bytes of the section containing glue for VFP11 erratum
3292 veneers. */
3293 bfd_size_type vfp11_erratum_glue_size;
3295 /* The size in bytes of the section containing glue for STM32L4XX erratum
3296 veneers. */
3297 bfd_size_type stm32l4xx_erratum_glue_size;
3299 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3300 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3301 elf32_arm_write_section(). */
3305 /* An arbitrary input BFD chosen to hold the glue sections. */
3308 /* Nonzero to output a BE8 image. */
3311 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3312 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3315 /* The relocation to use for R_ARM_TARGET2 relocations. */
3318 /* 0 = Ignore R_ARM_V4BX.
3319 1 = Convert BX to MOV PC.
3320 2 = Generate v4 interworing stubs. */
3323 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3326 /* Whether we should fix the ARM1176 BLX immediate issue. */
3329 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3332 /* What sort of code sequences we should look for which may trigger the
3333 VFP11 denorm erratum. */
3334 bfd_arm_vfp11_fix vfp11_fix;
3336 /* Global counter for the number of fixes we have emitted. */
3339 /* What sort of code sequences we should look for which may trigger the
3340 STM32L4XX erratum. */
3341 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3343 /* Global counter for the number of fixes we have emitted. */
3346 /* Nonzero to force PIC branch veneers. */
3349 /* The number of bytes in the initial entry in the PLT. */
3350 bfd_size_type plt_header_size;
3352 /* The number of bytes in the subsequent PLT etries. */
3353 bfd_size_type plt_entry_size;
3355 /* True if the target system is VxWorks. */
3358 /* True if the target system is Symbian OS. */
3361 /* True if the target system is Native Client. */
3364 /* True if the target uses REL relocations. */
3365 bfd_boolean use_rel;
3367 /* Nonzero if import library must be a secure gateway import library
3368 as per ARMv8-M Security Extensions. */
3371 /* The import library whose symbols' address must remain stable in
3372 the import library generated. */
3375 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3376 bfd_vma next_tls_desc_index;
3378 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3379 bfd_vma num_tls_desc;
3381 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3384 /* The offset into splt of the PLT entry for the TLS descriptor
3385 resolver. Special values are 0, if not necessary (or not found
3386 to be necessary yet), and -1 if needed but not determined
3387 yet. */
3388 bfd_vma dt_tlsdesc_plt;
3390 /* The offset into sgot of the GOT entry used by the PLT entry
3391 above. */
3392 bfd_vma dt_tlsdesc_got;
3394 /* Offset in .plt section of tls_arm_trampoline. */
3395 bfd_vma tls_trampoline;
3397 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3398 union
3399 {
3400 bfd_signed_vma refcount;
3401 bfd_vma offset;
3404 /* Small local sym cache. */
3407 /* For convenience in allocate_dynrelocs. */
3410 /* The amount of space used by the reserved portion of the sgotplt
3411 section, plus whatever space is used by the jump slots. */
3412 bfd_vma sgotplt_jump_table_size;
3414 /* The stub hash table. */
3417 /* Linker stub bfd. */
3420 /* Linker call-backs. */
3425 /* Array to keep track of which stub sections have been created, and
3426 information on stub grouping. */
3429 /* Input stub section holding secure gateway veneers. */
3432 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3433 start to be allocated. */
3434 bfd_vma new_cmse_stub_offset;
3436 /* Number of elements in stub_group. */
3439 /* Assorted information used by elf32_arm_size_stubs. */
3444 /* True if the target system uses FDPIC. */
3447 /* Fixup section. Used for FDPIC. */
3449 };
3451 /* Add an FDPIC read-only fixup. */
3452 static void
3454 {
3455 bfd_vma fixup_offset;
3460 }
3464 {
3465 #if GCC_VERSION >= 3004
3467 #else
3471 {
3475 }
3477 #endif
3478 }
3482 {
3483 #if GCC_VERSION >= 3004
3485 #else
3490 {
3492 sum++;
3494 }
3496 #endif
3497 }
3502 static void
3508 bfd_vma addr,
3509 bfd_vma dynreloc_value,
3510 bfd_vma seg)
3511 {
3513 {
3518 {
3520 Elf_Internal_Rela outrel;
3529 }
3530 else
3531 {
3545 }
3547 }
3548 }
3550 /* Create an entry in an ARM ELF linker hash table. */
3556 {
3560 /* Allocate the structure if it has not already been allocated by a
3561 subclass. */
3568 /* Call the allocation method of the superclass. */
3573 {
3591 }
3594 }
3596 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3597 symbols. */
3599 static bfd_boolean
3601 {
3603 {
3604 bfd_size_type num_syms;
3605 bfd_size_type size;
3631 }
3633 }
3635 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3636 to input bfd ABFD. Create the information if it doesn't already exist.
3637 Return null if an allocation fails. */
3641 {
3652 }
3654 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3655 in ABFD's symbol table. If the symbol is global, H points to its
3656 hash table entry, otherwise H is null.
3658 Return true if the symbol does have PLT information. When returning
3659 true, point *ROOT_PLT at the target-independent reference count/offset
3660 union and *ARM_PLT at the ARM-specific information. */
3662 static bfd_boolean
3667 {
3674 {
3678 }
3690 }
3694 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3695 before it. */
3697 static bfd_boolean
3700 {
3707 }
3709 /* Return a pointer to the head of the dynamic reloc list that should
3710 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3711 ABFD's symbol table. Return null if an error occurs. */
3716 {
3718 {
3725 }
3726 else
3727 {
3728 /* Track dynamic relocs needed for local syms too.
3729 We really need local syms available to do this
3730 easily. Oh well. */
3740 }
3741 }
3743 /* Initialize an entry in the stub hash table. */
3749 {
3750 /* Allocate the structure if it has not already been allocated by a
3751 subclass. */
3753 {
3758 }
3760 /* Call the allocation method of the superclass. */
3763 {
3766 /* Initialize the local fields. */
3781 }
3784 }
3786 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3787 shortcuts to them in our hash table. */
3789 static bfd_boolean
3791 {
3798 /* BPABI objects never have a GOT, or associated sections. */
3805 /* Also create .rofixup. */
3807 {
3813 }
3816 }
3818 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3820 static bfd_boolean
3822 {
3827 flagword flags;
3835 {
3842 }
3845 {
3853 }
3856 {
3862 }
3864 }
3866 /* Determine if we're dealing with a Thumb only architecture. */
3868 static bfd_boolean
3870 {
3873 Tag_CPU_arch_profile);
3880 /* Force return logic to be reviewed for each new architecture. */
3892 }
3894 /* Determine if we're dealing with a Thumb-2 object. */
3896 static bfd_boolean
3898 {
3901 Tag_THUMB_ISA_use);
3908 /* Force return logic to be reviewed for each new architecture. */
3918 }
3920 /* Determine whether Thumb-2 BL instruction is available. */
3922 static bfd_boolean
3924 {
3928 /* Force return logic to be reviewed for each new architecture. */
3931 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3934 }
3936 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3937 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3938 hash table. */
3940 static bfd_boolean
3942 {
3956 {
3961 {
3963 htab->plt_entry_size
3965 }
3966 else
3967 {
3968 htab->plt_header_size
3970 htab->plt_entry_size
3972 }
3976 }
3977 else
3978 {
3979 /* PR ld/16017
3980 Test for thumb only architectures. Note - we cannot just call
3981 using_thumb_only() as the attributes in the output bfd have not been
3982 initialised at this point, so instead we use the input bfd. */
3987 {
3990 }
3992 }
3998 else
4000 }
4009 }
4011 /* Copy the extra info we tack onto an elf_link_hash_entry. */
4013 static void
4017 {
4024 {
4026 {
4030 /* Add reloc counts against the indirect sym to the direct sym
4031 list. Merge any entries against the same section. */
4033 {
4038 {
4043 }
4046 }
4048 }
4052 }
4055 {
4056 /* Copy over PLT info. */
4064 /* Copy FDPIC counters. */
4069 /* We should only allocate a function to .iplt once the final
4070 symbol information is known. */
4074 {
4077 }
4078 }
4081 }
4083 /* Destroy an ARM elf linker hash table. */
4085 static void
4087 {
4093 }
4095 /* Create an ARM elf linker hash table. */
4099 {
4108 elf32_arm_link_hash_newfunc,
4110 ARM_ELF_DATA))
4111 {
4114 }
4118 #ifdef FOUR_WORD_PLT
4121 #else
4124 #endif
4131 {
4134 }
4138 }
4140 /* Determine what kind of NOPs are available. */
4142 static bfd_boolean
4144 {
4146 Tag_CPU_arch);
4148 /* Force return logic to be reviewed for each new architecture. */
4156 }
4158 static bfd_boolean
4160 {
4162 {
4179 }
4180 }
4182 /* Determine the type of stub needed, if any, for a call. */
4184 static enum elf32_arm_stub_type
4191 bfd_vma destination,
4195 {
4196 bfd_vma location;
4197 bfd_signed_vma branch_offset;
4222 /* True for architectures that implement the thumb2 movw instruction. */
4225 /* Determine where the call point is. */
4232 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4233 are considering a function call relocation. */
4239 /* For TLS call relocs, it is the caller's responsibility to provide
4240 the address of the appropriate trampoline. */
4247 {
4252 else
4255 {
4258 /* Note when dealing with PLT entries: the main PLT stub is in
4259 ARM mode, so if the branch is in Thumb mode, another
4260 Thumb->ARM stub will be inserted later just before the ARM
4261 PLT stub. If a long branch stub is needed, we'll add a
4262 Thumb->Arm one and branch directly to the ARM PLT entry.
4263 Here, we have to check if a pre-PLT Thumb->ARM stub
4264 is needed and if it will be close enough. */
4271 /* Thumb branch/call to PLT: it can become a branch to ARM
4272 or to Thumb. We must perform the same checks and
4273 corrections as in elf32_arm_final_link_relocate. */
4276 {
4280 {
4281 /* If the Thumb BLX instruction is available, convert
4282 the BL to a BLX instruction to call the ARM-mode
4283 PLT entry. */
4285 }
4286 else
4287 {
4289 /* Target the Thumb stub before the ARM PLT entry. */
4292 }
4293 }
4294 else
4295 {
4297 }
4298 }
4299 }
4300 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4307 {
4308 /* Handle cases where:
4309 - this call goes too far (different Thumb/Thumb2 max
4310 distance)
4311 - it's a Thumb->Arm call and blx is not available, or it's a
4312 Thumb->Arm branch (not bl). A stub is needed in this case,
4313 but only if this call is not through a PLT entry. Indeed,
4314 PLT stubs handle mode switching already. */
4318 || (thumb2_bl
4321 || (thumb2
4331 {
4332 /* If we need to insert a Thumb-Thumb long branch stub to a
4333 PLT, use one that branches directly to the ARM PLT
4334 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4335 stub, undo this now. */
4337 {
4340 }
4343 {
4344 /* Thumb to thumb. */
4346 {
4348 _bfd_error_handler
4350 " section with SHF_ARM_PURECODE section"
4351 " attribute is only supported for M-profile"
4356 /* PIC stubs. */
4359 /* V5T and above. Stub starts with ARM code, so
4360 we must be able to switch mode before
4361 reaching it, which is only possible for 'bl'
4362 (ie R_ARM_THM_CALL relocation). */
4363 ? arm_stub_long_branch_any_thumb_pic
4364 /* On V4T, use Thumb code only. */
4367 /* non-PIC stubs. */
4370 /* V5T and above. */
4371 ? arm_stub_long_branch_any_any
4372 /* V4T. */
4374 }
4375 else
4376 {
4379 else
4380 {
4382 _bfd_error_handler
4384 " section with SHF_ARM_PURECODE section"
4385 " attribute is only supported for M-profile"
4390 /* PIC stub. */
4391 ? arm_stub_long_branch_thumb_only_pic
4392 /* non-PIC stub. */
4395 }
4396 }
4397 }
4398 else
4399 {
4401 _bfd_error_handler
4403 " section with SHF_ARM_PURECODE section"
4408 /* Thumb to arm. */
4412 {
4413 _bfd_error_handler
4417 }
4419 stub_type =
4421 /* PIC stubs. */
4423 /* TLS PIC stubs. */
4427 /* V5T PIC and above. */
4428 ? arm_stub_long_branch_any_arm_pic
4429 /* V4T PIC stub. */
4432 /* non-PIC stubs. */
4434 /* V5T and above. */
4435 ? arm_stub_long_branch_any_any
4436 /* V4T. */
4439 /* Handle v4t short branches. */
4444 }
4445 }
4446 }
4451 {
4453 _bfd_error_handler
4455 " section with SHF_ARM_PURECODE section"
4456 " attribute is only supported for M-profile"
4460 {
4461 /* Arm to thumb. */
4466 {
4467 _bfd_error_handler
4471 }
4473 /* We have an extra 2-bytes reach because of
4474 the mode change (bit 24 (H) of BLX encoding). */
4480 {
4482 /* PIC stubs. */
4484 /* V5T and above. */
4485 ? arm_stub_long_branch_any_thumb_pic
4486 /* V4T stub. */
4489 /* non-PIC stubs. */
4491 /* V5T and above. */
4492 ? arm_stub_long_branch_any_any
4493 /* V4T. */
4495 }
4496 }
4497 else
4498 {
4499 /* Arm to arm. */
4502 {
4503 stub_type =
4505 /* PIC stubs. */
4507 /* TLS PIC Stub. */
4508 ? arm_stub_long_branch_any_tls_pic
4510 ? arm_stub_long_branch_arm_nacl_pic
4512 /* non-PIC stubs. */
4514 ? arm_stub_long_branch_arm_nacl
4516 }
4517 }
4518 }
4520 /* If a stub is needed, record the actual destination type. */
4525 }
4527 /* Build a name for an entry in the stub hash table. */
4535 {
4537 bfd_size_type len;
4540 {
4549 }
4550 else
4551 {
4563 }
4566 }
4568 /* Look up an entry in the stub hash. Stub entries are cached because
4569 creating the stub name takes a bit of time. */
4578 {
4586 /* If this input section is part of a group of sections sharing one
4587 stub section, then use the id of the first section in the group.
4588 Stub names need to include a section id, as there may well be
4589 more than one stub used to reach say, printf, and we need to
4590 distinguish between them. */
4598 {
4600 }
4601 else
4602 {
4615 }
4618 }
4620 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4621 section. */
4623 static bfd_boolean
4625 {
4630 {
4636 }
4639 }
4641 /* Required alignment (as a power of 2) for the dedicated section holding
4642 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4643 with input sections. */
4645 static int
4646 arm_dedicated_stub_output_section_required_alignment
4648 {
4653 {
4654 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4655 boundary. */
4662 }
4665 }
4667 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4668 NULL if veneers of this type are interspersed with input sections. */
4672 {
4677 {
4684 }
4687 }
4689 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4690 returns the address of the hash table field in HTAB holding a pointer to the
4691 corresponding input section. Otherwise, returns NULL. */
4696 {
4701 {
4708 }
4711 }
4713 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4714 is the section that branch into veneer and can be NULL if stub should go in
4715 a dedicated output section. Returns a pointer to the stub section, and the
4716 section to which the stub section will be attached (in *LINK_SEC_P).
4717 LINK_SEC_P may be NULL. */
4723 {
4726 bfd_boolean dedicated_output_section =
4731 {
4741 {
4745 }
4746 }
4747 else
4748 {
4758 }
4761 {
4763 bfd_size_type len;
4775 align);
4782 }
4791 }
4793 /* Add a new stub entry to the stub hash. Not all fields of the new
4794 stub entry are initialised. */
4800 {
4806 stub_type);
4810 /* Enter this entry into the linker stub hash table. */
4814 {
4820 }
4827 }
4829 /* Store an Arm insn into an output section not processed by
4830 elf32_arm_write_section. */
4832 static void
4835 {
4838 else
4840 }
4842 /* Store a 16-bit Thumb insn into an output section not processed by
4843 elf32_arm_write_section. */
4845 static void
4848 {
4851 else
4853 }
4855 /* Store a Thumb2 insn into an output section not processed by
4856 elf32_arm_write_section. */
4858 static void
4861 {
4862 /* T2 instructions are 16-bit streamed. */
4864 {
4867 }
4868 else
4869 {
4872 }
4873 }
4875 /* If it's possible to change R_TYPE to a more efficient access
4876 model, return the new reloc type. */
4878 static unsigned
4881 {
4888 /* We do not support relaxations for Old TLS models. */
4890 {
4897 }
4900 }
4902 static bfd_reloc_status_type elf32_arm_final_link_relocate
4908 static unsigned int
4910 {
4912 {
4944 }
4945 }
4947 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4948 veneering (TRUE) or have their own symbol (FALSE). */
4950 static bfd_boolean
4952 {
4957 {
4963 }
4966 }
4968 /* Returns the padding needed for the dedicated section used stubs of type
4969 STUB_TYPE. */
4971 static int
4973 {
4978 {
4984 }
4987 }
4989 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4990 returns the address of the hash table field in HTAB holding the offset at
4991 which new veneers should be layed out in the stub section. */
4996 {
4998 {
5005 }
5006 }
5008 static bfd_boolean
5011 {
5012 #define MAXRELOCS 3
5013 bfd_boolean removed_sg_veneer;
5020 bfd_vma sym_value;
5030 /* Massage our args to the form they really have. */
5042 /* We have to do less-strictly-aligned fixes last. */
5045 /* Assign a slot at the end of section if none assigned yet. */
5047 {
5050 }
5055 /* This is the address of the stub destination. */
5065 {
5067 {
5069 {
5072 {
5073 /* We've borrowed the reloc_addend field to mean we should
5074 insert a condition code into this (Thumb-1 branch)
5075 instruction. See THUMB16_BCOND_INSN. */
5078 }
5081 }
5091 {
5094 }
5101 /* Handle cases where the target is encoded within the
5102 instruction. */
5104 {
5107 }
5121 }
5122 }
5127 /* Stub size has already been computed in arm_size_one_stub. Check
5128 consistency. */
5131 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5135 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5136 to relocate in each stub. */
5137 removed_sg_veneer =
5142 {
5143 Elf_Internal_Rela rel;
5144 bfd_boolean unresolved_reloc;
5146 bfd_vma points_to =
5155 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5156 template should refer back to the instruction after the original
5157 branch. We use target_section as Cortex-A8 erratum workaround stubs
5158 are only generated when both source and target are in the same
5159 section. */
5171 }
5174 #undef MAXRELOCS
5175 }
5177 /* Calculate the template, template size and instruction size for a stub.
5178 Return value is the instruction size. */
5180 static unsigned int
5184 {
5199 {
5201 {
5215 }
5216 }
5219 }
5221 /* As above, but don't actually build the stub. Just bump offset so
5222 we know stub section sizes. */
5224 static bfd_boolean
5227 {
5232 /* Massage our args to the form they really have. */
5241 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5243 {
5247 }
5249 /* Already accounted for. */
5257 }
5259 /* External entry points for sizing and building linker stubs. */
5261 /* Set up various things so that we can make a list of input sections
5262 for each output section included in the link. Returns -1 on error,
5263 0 when no stubs will be needed, and 1 on success. */
5265 int
5268 {
5274 bfd_size_type amt;
5282 /* Count the number of input BFDs and find the top input section id. */
5286 {
5291 {
5294 }
5295 }
5304 /* We can't use output_bfd->section_count here to find the top output
5305 section index as some sections may have been removed, and
5306 _bfd_strip_section_from_output doesn't renumber the indices. */
5310 {
5313 }
5322 /* For sections we aren't interested in, mark their entries with a
5323 value we can check later. */
5325 do
5332 {
5335 }
5338 }
5340 /* The linker repeatedly calls this function for each input section,
5341 in the order that input sections are linked into output sections.
5342 Build lists of input sections to determine groupings between which
5343 we may insert linker stubs. */
5345 void
5348 {
5355 {
5359 {
5360 /* Steal the link_sec pointer for our list. */
5361 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5362 /* This happens to make the list in reverse order,
5363 which we reverse later. */
5366 }
5367 }
5368 }
5370 /* See whether we can group stub sections together. Grouping stub
5371 sections may result in fewer stubs. More importantly, we need to
5372 put all .init* and .fini* stubs at the end of the .init or
5373 .fini output sections respectively, because glibc splits the
5374 _init and _fini functions into multiple parts. Putting a stub in
5375 the middle of a function is not a good idea. */
5377 static void
5379 bfd_size_type stub_group_size,
5380 bfd_boolean stubs_always_after_branch)
5381 {
5384 do
5385 {
5392 /* Reverse the list: we must avoid placing stubs at the
5393 beginning of the section because the beginning of the text
5394 section may be required for an interrupt vector in bare metal
5395 code. */
5396 #define NEXT_SEC PREV_SEC
5399 {
5400 /* Pop from tail. */
5404 /* Push on head. */
5407 }
5410 {
5414 bfd_vma end_of_next;
5418 {
5422 /* End of NEXT is too far from start, so stop. */
5424 /* Add NEXT to the group. */
5426 }
5428 /* OK, the size from the start to the start of CURR is less
5429 than stub_group_size and thus can be handled by one stub
5430 section. (Or the head section is itself larger than
5431 stub_group_size, in which case we may be toast.)
5432 We should really be keeping track of the total size of
5433 stubs added here, as stubs contribute to the final output
5434 section size. */
5435 do
5436 {
5438 /* Set up this stub group. */
5440 }
5443 /* But wait, there's more! Input sections up to stub_group_size
5444 bytes after the stub section can be handled by it too. */
5446 {
5450 {
5453 /* End of NEXT is too far from stubs, so stop. */
5455 /* Add NEXT to the stub group. */
5459 }
5460 }
5462 }
5463 }
5467 #undef PREV_SEC
5468 #undef NEXT_SEC
5469 }
5471 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5472 erratum fix. */
5474 static int
5476 {
5484 else
5486 }
5491 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5492 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5493 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5494 otherwise. */
5496 static bfd_boolean
5506 {
5519 {
5523 bfd_vma base_vma;
5542 {
5553 /* Span is entirely within a single 4KB region: skip scanning. */
5558 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5560 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5561 * The branch target is in the same 4KB region as the
5562 first half of the branch.
5563 * The instruction before the branch is a 32-bit
5564 length non-branch instruction. */
5566 {
5575 {
5576 /* Load the rest of the insn (in manual-friendly order). */
5579 /* Encoding T4: B<c>.W. */
5581 /* Encoding T1: BL<c>.W. */
5583 /* Encoding T2: BLX<c>.W. */
5585 /* Encoding T3: B<c>.W (not permitted in IT block). */
5588 }
5593 && insn_32bit
5594 && is_32bit_branch
5595 && last_was_32bit
5597 {
5601 bfd_vma target;
5613 {
5617 /* We don't care about the error returned from this
5618 function, only if there is glue or not. */
5625 /* Keep a simpler condition, for the sake of clarity. */
5631 {
5635 else
5637 }
5638 }
5640 /* Check if we have an offending branch instruction. */
5643 /* We've already made a stub for this instruction, e.g.
5644 it's a long branch or a Thumb->ARM stub. Assume that
5645 stub will suffice to work around the A8 erratum (see
5646 setting of always_after_branch above). */
5647 ;
5649 {
5658 }
5660 {
5680 }
5683 {
5686 /* The original instruction is a BL, but the target is
5687 an ARM instruction. If we were not making a stub,
5688 the BL would have been converted to a BLX. Use the
5689 BLX stub instead in that case. */
5692 {
5696 }
5697 /* Conversely, if the original instruction was
5698 BLX but the target is Thumb mode, use the BL
5699 stub. */
5702 {
5706 }
5711 /* If we found a relocation, use the proper destination,
5712 not the offset in the (unrelocated) instruction.
5713 Note this is always done if we switched the stub type
5714 above. */
5716 offset =
5719 /* If the stub will use a Thumb-mode branch to a
5720 PLT target, redirect it to the preceding Thumb
5721 entry point. */
5727 /* The BLX stub is ARM-mode code. Adjust the offset to
5728 take the different PC value (+8 instead of +4) into
5729 account. */
5734 {
5738 {
5744 }
5747 {
5748 /* If we're doing a subsequent scan,
5749 check if we've found the same fix as
5750 before, and try and reuse the stub
5751 name. */
5755 {
5759 }
5760 }
5763 {
5767 }
5780 num_a8_fixes++;
5781 }
5782 }
5783 }
5788 }
5789 }
5793 }
5800 }
5802 /* Create or update a stub entry depending on whether the stub can already be
5803 found in HTAB. The stub is identified by:
5804 - its type STUB_TYPE
5805 - its source branch (note that several can share the same stub) whose
5806 section and relocation (if any) are given by SECTION and IRELA
5807 respectively
5808 - its target symbol whose input section, hash, name, value and branch type
5809 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5810 respectively
5812 If found, the value of the stub's target symbol is updated from SYM_VALUE
5813 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5814 TRUE and the stub entry is initialized.
5816 Returns the stub that was created or updated, or NULL if an error
5817 occurred. */
5826 {
5838 else
5839 {
5844 /* Support for grouping stub sections. */
5847 /* Get the name of this stub. */
5849 stub_type);
5852 }
5855 FALSE);
5856 /* The proper stub has already been created, just update its value. */
5858 {
5863 }
5867 {
5871 }
5881 else
5882 {
5889 {
5892 }
5894 /* For historical reasons, use the existing names for ARM-to-Thumb and
5895 Thumb-to-ARM stubs. */
5906 else
5908 }
5912 }
5914 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5915 gateway veneer to transition from non secure to secure state and create them
5916 accordingly.
5918 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5919 defines the conditions that govern Secure Gateway veneer creation for a
5920 given symbol <SYM> as follows:
5921 - it has function type
5922 - it has non local binding
5923 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5924 same type, binding and value as <SYM> (called normal symbol).
5925 An entry function can handle secure state transition itself in which case
5926 its special symbol would have a different value from the normal symbol.
5928 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5929 entry mapping while HTAB gives the name to hash entry mapping.
5930 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5931 created.
5933 The return value gives whether a stub failed to be allocated. */
5935 static bfd_boolean
5939 {
5947 bfd_vma sym_value;
5963 NULL);
5967 /* Scan symbols. */
5969 {
5973 {
5975 /* Not a special symbol. */
5981 /* Special symbol with local binding. */
5983 }
5984 else
5985 {
5989 /* Not a special symbol. */
5993 /* Special symbol has incorrect binding or type. */
5998 }
6001 {
6007 }
6010 {
6017 }
6023 /* No associated normal symbol or it is neither global nor weak. */
6028 {
6029 /* Initialize here to avoid warning about use of possibly
6030 uninitialized variable. */
6034 {
6035 /* Searching for a normal symbol with local binding. */
6037 {
6038 lsym_name =
6044 }
6045 }
6048 {
6049 _bfd_error_handler
6053 }
6054 else
6055 _bfd_error_handler
6060 }
6066 {
6067 _bfd_error_handler
6071 }
6075 /* If this section is a link-once section that will be discarded, then
6076 don't create any stubs. */
6078 {
6079 _bfd_error_handler
6082 }
6085 {
6086 _bfd_error_handler
6089 }
6094 stub_entry
6101 else
6102 {
6105 }
6106 }
6111 }
6113 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6114 code entry function, ie can be called from non secure code without using a
6115 veneer. */
6117 static bfd_boolean
6119 {
6123 file_ptr offset;
6126 /* Defined symbol of function type. */
6133 /* Read first instruction. */
6143 /* Starts by SG instruction. */
6145 }
6147 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6148 secure gateway veneers (ie. the veneers was not in the input import library)
6149 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6151 static bfd_boolean
6153 {
6157 /* Massage our args to the form they really have. */
6171 }
6173 /* Set offset of each secure gateway veneers so that its address remain
6174 identical to the one in the input import library referred by
6175 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6176 (present in input import library but absent from the executable being
6177 linked) or if new veneers appeared and there is no output import library
6178 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6179 number of secure gateway veneers found in the input import library.
6181 The function returns whether an error occurred. If no error occurred,
6182 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6183 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6184 veneer observed set for new veneers to be layed out after. */
6186 static bfd_boolean
6190 {
6193 flagword flags;
6200 bfd_size_type cmse_stub_size;
6209 /* No input secure gateway import library. */
6215 {
6219 }
6221 /* Get symbol table size. */
6226 /* Read in the input secure gateway import library's symbol table. */
6230 {
6233 }
6236 cmse_stub_size =
6240 out_sec_name =
6242 stub_out_sec =
6247 /* Set addresses of veneers mentionned in input secure gateway import
6248 library's symbol table. */
6250 {
6261 {
6263 "symbol should be absolute, global and "
6268 }
6277 /* Stub entry should have been created by cmse_scan or the symbol be of
6278 a secure function callable from non secure code. */
6280 {
6281 bfd_boolean new_stub;
6283 _bfd_error_handler
6287 stub_entry
6294 else
6295 {
6297 new_cmse_stubs_created++;
6299 }
6302 }
6303 /* Symbol found is not callable from non secure code. */
6305 {
6307 {
6309 sym_name);
6311 }
6313 }
6314 else
6315 {
6316 /* Only stubs for SG veneers should have been created. */
6319 /* Check visibility hasn't changed. */
6322 _bfd_error_handler
6324 sym_name);
6327 }
6329 /* Size should match that of a SG veneer. */
6331 {
6335 }
6337 /* Previous veneer address is before current SG veneer section. */
6339 {
6340 /* Avoid offset underflow. */
6345 }
6347 /* Complain if stub offset not a multiple of stub size. */
6349 {
6350 _bfd_error_handler
6354 }
6359 new_cmse_stubs_created--;
6365 }
6368 {
6370 _bfd_error_handler
6374 }
6377 {
6378 _bfd_error_handler
6380 out_sec_name);
6382 }
6384 free_sym_buf:
6387 }
6389 /* Determine and set the size of the stub section for a final link.
6391 The basic idea here is to examine all the relocations looking for
6392 PC-relative calls to a target that is unreachable with a "bl"
6393 instruction. */
6395 bfd_boolean
6399 bfd_signed_vma group_size,
6401 asection *,
6404 {
6408 bfd_size_type stub_group_size;
6420 {
6425 }
6427 /* Propagate mach to stub bfd, because it may not have been
6428 finalized when we created stub_bfd. */
6432 /* Stash our params away. */
6441 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6442 as the first half of a 32-bit branch straddling two 4K pages. This is a
6443 crude way of enforcing that. */
6449 else
6453 {
6454 /* Default values. */
6455 /* Thumb branch range is +-4MB has to be used as the default
6456 maximum size (a given section can contain both ARM and Thumb
6457 code, so the worst case has to be taken into account).
6459 This value is 24K less than that, which allows for 2025
6460 12-byte stubs. If we exceed that, then we will fail to link.
6461 The user will have to relink with an explicit group size
6462 option. */
6464 }
6468 /* If we're applying the cortex A8 fix, we need to determine the
6469 program header size now, because we cannot change it later --
6470 that could alter section placements. Notice the A8 erratum fix
6471 ends up requiring the section addresses to remain unchanged
6472 modulo the page size. That's something we cannot represent
6473 inside BFD, and we don't want to force the section alignment to
6474 be the page size. */
6479 {
6491 {
6502 /* We'll need the symbol table in a second. */
6507 /* Limit scan of symbols to object file whose profile is
6508 Microcontroller to not hinder performance in the general case. */
6510 {
6520 }
6522 /* Walk over each section attached to the input bfd. */
6526 {
6529 /* If there aren't any relocs, then there's nothing more
6530 to do. */
6536 /* If this section is a link-once section that will be
6537 discarded, then don't create any stubs. */
6542 /* Get the relocs. */
6543 internal_relocs
6549 /* Now examine each relocation. */
6553 {
6556 bfd_vma sym_value;
6557 bfd_vma destination;
6568 {
6570 error_ret_free_internal:
6573 /* Fall through. */
6574 error_ret_free_local:
6580 }
6584 hash = elf32_arm_hash_entry
6588 /* Only look for stubs on branch instructions, or
6589 non-relaxed TLSCALL */
6602 : (elf32_arm_local_got_tls_type
6607 /* Now determine the call target, its name, value,
6608 section. */
6616 {
6617 /* A non-relaxed TLS call. The target is the
6618 plt-resident trampoline and nothing to do
6619 with the symbol. */
6626 }
6628 {
6629 /* It's a local symbol. */
6633 {
6634 local_syms
6637 local_syms
6643 }
6652 else
6653 sym_sec =
6657 /* This is an undefined symbol. It can never
6658 be resolved. */
6667 branch_type =
6669 sym_name
6673 }
6674 else
6675 {
6676 /* It's an external symbol. */
6684 {
6691 /* For a destination in a shared library,
6692 use the PLT stub as target address to
6693 decide whether a branch stub is
6694 needed. */
6699 {
6703 destination = (sym_value
6706 }
6711 }
6714 {
6715 /* For a shared library, use the PLT stub as
6716 target address to decide whether a long
6717 branch stub is needed.
6718 For absolute code, they cannot be handled. */
6726 {
6730 destination = (sym_value
6733 }
6734 else
6736 }
6737 else
6738 {
6741 }
6743 branch_type =
6746 }
6748 do
6749 {
6750 bfd_boolean new_stub;
6753 /* Determine what (if any) linker stub is needed. */
6761 /* We've either created a stub for this reloc already,
6762 or we are about to. */
6763 stub_entry =
6774 else
6776 }
6779 /* Look for relocations which might trigger Cortex-A8
6780 erratum. */
6786 {
6792 {
6793 /* Found a candidate. Note we haven't checked the
6794 destination is within 4K here: if we do so (and
6795 don't create an entry in a8_relocs) we can't tell
6796 that a branch should have been relocated when
6797 scanning later. */
6799 {
6805 }
6815 num_a8_relocs++;
6816 }
6817 }
6818 }
6820 /* We're done with the internal relocs, free them. */
6823 }
6826 {
6827 /* Sort relocs which might apply to Cortex-A8 erratum. */
6832 /* Scan for branches which might trigger Cortex-A8 erratum. */
6839 }
6843 {
6846 else
6848 }
6849 }
6862 /* OK, we've added some stubs. Find out the new size of the
6863 stub sections. */
6867 {
6868 /* Ignore non-stub sections. */
6873 }
6875 /* Add new SG veneers after those already in the input import
6876 library. */
6878 stub_type++)
6879 {
6891 }
6893 /* Compute stub section size, considering padding. */
6896 stub_type++)
6897 {
6903 /* Skip if no stub input section or no stub section padding
6904 required. */
6907 /* Stub section padding required but no dedicated section. */
6913 }
6915 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6918 {
6925 stub_sec->size
6927 NULL);
6928 }
6931 /* Ask the linker to do its stuff. */
6934 }
6936 /* Add stubs for Cortex-A8 erratum fixes now. */
6938 {
6940 {
6953 {
6957 }
6976 }
6978 /* Stash the Cortex-A8 erratum fix array for use later in
6979 elf32_arm_write_section(). */
6982 }
6983 else
6984 {
6987 }
6989 }
6991 /* Build all the stubs associated with the current output file. The
6992 stubs are kept in a hash table attached to the main linker hash
6993 table. We also set up the .plt entries for statically linked PIC
6994 functions here. This function is called via arm_elf_finish in the
6995 linker. */
6997 bfd_boolean
6999 {
7012 {
7013 bfd_size_type size;
7015 /* Ignore non-stub sections. */
7019 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
7020 must at least be done for stub section requiring padding and for SG
7021 veneers to ensure that a non secure code branching to a removed SG
7022 veneer causes an error. */
7029 }
7031 /* Add new SG veneers after those already in the input import library. */
7033 {
7045 }
7047 /* Build the stubs as directed by the stub hash table. */
7051 {
7052 /* Place the cortex a8 stubs last. */
7055 }
7058 }
7060 /* Locate the Thumb encoded calling stub for NAME. */
7066 {
7071 /* We need a pointer to the armelf specific hash table. */
7083 hash = elf_link_hash_lookup
7094 }
7096 /* Locate the ARM encoded calling stub for NAME. */
7102 {
7107 /* We need a pointer to the elfarm specific hash table. */
7119 myh = elf_link_hash_lookup
7130 }
7132 /* ARM->Thumb glue (static images):
7134 .arm
7135 __func_from_arm:
7136 ldr r12, __func_addr
7137 bx r12
7138 __func_addr:
7139 .word func @ behave as if you saw a ARM_32 reloc.
7141 (v5t static images)
7142 .arm
7143 __func_from_arm:
7144 ldr pc, __func_addr
7145 __func_addr:
7146 .word func @ behave as if you saw a ARM_32 reloc.
7148 (relocatable images)
7149 .arm
7150 __func_from_arm:
7151 ldr r12, __func_offset
7152 add r12, r12, pc
7153 bx r12
7154 __func_offset:
7155 .word func - . */
7157 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7162 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7166 #define ARM2THUMB_PIC_GLUE_SIZE 16
7171 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7173 .thumb .thumb
7174 .align 2 .align 2
7175 __func_from_thumb: __func_from_thumb:
7176 bx pc push {r6, lr}
7177 nop ldr r6, __func_addr
7178 .arm mov lr, pc
7179 b func bx r6
7180 .arm
7181 ;; back_to_thumb
7182 ldmia r13! {r6, lr}
7183 bx lr
7184 __func_addr:
7185 .word func */
7187 #define THUMB2ARM_GLUE_SIZE 8
7192 #define VFP11_ERRATUM_VENEER_SIZE 8
7193 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7194 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7196 #define ARM_BX_VENEER_SIZE 12
7201 #ifndef ELFARM_NABI_C_INCLUDED
7202 static void
7204 {
7209 {
7210 /* Do not include empty glue sections in the output. */
7212 {
7216 }
7218 }
7229 }
7231 bfd_boolean
7233 {
7241 ARM2THUMB_GLUE_SECTION_NAME);
7245 THUMB2ARM_GLUE_SECTION_NAME);
7249 VFP11_ERRATUM_VENEER_SECTION_NAME);
7253 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7257 ARM_BX_GLUE_SECTION_NAME);
7260 }
7262 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7263 returns the symbol identifying the stub. */
7268 {
7275 bfd_vma val;
7276 bfd_size_type size;
7282 s = bfd_get_linker_section
7294 myh = elf_link_hash_lookup
7298 {
7299 /* We've already seen this guy. */
7302 }
7304 /* The only trick here is using hash_table->arm_glue_size as the value.
7305 Even though the section isn't allocated yet, this is where we will be
7306 putting it. The +1 on the value marks that the stub has not been
7307 output yet - not that it is a Thumb function. */
7326 else
7333 }
7335 /* Allocate space for ARMv4 BX veneers. */
7337 static void
7339 {
7345 bfd_vma val;
7347 /* BX PC does not need a veneer. */
7355 /* Check if this veneer has already been allocated. */
7359 s = bfd_get_linker_section
7364 /* Add symbol for veneer. */
7372 myh = elf_link_hash_lookup
7390 }
7393 /* Add an entry to the code/data map for section SEC. */
7395 static void
7397 {
7402 {
7407 }
7412 {
7417 }
7420 {
7423 }
7424 }
7427 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7428 veneers are handled for now. */
7430 static bfd_vma
7436 {
7442 bfd_vma val;
7450 s = bfd_get_linker_section
7465 myh = elf_link_hash_lookup
7480 /* Link veneer back to calling location. */
7494 /* A symbol for the return from the veneer. */
7498 myh = elf_link_hash_lookup
7515 /* Generate a mapping symbol for the veneer section, and explicitly add an
7516 entry for that symbol to the code/data map for the section. */
7518 {
7520 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7521 ever requires this erratum fix. */
7531 /* The elf32_arm_init_maps function only cares about symbols from input
7532 BFDs. We must make a note of this generated mapping symbol
7533 ourselves so that code byteswapping works properly in
7534 elf32_arm_write_section. */
7536 }
7542 /* The offset of the veneer. */
7544 }
7546 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7547 veneers need to be handled because used only in Cortex-M. */
7549 static bfd_vma
7555 bfd_size_type veneer_size)
7556 {
7562 bfd_vma val;
7570 s = bfd_get_linker_section
7585 myh = elf_link_hash_lookup
7600 /* Link veneer back to calling location. */
7614 /* A symbol for the return from the veneer. */
7618 myh = elf_link_hash_lookup
7635 /* Generate a mapping symbol for the veneer section, and explicitly add an
7636 entry for that symbol to the code/data map for the section. */
7638 {
7640 /* Creates a THUMB symbol since there is no other choice. */
7650 /* The elf32_arm_init_maps function only cares about symbols from input
7651 BFDs. We must make a note of this generated mapping symbol
7652 ourselves so that code byteswapping works properly in
7653 elf32_arm_write_section. */
7655 }
7661 /* The offset of the veneer. */
7663 }
7665 #define ARM_GLUE_SECTION_FLAGS \
7666 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7667 | SEC_READONLY | SEC_LINKER_CREATED)
7669 /* Create a fake section for use by the ARM backend of the linker. */
7671 static bfd_boolean
7673 {
7678 /* Already made. */
7687 /* Set the gc mark to prevent the section from being removed by garbage
7688 collection, despite the fact that no relocs refer to this section. */
7692 }
7694 /* Set size of .plt entries. This function is called from the
7695 linker scripts in ld/emultempl/{armelf}.em. */
7697 void
7699 {
7701 }
7703 /* Add the glue sections to ABFD. This function is called from the
7704 linker scripts in ld/emultempl/{armelf}.em. */
7706 bfd_boolean
7709 {
7711 bfd_boolean dostm32l4xx = globals
7713 bfd_boolean addglue;
7715 /* If we are only performing a partial
7716 link do not bother adding the glue. */
7728 return addglue
7730 }
7732 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7733 ensures they are not marked for deletion by
7734 strip_excluded_output_sections () when veneers are going to be created
7735 later. Not doing so would trigger assert on empty section size in
7736 lang_size_sections_1 (). */
7738 void
7740 {
7743 /* If we are only performing a partial
7744 link do not bother adding the glue. */
7749 {
7760 }
7761 }
7763 /* Select a BFD to be used to hold the sections used by the glue code.
7764 This function is called from the linker scripts in ld/emultempl/
7765 {armelf/pe}.em. */
7767 bfd_boolean
7769 {
7772 /* If we are only performing a partial link
7773 do not bother getting a bfd to hold the glue. */
7777 /* Make sure we don't attach the glue sections to a dynamic object. */
7786 /* Save the bfd for later use. */
7790 }
7792 static void
7794 {
7798 Tag_CPU_arch);
7801 {
7804 }
7805 else
7806 {
7809 }
7810 }
7812 bfd_boolean
7815 {
7824 /* If we are only performing a partial link do not bother
7825 to construct any glue. */
7829 /* Here we have a bfd that is to be included on the link. We have a
7830 hook to do reloc rummaging, before section sizes are nailed down. */
7837 {
7839 abfd);
7841 }
7843 /* PR 5398: If we have not decided to include any loadable sections in
7844 the output then we will not have a glue owner bfd. This is OK, it
7845 just means that there is nothing else for us to do here. */
7849 /* Rummage around all the relocs and map the glue vectors. */
7856 {
7865 /* Load the relocs. */
7866 internal_relocs
7874 {
7883 /* These are the only relocation types we care about. */
7888 /* Get the section contents if we haven't done so already. */
7890 {
7891 /* Get cached copy if it exists. */
7894 else
7895 {
7896 /* Go get them off disk. */
7899 }
7900 }
7903 {
7909 }
7911 /* If the relocation is not against a symbol it cannot concern us. */
7914 /* We don't care about local symbols. */
7918 /* This is an external symbol. */
7923 /* If the relocation is against a static symbol it must be within
7924 the current section and so cannot be a cross ARM/Thumb relocation. */
7928 /* If the call will go through a PLT entry then we do not need
7929 glue. */
7934 {
7936 /* This one is a call from arm code. We need to look up
7937 the target of the call. If it is a thumb target, we
7938 insert glue. */
7946 }
7947 }
7958 }
7962 error_return:
7971 }
7972 #endif
7975 /* Initialise maps of ARM/Thumb/data for input BFDs. */
7977 void
7979 {
7984 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7994 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7995 should contain the number of local symbols, which should come before any
7996 global symbols. Mapping symbols are always local. */
7998 NULL);
8000 /* No internal symbols read? Skip this BFD. */
8005 {
8012 {
8017 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
8019 }
8020 }
8021 }
8024 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8025 say what they wanted. */
8027 void
8029 {
8037 {
8038 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8043 else
8045 }
8046 }
8049 void
8051 {
8057 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8059 {
8061 {
8068 /* Give a warning, but do as the user requests anyway. */
8071 }
8072 }
8074 /* For earlier architectures, we might need the workaround, but do not
8075 enable it by default. If users is running with broken hardware, they
8076 must enable the erratum fix explicitly. */
8078 }
8080 void
8082 {
8089 /* We assume only Cortex-M4 may require the fix. */
8092 {
8094 /* Give a warning, but do as the user requests anyway. */
8095 _bfd_error_handler
8098 }
8099 }
8101 enum bfd_arm_vfp11_pipe
8102 {
8103 VFP11_FMAC,
8104 VFP11_LS,
8105 VFP11_DS,
8106 VFP11_BAD
8107 };
8109 /* Return a VFP register number. This is encoded as RX:X for single-precision
8110 registers, or X:RX for double-precision registers, where RX is the group of
8111 four bits in the instruction encoding and X is the single extension bit.
8112 RX and X fields are specified using their lowest (starting) bit. The return
8113 value is:
8115 0...31: single-precision registers s0...s31
8116 32...63: double-precision registers d0...d31.
8118 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8119 encounter VFP3 instructions, so we allow the full range for DP registers. */
8121 static unsigned int
8124 {
8127 else
8129 }
8131 /* Set bits in *WMASK according to a register number REG as encoded by
8132 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8134 static void
8136 {
8141 }
8143 /* Return TRUE if WMASK overwrites anything in REGS. */
8145 static bfd_boolean
8147 {
8151 {
8164 }
8167 }
8169 /* In this function, we're interested in two things: finding input registers
8170 for VFP data-processing instructions, and finding the set of registers which
8171 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8172 hold the written set, so FLDM etc. are easy to deal with (we're only
8173 interested in 32 SP registers or 16 dp registers, due to the VFP version
8174 implemented by the chip in question). DP registers are marked by setting
8175 both SP registers in the write mask). */
8177 static enum bfd_arm_vfp11_pipe
8180 {
8185 {
8195 {
8217 vfp_binop:
8225 {
8230 {
8244 /* These instructions will not bounce due to underflow. */
8250 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8251 registers to cause the erratum in previous instructions. */
8257 {
8262 /* Only FCVTSD can underflow. */
8269 }
8274 }
8275 }
8280 }
8281 }
8282 /* Two-register transfer. */
8284 {
8288 {
8291 else
8292 {
8295 }
8296 }
8299 }
8301 {
8306 {
8313 {
8321 }
8331 }
8334 }
8335 /* Single-register transfer. Note L==0. */
8337 {
8342 {
8345 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8346 destination register. I don't know if this is exactly right,
8347 but it is the conservative choice. */
8353 }
8356 }
8359 }
8365 /* Look for potentially-troublesome code sequences which might trigger the
8366 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8367 (available from ARM) for details of the erratum. A short version is
8368 described in ld.texinfo. */
8370 bfd_boolean
8372 {
8383 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8384 The states transition as follows:
8386 0 -> 1 (vector) or 0 -> 2 (scalar)
8387 A VFP FMAC-pipeline instruction has been seen. Fill
8388 regs[0]..regs[numregs-1] with its input operands. Remember this
8389 instruction in 'first_fmac'.
8391 1 -> 2
8392 Any instruction, except for a VFP instruction which overwrites
8393 regs[*].
8395 1 -> 3 [ -> 0 ] or
8396 2 -> 3 [ -> 0 ]
8397 A VFP instruction has been seen which overwrites any of regs[*].
8398 We must make a veneer! Reset state to 0 before examining next
8399 instruction.
8401 2 -> 0
8402 If we fail to match anything in state 2, reset to state 0 and reset
8403 the instruction pointer to the instruction after 'first_fmac'.
8405 If the VFP11 vector mode is in use, there must be at least two unrelated
8406 instructions between anti-dependent VFP11 instructions to properly avoid
8407 triggering the erratum, hence the use of the extra state 1. */
8409 /* If we are only performing a partial link do not bother
8410 to construct any glue. */
8414 /* Skip if this bfd does not correspond to an ELF image. */
8418 /* We should have chosen a fix type by the time we get here. */
8424 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8429 {
8433 /* If we don't have executable progbits, we're not interested in this
8434 section. Also skip if section is to be excluded. */
8454 elf32_arm_compare_mapping);
8457 {
8463 /* FIXME: Only ARM mode is supported at present. We may need to
8464 support Thumb-2 mode also at some point. */
8469 {
8484 {
8488 /* I'm assuming the VFP11 erratum can trigger with denorm
8489 operands on either the FMAC or the DS pipeline. This might
8490 lead to slightly overenthusiastic veneer insertion. */
8492 {
8496 }
8500 {
8503 other_regs,
8507 numregs))
8509 else
8511 }
8515 {
8518 other_regs,
8522 numregs))
8524 else
8525 {
8528 }
8529 }
8534 }
8537 {
8546 {
8553 }
8556 first_fmac);
8564 }
8567 }
8568 }
8574 }
8578 error_return:
8584 }
8586 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8587 after sections have been laid out, using specially-named symbols. */
8589 void
8592 {
8600 /* Skip if this bfd does not correspond to an ELF image. */
8612 {
8617 {
8619 bfd_vma vma;
8622 {
8625 /* Find veneer symbol. */
8629 myh = elf_link_hash_lookup
8645 /* Find return location. */
8649 myh = elf_link_hash_lookup
8665 }
8666 }
8667 }
8670 }
8672 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8673 return locations after sections have been laid out, using
8674 specially-named symbols. */
8676 void
8679 {
8687 /* Skip if this bfd does not correspond to an ELF image. */
8699 {
8704 {
8706 bfd_vma vma;
8709 {
8711 /* Find veneer symbol. */
8715 myh = elf_link_hash_lookup
8730 /* Find return location. */
8734 myh = elf_link_hash_lookup
8750 }
8751 }
8752 }
8755 }
8759 {
8760 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8761 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8763 }
8767 {
8768 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8769 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8771 }
8775 {
8776 /* A6.5 Extension register load or store instruction
8777 A7.7.229
8778 We look for SP 32-bit and DP 64-bit registers.
8779 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8780 <list> is consecutive 64-bit registers
8781 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8782 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8783 <list> is consecutive 32-bit registers
8784 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8785 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8786 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8787 return
8792 /* (IA with !), includes VPOP (when reg number is SP). */
8794 /* (DB with !). */
8796 }
8798 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8799 VLDM opcode and:
8800 - computes the number and the mode of memory accesses
8801 - decides if the replacement should be done:
8802 . replaces only if > 8-word accesses
8803 . or (testing purposes only) replaces all accesses. */
8805 static bfd_boolean
8807 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8808 {
8811 /* The field encoding the register list is the same for both LDMIA
8812 and LDMDB encodings. */
8818 /* DEFAULT mode accounts for the real bug condition situation,
8819 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8820 return
8823 }
8825 /* Look for potentially-troublesome code sequences which might trigger
8826 the STM STM32L4XX erratum. */
8828 bfd_boolean
8831 {
8839 /* If we are only performing a partial link do not bother
8840 to construct any glue. */
8844 /* Skip if this bfd does not correspond to an ELF image. */
8851 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8856 {
8860 /* If we don't have executable progbits, we're not interested in this
8861 section. Also skip if section is to be excluded. */
8881 elf32_arm_compare_mapping);
8884 {
8891 /* Only Thumb2 mode need be supported with this CM4 specific
8892 code, we should not encounter any arm mode eg span_type
8893 != 'a'. */
8898 {
8905 /* The first 16-bits of all 32-bit thumb2 instructions start
8906 with opcode[15..13]=0b111 and the encoded op1 can be anything
8907 except opcode[12..11]!=0b00.
8908 See 32-bit Thumb instruction encoding. */
8912 /* Compute the predicate that tells if the instruction
8913 is concerned by the IT block
8914 - Creates an error if there is a ldm that is not
8915 last in the IT block thus cannot be replaced
8916 - Otherwise we can create a branch at the end of the
8917 IT block, it will be controlled naturally by IT
8918 with the proper pseudo-predicate
8919 - So the only interesting predicate is the one that
8920 tells that we are not on the last item of an IT
8921 block. */
8926 {
8927 /* Load the rest of the insn (in manual-friendly order). */
8932 /* Veneers are created for (v)ldm depending on
8933 option flags and memory accesses conditions; but
8934 if the instruction is not the last instruction of
8935 an IT block, we cannot create a jump there, so we
8936 bail out. */
8938 && stm32l4xx_need_create_replacing_stub
8940 {
8942 {
8943 _bfd_error_handler
8944 /* xgettext:c-format */
8946 " in non-last IT block instruction:"
8947 " STM32L4XX veneer cannot be generated; "
8948 "use gcc option -mrestrict-it to generate"
8951 }
8952 else
8953 {
8956 bfd_zmalloc
8962 /* We create only thumb branches. */
8964 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8965 record_stm32l4xx_erratum_veneer
8967 i,
8968 is_ldm ?
8969 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8970 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8974 }
8975 }
8976 }
8977 else
8978 {
8979 /* A7.7.37 IT p208
8980 IT blocks are only encoded in T1
8981 Encoding T1: IT{x{y{z}}} <firstcond>
8982 1 0 1 1 - 1 1 1 1 - firstcond - mask
8983 if mask = '0000' then see 'related encodings'
8984 We don't deal with UNPREDICTABLE, just ignore these.
8985 There can be no nested IT blocks so an IT block
8986 is naturally a new one for which it is worth
8987 computing its size. */
8990 /* If we have a new IT block we compute its size. */
8992 {
8993 /* Compute the number of instructions controlled
8994 by the IT block, it will be used to decide
8995 whether we are inside an IT block or not. */
8998 }
8999 }
9002 }
9003 }
9009 }
9013 error_return:
9019 }
9021 /* Set target relocation values needed during linking. */
9023 void
9027 {
9043 else
9044 {
9047 }
9054 else
9066 }
9068 /* Replace the target offset of a Thumb bl or b.w instruction. */
9070 static void
9072 {
9073 bfd_vma upper;
9074 bfd_vma lower;
9091 }
9093 /* Thumb code calling an ARM function. */
9095 static int
9103 bfd_vma offset,
9104 bfd_signed_vma addend,
9105 bfd_vma val,
9107 {
9109 bfd_vma my_offset;
9125 THUMB2ARM_GLUE_SECTION_NAME);
9132 {
9136 {
9137 _bfd_error_handler
9143 }
9154 ret_offset =
9155 /* Address of destination of the stub. */
9158 /* Offset from the start of the current section
9159 to the start of the stubs. */
9161 /* Offset of the start of this stub from the start of the stubs. */
9162 + my_offset
9163 /* Address of the start of the current section. */
9165 /* The branch instruction is 4 bytes into the stub. */
9167 /* ARM branches work from the pc of the instruction + 8. */
9173 }
9177 /* Now go back and fix up the original BL insn to point to here. */
9178 ret_offset =
9179 /* Address of where the stub is located. */
9181 /* Address of where the BL is located. */
9184 /* Addend in the relocation. */
9185 - addend
9186 /* Biassing for PC-relative addressing. */
9192 }
9194 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9202 bfd_vma val,
9205 {
9206 bfd_vma my_offset;
9222 {
9226 {
9227 _bfd_error_handler
9231 }
9239 {
9240 /* For relocatable objects we can't use absolute addresses,
9241 so construct the address from a relative offset. */
9242 /* TODO: If the offset is small it's probably worth
9243 constructing the address with adds. */
9250 /* Adjust the offset by 4 for the position of the add,
9251 and 8 for the pipeline offset. */
9258 }
9260 {
9264 /* It's a thumb address. Add the low order bit. */
9267 }
9268 else
9269 {
9276 /* It's a thumb address. Add the low order bit. */
9281 }
9282 }
9287 }
9289 /* Arm code calling a Thumb function. */
9291 static int
9299 bfd_vma offset,
9300 bfd_signed_vma addend,
9301 bfd_vma val,
9303 {
9305 bfd_vma my_offset;
9316 ARM2THUMB_GLUE_SECTION_NAME);
9330 /* Somehow these are both 4 too far, so subtract 8. */
9332 + my_offset
9344 }
9346 /* Populate Arm stub for an exported Thumb function. */
9348 static bfd_boolean
9350 {
9357 bfd_vma val;
9361 /* Allocate stubs for exported Thumb functions on v4t. */
9370 ARM2THUMB_GLUE_SECTION_NAME);
9388 }
9390 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9392 static bfd_vma
9394 {
9396 bfd_vma glue_addr;
9405 ARM_BX_GLUE_SECTION_NAME);
9415 {
9421 }
9424 }
9426 /* Generate Arm stubs for exported Thumb symbols. */
9427 static void
9430 {
9434 /* Ignore this if we are not called by the ELF backend linker. */
9441 /* If blx is available then exported Thumb symbols are OK and there is
9442 nothing to do. */
9447 link_info);
9448 }
9450 /* Reserve space for COUNT dynamic relocations in relocation selection
9451 SRELOC. */
9453 static void
9455 bfd_size_type count)
9456 {
9464 }
9466 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9467 dynamic, the relocations should go in SRELOC, otherwise they should
9468 go in the special .rel.iplt section. */
9470 static void
9472 bfd_size_type count)
9473 {
9479 else
9480 {
9483 }
9484 }
9486 /* Add relocation REL to the end of relocation section SRELOC. */
9488 static void
9491 {
9506 }
9508 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9509 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9510 to .plt. */
9512 static void
9514 bfd_boolean is_iplt_entry,
9517 {
9525 {
9529 /* NaCl uses a special first entry in .iplt too. */
9533 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9535 }
9536 else
9537 {
9542 {
9543 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9544 /* For lazy binding, relocations will be put into .rel.plt, in
9545 .rel.got otherwise. */
9546 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9549 else
9551 }
9552 else
9553 {
9554 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9556 }
9558 /* If this is the first .plt entry, make room for the special
9559 first entry. */
9564 }
9566 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9573 {
9574 /* We also need to make an entry in the .got.plt section, which
9575 will be placed in the .got section by the linker script. */
9578 else
9581 /* Function descriptor takes 64 bits in GOT. */
9583 else
9585 }
9586 }
9588 static bfd_vma
9590 {
9592 }
9594 static bfd_vma
9596 {
9598 }
9600 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9601 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9602 Otherwise, DYNINDX is the index of the symbol in the dynamic
9603 symbol table and SYM_VALUE is undefined.
9605 ROOT_PLT points to the offset of the PLT entry from the start of its
9606 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9607 bookkeeping information.
9609 Returns FALSE if there was a problem. */
9611 static bfd_boolean
9616 {
9622 bfd_vma plt_index;
9623 Elf_Internal_Rela rel;
9624 bfd_vma plt_header_size;
9625 bfd_vma got_header_size;
9629 /* Pick the appropriate sections and sizes. */
9631 {
9636 /* There are no reserved entries in .igot.plt, and no special
9637 first entry in .iplt. */
9640 }
9641 else
9642 {
9649 }
9652 /* Fill in the entry in the procedure linkage table. */
9654 {
9663 /* Fill in the entry in the .rel.plt section. */
9669 /* Get the index in the procedure linkage table which
9670 corresponds to this symbol. This is the index of this symbol
9671 in all the symbols for which we are making plt entries. The
9672 first entry in the procedure linkage table is reserved. */
9675 }
9676 else
9677 {
9684 /* Get the offset into the .(i)got.plt table of the entry that
9685 corresponds to this function. */
9688 /* Get the index in the procedure linkage table which
9689 corresponds to this symbol. This is the index of this symbol
9690 in all the symbols for which we are making plt entries.
9691 After the reserved .got.plt entries, all symbols appear in
9692 the same order as in .plt. */
9694 /* Function descriptor takes 8 bytes. */
9696 else
9699 /* Calculate the address of the GOT entry. */
9704 /* ...and the address of the PLT entry. */
9711 {
9713 bfd_vma val;
9716 {
9724 else
9726 }
9727 }
9729 {
9731 bfd_vma val;
9734 {
9744 else
9746 }
9751 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9752 referencing the GOT for this PLT entry. */
9759 /* Create the R_ARM_ABS32 relocation referencing the
9760 beginning of the PLT for this GOT entry. */
9765 }
9767 {
9768 /* Calculate the displacement between the PLT slot and the
9769 common tail that's part of the special initial PLT slot. */
9770 int32_t tail_displacement
9780 /* Calculate the displacement between the PLT slot and the entry
9781 in the GOT. The offset accounts for the value produced by
9782 adding to pc in the penultimate instruction of the PLT stub. */
9783 got_displacement = (got_address
9786 /* NaCl does not support interworking at all. */
9804 }
9806 {
9808 ? elf32_arm_fdpic_thumb_plt_entry
9811 /* Fill-up Thumb stub if needed. */
9813 {
9818 }
9819 /* As we are using 32 bit instructions even for the Thumb
9820 version, we have to use 'put_arm_insn' instead of
9821 'put_thumb_insn'. */
9829 {
9830 /* funcdesc_value_reloc_offset. */
9838 }
9839 }
9841 {
9842 /* PR ld/16017: Generate thumb only PLT entries. */
9844 {
9845 /* FIXME: We ought to be able to generate thumb-1 PLT
9846 instructions... */
9848 output_bfd);
9850 }
9852 /* Calculate the displacement between the PLT slot and the entry in
9853 the GOT. The 12-byte offset accounts for the value produced by
9854 adding to pc in the 3rd instruction of the PLT stub. */
9857 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9858 instead of 'put_thumb_insn'. */
9879 }
9880 else
9881 {
9882 /* Calculate the displacement between the PLT slot and the
9883 entry in the GOT. The eight-byte offset accounts for the
9884 value produced by adding to pc in the first instruction
9885 of the PLT stub. */
9889 {
9894 }
9897 {
9912 #ifdef FOUR_WORD_PLT
9914 #endif
9915 }
9916 else
9917 {
9934 }
9935 }
9937 /* Fill in the entry in the .rel(a).(i)plt section. */
9941 {
9942 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9943 The dynamic linker or static executable then calls SYM_VALUE
9944 to determine the correct run-time value of the .igot.plt entry. */
9947 }
9948 else
9949 {
9950 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9951 used by PLT entry. */
9953 {
9956 }
9957 else
9958 {
9962 }
9963 }
9965 /* Fill in the entry in the global offset table. */
9970 {
9971 /* Setup initial funcdesc value. */
9972 /* FIXME: we don't support lazy binding because there is a
9973 race condition between both words getting written and
9974 some other thread attempting to read them. The ARM
9975 architecture does not have an atomic 64 bit load/store
9976 instruction that could be used to prevent it; it is
9977 recommended that threaded FDPIC applications run with the
9978 LD_BIND_NOW environment variable set. */
9983 }
9984 }
9988 else
9989 {
9991 {
9992 /* For FDPIC we put PLT relocationss into .rel.got when not
9993 lazy binding otherwise we put them in .rel.plt. For now,
9994 we don't support lazy binding so put it in .rel.got. */
9997 else
9999 }
10000 else
10001 {
10004 }
10005 }
10008 }
10010 /* Some relocations map to different relocations depending on the
10011 target. Return the real relocation. */
10013 static int
10016 {
10018 {
10022 else
10030 }
10031 }
10033 /* Return the base VMA address which should be subtracted from real addresses
10034 when resolving @dtpoff relocation.
10035 This is PT_TLS segment p_vaddr. */
10037 static bfd_vma
10039 {
10040 /* If tls_sec is NULL, we should have signalled an error already. */
10044 }
10046 /* Return the relocation value for @tpoff relocation
10047 if STT_TLS virtual address is ADDRESS. */
10049 static bfd_vma
10051 {
10053 bfd_vma base;
10055 /* If tls_sec is NULL, we should have signalled an error already. */
10060 }
10062 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10063 VALUE is the relocation value. */
10065 static bfd_reloc_status_type
10067 {
10074 }
10076 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10077 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10078 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10080 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10081 is to then call final_link_relocate. Return other values in the
10082 case of error.
10084 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10085 the pre-relaxed code. It would be nice if the relocs were updated
10086 to match the optimization. */
10088 static bfd_reloc_status_type
10092 {
10096 {
10103 else
10104 {
10108 else
10110 }
10115 /* Thumb insn. */
10118 {
10120 /* nop */
10122 }
10124 {
10126 /* nop */
10128 else
10129 /* ldr rx,[ry] */
10131 }
10133 {
10135 /* nop */
10137 else
10138 /* mov r0, rx */
10141 }
10142 else
10143 {
10145 /* It's a 32 bit instruction, fetch the rest of it for
10146 error generation. */
10149 _bfd_error_handler
10150 /* xgettext:c-format */
10156 }
10160 /* arm insn. */
10163 {
10165 /* mov rx, ry */
10168 }
10170 {
10172 /* nop */
10174 else
10175 /* ldr rx,[ry] */
10178 }
10180 {
10182 /* nop */
10184 else
10185 /* mov r0, rx */
10188 }
10189 else
10190 {
10191 _bfd_error_handler
10192 /* xgettext:c-format */
10198 }
10202 /* GD->IE relaxation, turn the instruction into 'nop' or
10203 'ldr r0, [pc,r0]' */
10209 /* GD->IE relaxation. */
10211 /* add r0,pc; ldr r0, [r0] */
10214 /* nop.w */
10216 else
10217 /* nop; nop */
10223 }
10225 }
10227 /* For a given value of n, calculate the value of G_n as required to
10228 deal with group relocations. We return it in the form of an
10229 encoded constant-and-rotation, together with the final residual. If n is
10230 specified as less than zero, then final_residual is filled with the
10231 input value and no further action is performed. */
10233 static bfd_vma
10235 {
10237 bfd_vma g_n;
10242 {
10245 /* Calculate which part of the value to mask. */
10248 else
10249 {
10252 /* Determine the most significant bit in the residual and
10253 align the resulting value to a 2-bit boundary. */
10258 /* The desired shift is now (msb - 6), or zero, whichever
10259 is the greater. */
10263 }
10265 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10270 /* Calculate the residual for the next time around. */
10272 }
10277 }
10279 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10280 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10282 static int
10284 {
10294 }
10296 /* Helper function to compute the Addend for Armv8.1-M Mainline relocations. */
10297 static bfd_vma
10310 {
10320 {
10326 }
10334 {
10338 stub_type);
10340 {
10344 }
10345 }
10347 }
10349 /* Perform a relocation as part of a final link. */
10351 static bfd_reloc_status_type
10358 bfd_vma value,
10367 {
10377 bfd_vma addend;
10378 bfd_signed_vma signed_addend;
10380 bfd_vma dynreloc_value;
10385 bfd_vma plt_offset;
10386 bfd_vma gotplt_offset;
10387 bfd_boolean has_iplt_entry;
10388 bfd_boolean resolved_to_zero;
10397 /* Some relocation types map to different relocations depending on the
10398 target. We pick the right one here. */
10401 /* It is possible to have linker relaxations on some TLS access
10402 models. Update our information here. */
10415 else
10421 {
10425 {
10429 }
10430 else
10432 }
10433 else
10436 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10437 are resolving a function call relocation. */
10444 /* Record the symbol information that should be used in dynamic
10445 relocations. */
10451 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10452 VALUE appropriately for relocations that we resolve at link time. */
10457 {
10462 {
10466 /* Populate .iplt entries here, because not all of them will
10467 be seen by finish_dynamic_symbol. The lower bit is set if
10468 we have already populated the entry. */
10470 plt_offset--;
10471 else
10472 {
10476 else
10478 }
10480 /* Static relocations always resolve to the .iplt entry. */
10487 /* If there are non-call relocations that resolve to the .iplt
10488 entry, then all dynamic ones must too. */
10490 {
10493 }
10494 }
10495 else
10496 /* We populate the .plt entry in finish_dynamic_symbol. */
10498 }
10499 else
10500 {
10504 }
10510 {
10512 /* We don't need to find a value for this symbol. It's just a
10513 marker. */
10520 /* Fall through. */
10532 /* Handle relocations which should use the PLT entry. ABS32/REL32
10533 will use the symbol's value, which may point to a PLT entry, but we
10534 don't need to handle that here. If we created a PLT entry, all
10535 branches in this object should go to it, except if the PLT is too
10536 far away, in which case a long branch stub should be inserted. */
10543 {
10544 /* If we've created a .plt section, and assigned a PLT entry
10545 to this function, it must either be a STT_GNU_IFUNC reference
10546 or not be known to bind locally. In other cases, we should
10547 have cleared the PLT entry by now. */
10557 }
10559 /* When generating a shared object or relocatable executable, these
10560 relocations are copied into the output file to be resolved at
10561 run time. */
10582 {
10583 Elf_Internal_Rela outrel;
10589 {
10595 _bfd_error_handler
10600 }
10605 {
10611 }
10636 else
10637 {
10640 /* This symbol is local, or marked to become local. */
10644 {
10647 /* On Symbian OS, the data segment and text segement
10648 can be relocated independently. Therefore, we
10649 must indicate the segment to which this
10650 relocation is relative. The BPABI allows us to
10651 use any symbol in the right segment; we just use
10652 the section symbol as it is convenient. (We
10653 cannot use the symbol given by "h" directly as it
10654 will not appear in the dynamic symbol table.)
10656 Note that the dynamic linker ignores the section
10657 symbol value, so we don't subtract osec->vma
10658 from the emitted reloc addend. */
10661 else
10665 {
10671 else
10674 }
10676 }
10677 else
10678 /* On SVR4-ish systems, the dynamic loader cannot
10679 relocate the text and data segments independently,
10680 so the symbol does not matter. */
10683 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10684 to the .iplt entry. Instead, every non-call reference
10685 must use an R_ARM_IRELATIVE relocation to obtain the
10686 correct run-time address. */
10690 else
10694 else
10696 }
10700 else
10703 /* If this reloc is against an external symbol, we do not want to
10704 fiddle with the addend. Otherwise, we need to include the symbol
10705 value so that it becomes an addend for the dynamic reloc. */
10712 }
10714 {
10723 {
10727 {
10728 /* Check for Arm calling Arm function. */
10729 /* FIXME: Should we translate the instruction into a BL
10730 instruction instead ? */
10732 _bfd_error_handler
10737 }
10739 {
10740 /* Check for Arm calling Thumb function. */
10742 {
10747 error_message))
10749 else
10751 }
10752 }
10754 /* Check if a stub has to be inserted because the
10755 destination is too far or we are changing mode. */
10759 {
10770 {
10771 /* The target is out of reach, so redirect the
10772 branch to the local stub for this function. */
10776 stub_type);
10777 {
10785 }
10786 }
10787 else
10788 {
10789 /* If the call goes through a PLT entry, make sure to
10790 check distance to the right destination address. */
10792 {
10797 /* The PLT entry is in ARM mode, regardless of the
10798 target function. */
10800 }
10801 }
10802 }
10804 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10805 where:
10806 S is the address of the symbol in the relocation.
10807 P is address of the instruction being relocated.
10808 A is the addend (extracted from the instruction) in bytes.
10810 S is held in 'value'.
10811 P is the base address of the section containing the
10812 instruction plus the offset of the reloc into that
10813 section, ie:
10814 (input_section->output_section->vma +
10815 input_section->output_offset +
10816 rel->r_offset).
10817 A is the addend, converted into bytes, ie:
10818 (signed_addend * 4)
10820 Note: None of these operations have knowledge of the pipeline
10821 size of the processor, thus it is up to the assembler to
10822 encode this information into the addend. */
10828 else
10829 /* RELA addends do not have to be adjusted by howto->size. */
10835 /* A branch to an undefined weak symbol is turned into a jump to
10836 the next instruction unless a PLT entry will be created.
10837 Do the same for local undefined symbols (but not for STN_UNDEF).
10838 The jump to the next instruction is optimized as a NOP depending
10839 on the architecture. */
10843 {
10848 else
10850 }
10851 else
10852 {
10853 /* Perform a signed range check. */
10864 {
10865 /* Set the H bit in the BLX instruction. */
10867 {
10870 else
10872 }
10874 /* Select the correct instruction (BL or BLX). */
10875 /* Only if we are not handling a BL to a stub. In this
10876 case, mode switching is performed by the stub. */
10880 {
10883 }
10884 }
10885 }
10886 }
10918 {
10919 /* Check for overflow. */
10922 }
10928 }
10934 /* PR 16202: Refectch the addend using the correct size. */
10939 /* There is no way to tell whether the user intended to use a signed or
10940 unsigned addend. When checking for overflow we accept either,
10941 as specified by the AAELF. */
10949 /* PR 16202: Refectch the addend using the correct size. */
10954 /* See comment for R_ARM_ABS8. */
10962 /* Support ldr and str instructions for the thumb. */
10964 {
10965 /* Need to refetch addend. */
10967 /* ??? Need to determine shift amount from operand size. */
10969 }
10972 /* ??? Isn't value unsigned? */
10976 /* ??? Value needs to be properly shifted into place first. */
10982 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10983 {
10984 bfd_vma insn;
10985 bfd_signed_vma relocation;
10991 {
10996 }
11003 /* PR 21523: Use an absolute value. The user of this reloc will
11004 have already selected an ADD or SUB insn appropriately. */
11010 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
11024 }
11027 /* PR 10073: This reloc is not generated by the GNU toolchain,
11028 but it is supported for compatibility with third party libraries
11029 generated by other compilers, specifically the ARM/IAR. */
11030 {
11031 bfd_vma insn;
11032 bfd_signed_vma relocation;
11046 /* We do not check for overflow of this reloc. Although strictly
11047 speaking this is incorrect, it appears to be necessary in order
11048 to work with IAR generated relocs. Since GCC and GAS do not
11049 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11050 a problem for them. */
11058 }
11061 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11062 {
11063 bfd_vma insn;
11064 bfd_signed_vma relocation;
11070 {
11074 }
11094 }
11099 /* Thumb BL (branch long instruction). */
11100 {
11101 bfd_vma relocation;
11102 bfd_vma reloc_sign;
11106 bfd_signed_vma reloc_signed_max;
11107 bfd_signed_vma reloc_signed_min;
11108 bfd_vma check;
11109 bfd_signed_vma signed_check;
11114 /* A branch to an undefined weak symbol is turned into a jump to
11115 the next instruction unless a PLT entry will be created.
11116 The jump to the next instruction is optimized as a NOP.W for
11117 Thumb-2 enabled architectures. */
11120 {
11122 {
11125 }
11126 else
11127 {
11130 }
11132 }
11134 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11135 with Thumb-1) involving the J1 and J2 bits. */
11137 {
11147 /* Sign extend. */
11151 }
11154 {
11155 /* Check for Thumb to Thumb call. */
11156 /* FIXME: Should we translate the instruction into a BL
11157 instruction instead ? */
11159 _bfd_error_handler
11164 }
11165 else
11166 {
11167 /* If it is not a call to Thumb, assume call to Arm.
11168 If it is a call relative to a section name, then it is not a
11169 function call at all, but rather a long jump. Calls through
11170 the PLT do not require stubs. */
11172 {
11174 {
11175 /* Convert BL to BLX. */
11177 }
11180 {
11184 error_message))
11186 else
11188 }
11189 }
11193 {
11194 /* Make sure this is a BL. */
11196 }
11197 }
11201 {
11202 /* Check if a stub has to be inserted because the destination
11203 is too far. */
11215 {
11216 /* The target is out of reach or we are changing modes, so
11217 redirect the branch to the local stub for this
11218 function. */
11222 stub_type);
11224 {
11231 }
11233 /* If this call becomes a call to Arm, force BLX. */
11235 {
11240 }
11241 }
11242 }
11244 /* Handle calls via the PLT. */
11246 {
11254 {
11255 /* If the Thumb BLX instruction is available, convert
11256 the BL to a BLX instruction to call the ARM-mode
11257 PLT entry. */
11260 }
11261 else
11262 {
11264 /* Target the Thumb stub before the ARM PLT entry. */
11267 }
11269 }
11279 /* If this is a signed value, the rightshift just dropped
11280 leading 1 bits (assuming twos complement). */
11283 else
11286 /* Calculate the permissable maximum and minimum values for
11287 this relocation according to whether we're relocating for
11288 Thumb-2 or not. */
11295 /* Assumes two's complement. */
11300 /* For a BLX instruction, make sure that the relocation is rounded up
11301 to a word boundary. This follows the semantics of the instruction
11302 which specifies that bit 1 of the target address will come from bit
11303 1 of the base address. */
11306 /* Put RELOCATION back into the insn. Assumes two's complement.
11307 We use the Thumb-2 encoding, which is safe even if dealing with
11308 a Thumb-1 instruction by virtue of our overflow check above. */
11318 /* Put the relocated value back in the object file: */
11323 }
11327 /* Thumb32 conditional branch instruction. */
11328 {
11329 bfd_vma relocation;
11335 bfd_signed_vma signed_check;
11340 /* Need to refetch the addend, reconstruct the top three bits,
11341 and squish the two 11 bit pieces together. */
11343 {
11357 }
11359 /* Handle calls via the PLT. */
11361 {
11365 /* Target the Thumb stub before the ARM PLT entry. */
11368 }
11377 {
11381 stub_type);
11383 {
11387 }
11388 }
11399 /* Put RELOCATION back into the insn. */
11400 {
11409 }
11411 /* Put the relocated value back in the object file: */
11416 }
11421 /* Thumb B (branch) instruction). */
11422 {
11423 bfd_signed_vma relocation;
11426 bfd_signed_vma signed_check;
11428 /* CZB cannot jump backward. */
11433 {
11434 /* Need to refetch addend. */
11437 {
11441 }
11442 else
11444 /* The value in the insn has been right shifted. We need to
11445 undo this, so that we can perform the address calculation
11446 in terms of bytes. */
11448 }
11460 else
11466 /* Assumes two's complement. */
11471 }
11476 {
11477 bfd_vma insn;
11478 bfd_vma relocation;
11482 {
11483 /* Extract the addend. */
11486 }
11496 }
11504 /* Relocation is relative to the start of the
11505 global offset table. */
11511 /* If we are addressing a Thumb function, we need to adjust the
11512 address by one, so that attempts to call the function pointer will
11513 correctly interpret it as Thumb code. */
11517 /* Note that sgot->output_offset is not involved in this
11518 calculation. We always want the start of .got. If we
11519 define _GLOBAL_OFFSET_TABLE in a different way, as is
11520 permitted by the ABI, we might have to change this
11521 calculation. */
11528 /* Use global offset table as symbol value. */
11542 /* Relocation is to the entry for this symbol in the
11543 global offset table. */
11550 {
11551 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11552 symbol, and the relocation resolves directly to the runtime
11553 target rather than to the .iplt entry. This means that any
11554 .got entry would be the same value as the .igot.plt entry,
11555 so there's no point creating both. */
11558 }
11560 {
11561 bfd_vma off;
11566 {
11567 /* We have already processsed one GOT relocation against
11568 this symbol. */
11573 }
11574 else
11575 {
11576 Elf_Internal_Rela outrel;
11581 {
11582 /* If the symbol doesn't resolve locally in a static
11583 object, we have an undefined reference. If the
11584 symbol doesn't resolve locally in a dynamic object,
11585 it should be resolved by the dynamic linker. */
11587 {
11590 }
11591 else
11594 }
11595 else
11596 {
11603 else
11604 {
11608 }
11610 }
11612 /* The GOT entry is initialized to zero by default.
11613 See if we should install a different value. */
11616 {
11620 }
11629 {
11634 }
11637 }
11639 }
11640 else
11641 {
11642 bfd_vma off;
11649 /* The offset must always be a multiple of 4. We use the
11650 least significant bit to record whether we have already
11651 generated the necessary reloc. */
11654 else
11655 {
11656 Elf_Internal_Rela outrel;
11663 else
11664 {
11668 }
11670 /* The GOT entry is initialized to zero by default.
11671 See if we should install a different value. */
11682 {
11688 }
11691 }
11694 }
11711 {
11712 bfd_vma off;
11721 else
11722 {
11723 /* If we don't know the module number, create a relocation
11724 for it. */
11726 {
11727 Elf_Internal_Rela outrel;
11742 }
11743 else
11747 }
11750 {
11756 }
11757 else
11758 {
11766 }
11767 }
11778 {
11786 {
11787 bfd_boolean dyn;
11791 h)
11794 {
11797 }
11801 }
11802 else
11803 {
11808 }
11810 /* Linker relaxations happens from one of the
11811 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11819 else
11820 {
11822 Elf_Internal_Rela outrel;
11825 /* The GOT entries have not been initialized yet. Do it
11826 now, and emit any relocations. If both an IE GOT and a
11827 GD GOT are necessary, we emit the GD first. */
11834 {
11837 }
11840 {
11843 /* We should have relaxed, unless this is an undefined
11844 weak symbol. */
11853 + offplt
11865 /* For globals, the first word in the relocation gets
11866 the relocation index and the top bit set, or zero,
11867 if we're binding now. For locals, it gets the
11868 symbol's offset in the tls section. */
11876 /* Second word in the relocation is always zero. */
11880 }
11882 {
11884 {
11900 else
11901 {
11904 R_ARM_TLS_DTPOFF32);
11913 }
11914 }
11915 else
11916 {
11917 /* If we are not emitting relocations for a
11918 general dynamic reference, then we must be in a
11919 static link or an executable link with the
11920 symbol binding locally. Mark it as belonging
11921 to module 1, the executable. */
11926 }
11929 }
11932 {
11934 {
11937 else
11949 }
11950 else
11954 }
11958 else
11960 }
11969 {
11970 bfd_signed_vma offset;
11971 /* TLS stubs are arm mode. The original symbol is a
11972 data object, so branch_type is bogus. */
11974 enum elf32_arm_stub_type stub_type
11982 {
11984 = elf32_arm_get_stub_entry
11990 }
11991 else
11997 {
12007 }
12008 else
12009 {
12010 /* Thumb blx encodes the offset in a complicated
12011 fashion. */
12021 {
12023 }
12024 else
12025 {
12027 /* Round up the offset to a word boundary. */
12029 }
12041 }
12042 }
12043 /* These relocations needs special care, as besides the fact
12044 they point somewhere in .gotplt, the addend must be
12045 adjusted accordingly depending on the type of instruction
12046 we refer to. */
12048 {
12057 {
12064 /* bl/blx */
12067 /* add */
12069 else
12070 {
12071 _bfd_error_handler
12072 /* xgettext:c-format */
12074 "unexpected %s instruction '%#lx' "
12079 }
12080 }
12081 else
12082 {
12086 {
12097 _bfd_error_handler
12098 /* xgettext:c-format */
12100 "unexpected %s instruction '%#lx' "
12105 }
12106 }
12114 }
12115 else
12123 {
12124 /* For FDPIC relocations, resolve to the offset of the GOT
12125 entry from the start of GOT. */
12131 }
12132 else
12133 {
12137 }
12138 }
12142 {
12143 _bfd_error_handler
12144 /* xgettext:c-format */
12149 }
12150 else
12159 {
12162 /* Ensure that we have a BX instruction. */
12166 {
12167 /* Branch to veneer. */
12168 bfd_vma glue_addr;
12175 }
12176 else
12177 {
12178 /* Preserve Rm (lowest four bits) and the condition code
12179 (highest four bits). Other bits encode MOV PC,Rm. */
12181 }
12184 }
12191 /* Until we properly support segment-base-relative addressing then
12192 we assume the segment base to be zero, as for the group relocations.
12193 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12194 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12198 {
12202 {
12205 }
12227 }
12234 /* Until we properly support segment-base-relative addressing then
12235 we assume the segment base to be zero, as for the above relocations.
12236 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12237 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12238 as R_ARM_THM_MOVT_ABS. */
12242 {
12243 bfd_vma insn;
12249 {
12255 }
12281 }
12294 {
12298 /* sb is the origin of the *segment* containing the symbol. */
12300 bfd_vma residual;
12301 bfd_vma g_n;
12302 bfd_signed_vma signed_value;
12305 /* Determine which group of bits to select. */
12307 {
12329 }
12331 /* If REL, extract the addend from the insn. If RELA, it will
12332 have already been fetched for us. */
12334 {
12341 else
12342 {
12343 /* Compensate for the fact that in the instruction, the
12344 rotation is stored in multiples of 2 bits. */
12347 /* Rotate "constant" right by "rotation" bits. */
12350 }
12352 /* Determine if the instruction is an ADD or a SUB.
12353 (For REL, this determines the sign of the addend.) */
12356 {
12357 _bfd_error_handler
12358 /* xgettext:c-format */
12363 }
12366 }
12368 /* Compute the value (X) to go in the place. */
12374 /* PC relative. */
12376 else
12377 /* Section base relative. */
12380 /* If the target symbol is a Thumb function, then set the
12381 Thumb bit in the address. */
12385 /* Calculate the value of the relevant G_n, in encoded
12386 constant-with-rotation format. */
12390 /* Check for overflow if required. */
12397 {
12398 _bfd_error_handler
12399 /* xgettext:c-format */
12406 }
12408 /* Mask out the value and the ADD/SUB part of the opcode; take care
12409 not to destroy the S bit. */
12412 /* Set the opcode according to whether the value to go in the
12413 place is negative. */
12416 else
12419 /* Encode the offset. */
12423 }
12432 {
12436 /* sb is the origin of the *segment* containing the symbol. */
12438 bfd_vma residual;
12439 bfd_signed_vma signed_value;
12442 /* Determine which groups of bits to calculate. */
12444 {
12462 }
12464 /* If REL, extract the addend from the insn. If RELA, it will
12465 have already been fetched for us. */
12467 {
12470 }
12472 /* Compute the value (X) to go in the place. */
12476 /* PC relative. */
12478 else
12479 /* Section base relative. */
12482 /* Calculate the value of the relevant G_{n-1} to obtain
12483 the residual at that stage. */
12487 /* Check for overflow. */
12489 {
12490 _bfd_error_handler
12491 /* xgettext:c-format */
12498 }
12500 /* Mask out the value and U bit. */
12503 /* Set the U bit if the value to go in the place is non-negative. */
12507 /* Encode the offset. */
12511 }
12520 {
12524 /* sb is the origin of the *segment* containing the symbol. */
12526 bfd_vma residual;
12527 bfd_signed_vma signed_value;
12530 /* Determine which groups of bits to calculate. */
12532 {
12550 }
12552 /* If REL, extract the addend from the insn. If RELA, it will
12553 have already been fetched for us. */
12555 {
12558 }
12560 /* Compute the value (X) to go in the place. */
12564 /* PC relative. */
12566 else
12567 /* Section base relative. */
12570 /* Calculate the value of the relevant G_{n-1} to obtain
12571 the residual at that stage. */
12575 /* Check for overflow. */
12577 {
12578 _bfd_error_handler
12579 /* xgettext:c-format */
12586 }
12588 /* Mask out the value and U bit. */
12591 /* Set the U bit if the value to go in the place is non-negative. */
12595 /* Encode the offset. */
12599 }
12608 {
12612 /* sb is the origin of the *segment* containing the symbol. */
12614 bfd_vma residual;
12615 bfd_signed_vma signed_value;
12618 /* Determine which groups of bits to calculate. */
12620 {
12638 }
12640 /* If REL, extract the addend from the insn. If RELA, it will
12641 have already been fetched for us. */
12643 {
12646 }
12648 /* Compute the value (X) to go in the place. */
12652 /* PC relative. */
12654 else
12655 /* Section base relative. */
12658 /* Calculate the value of the relevant G_{n-1} to obtain
12659 the residual at that stage. */
12663 /* Check for overflow. (The absolute value to go in the place must be
12664 divisible by four and, after having been divided by four, must
12665 fit in eight bits.) */
12667 {
12668 _bfd_error_handler
12669 /* xgettext:c-format */
12676 }
12678 /* Mask out the value and U bit. */
12681 /* Set the U bit if the value to go in the place is non-negative. */
12685 /* Encode the offset. */
12689 }
12696 {
12702 /* Compute address. */
12708 /* Clean imm8 insn. */
12710 /* And update with correct part of address. */
12712 /* Update insn. */
12714 }
12720 {
12722 {
12732 /* Resolve relocation. */
12735 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12736 not done yet. */
12740 }
12741 else
12742 {
12745 bfd_vma addr;
12748 /* For static binaries, sym_sec can be null. */
12750 {
12753 }
12754 else
12755 {
12758 }
12763 /* This case cannot occur since funcdesc is allocated by
12764 the dynamic loader so we cannot resolve the relocation. */
12768 /* Resolve relocation. */
12771 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12775 }
12776 }
12781 {
12783 {
12784 Elf_Internal_Rela outrel;
12786 /* Resolve relocation. */
12790 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12792 {
12795 bfd_vma addr;
12798 /* For static binaries sym_sec can be null. */
12800 {
12803 }
12804 else
12805 {
12808 }
12810 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12814 }
12816 /* Add a dynamic relocation on GOT entry if not already done. */
12818 {
12820 {
12825 else
12829 sgot->contents
12831 }
12832 else
12833 {
12835 }
12843 else
12846 else
12849 }
12850 }
12851 else
12852 {
12853 /* Such relocation on static function should not have been
12854 emitted by the compiler. */
12856 }
12857 }
12862 {
12864 {
12866 Elf_Internal_Rela outrel;
12875 /* Replace static FUNCDESC relocation with a
12876 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12877 executable. */
12884 else
12890 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12894 }
12895 else
12896 {
12898 {
12901 bfd_vma addr;
12903 Elf_Internal_Rela outrel;
12905 /* For static binaries sym_sec can be null. */
12907 {
12910 }
12911 else
12912 {
12915 }
12920 /* Replace static FUNCDESC relocation with a
12921 R_ARM_RELATIVE dynamic relocation. */
12928 else
12934 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12938 }
12939 else
12940 {
12941 Elf_Internal_Rela outrel;
12943 /* Add a dynamic relocation. */
12949 }
12950 }
12951 }
12956 {
12957 bfd_vma relocation;
12962 {
12970 /* Sign extend. */
12972 }
12983 /* Put RELOCATION back into the insn. */
12984 {
12991 }
12993 /* Put the relocated value back in the object file: */
12998 }
13001 {
13002 bfd_vma relocation;
13007 {
13015 /* Sign extend. */
13017 }
13028 /* Put RELOCATION back into the insn. */
13029 {
13036 }
13038 /* Put the relocated value back in the object file: */
13043 }
13046 {
13047 bfd_vma relocation;
13052 {
13060 /* Sign extend. */
13062 }
13073 /* Put RELOCATION back into the insn. */
13074 {
13081 }
13083 /* Put the relocated value back in the object file: */
13088 }
13092 }
13093 }
13095 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13096 static void
13100 bfd_signed_vma increment)
13101 {
13102 bfd_signed_vma addend;
13106 {
13124 }
13125 else
13126 {
13127 bfd_vma contents;
13131 /* Get the (signed) value from the instruction. */
13134 {
13135 bfd_signed_vma mask;
13140 }
13142 /* Add in the increment, (which is a byte value). */
13144 {
13156 /* Should we check for overflow here ? */
13158 /* Drop any undesired bits. */
13161 }
13166 }
13167 }
13169 #define IS_ARM_TLS_RELOC(R_TYPE) \
13170 ((R_TYPE) == R_ARM_TLS_GD32 \
13171 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
13172 || (R_TYPE) == R_ARM_TLS_LDO32 \
13173 || (R_TYPE) == R_ARM_TLS_LDM32 \
13174 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
13175 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13176 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13177 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13178 || (R_TYPE) == R_ARM_TLS_LE32 \
13179 || (R_TYPE) == R_ARM_TLS_IE32 \
13180 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
13181 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13183 /* Specific set of relocations for the gnu tls dialect. */
13184 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13185 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13186 || (R_TYPE) == R_ARM_TLS_CALL \
13187 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13188 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13189 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
13191 /* Relocate an ARM ELF section. */
13193 static bfd_boolean
13202 {
13220 {
13227 bfd_vma relocation;
13228 bfd_reloc_status_type r;
13229 arelent bfd_reloc;
13252 {
13257 /* An object file might have a reference to a local
13258 undefined symbol. This is a daft object file, but we
13259 should at least do something about it. V4BX & NONE
13260 relocations do not use the symbol and are explicitly
13261 allowed to use the undefined symbol, so allow those.
13262 Likewise for relocations against STN_UNDEF. */
13275 {
13282 {
13287 {
13309 {
13310 _bfd_error_handler
13311 /* xgettext:c-format */
13317 }
13321 /* Get the (signed) value from the instruction. */
13324 {
13325 bfd_signed_vma mask;
13330 }
13332 }
13335 addend =
13340 /* Cases here must match those in the preceding
13341 switch statement. */
13343 {
13366 }
13367 }
13368 }
13369 else
13371 }
13372 else
13373 {
13382 }
13389 {
13390 /* This is a relocatable link. We don't have to change
13391 anything, unless the reloc is against a section symbol,
13392 in which case we have to adjust according to where the
13393 section symbol winds up in the output section. */
13395 {
13399 else
13401 }
13403 }
13407 else
13408 {
13409 name = (bfd_elf_string_from_elf_section
13413 }
13421 {
13422 _bfd_error_handler
13424 /* xgettext:c-format */
13426 /* xgettext:c-format */
13428 input_bfd,
13429 input_section,
13432 name);
13433 }
13435 /* We call elf32_arm_final_link_relocate unless we're completely
13436 done, i.e., the relaxation produced the final output we want,
13437 and we won't let anybody mess with it. Also, we have to do
13438 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13439 both in relaxed and non-relaxed cases. */
13445 {
13448 /* This may have been marked unresolved because it came from
13449 a shared library. But we've just dealt with that. */
13451 }
13452 else
13456 {
13467 }
13469 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13470 because such sections are not SEC_ALLOC and thus ld.so will
13471 not process them. */
13477 {
13478 _bfd_error_handler
13479 /* xgettext:c-format */
13482 input_bfd,
13483 input_section,
13488 }
13491 {
13493 {
13495 /* If the overflowing reloc was to an undefined symbol,
13496 we have already printed one error message and there
13497 is no point complaining again. */
13518 /* error_message should already be set. */
13523 /* Fall through. */
13525 common_error:
13530 }
13531 }
13532 }
13535 }
13537 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13538 adds the edit to the start of the list. (The list must be built in order of
13539 ascending TINDEX: the function's callers are primarily responsible for
13540 maintaining that condition). */
13542 static void
13545 arm_unwind_edit_type type,
13548 {
13557 {
13567 }
13568 else
13569 {
13576 }
13577 }
13581 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13582 static void
13584 {
13592 /* Adjust size of output section. */
13594 }
13596 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13597 static void
13599 {
13611 }
13613 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13614 made to those tables, such that:
13616 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13617 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13618 codes which have been inlined into the index).
13620 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13622 The edits are applied when the tables are written
13623 (in elf32_arm_write_section). */
13625 bfd_boolean
13629 bfd_boolean merge_exidx_entries)
13630 {
13637 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13638 text sections. */
13640 {
13644 {
13652 {
13653 Elf_Internal_Shdr *linked_hdr
13661 /* Link this .ARM.exidx section back from the text section it
13662 describes. */
13664 }
13665 }
13666 }
13668 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13669 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13670 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13673 {
13680 bfd_vma j;
13691 {
13692 /* Section has no unwind data. */
13696 /* Ignore zero sized sections. */
13703 }
13705 /* Skip /DISCARD/ sections. */
13722 /* An error? */
13726 {
13728 /* Add cantunwind if first unwind item does not match section
13729 start. */
13731 {
13734 }
13735 }
13738 {
13743 /* An EXIDX_CANTUNWIND entry. */
13745 {
13749 }
13750 /* Inlined unwinding data. Merge if equal to previous. */
13752 {
13758 }
13759 /* Normal table entry. In theory we could merge these too,
13760 but duplicate entries are likely to be much less common. */
13761 else
13765 {
13770 }
13773 }
13775 /* Free contents if we allocated it ourselves. */
13779 /* Record edits to be applied later (in elf32_arm_write_section). */
13788 }
13790 /* Add terminating CANTUNWIND entry. */
13796 }
13798 static bfd_boolean
13801 {
13817 }
13819 static bfd_boolean
13821 {
13828 /* Invoke the regular ELF backend linker to do all the work. */
13832 /* Process stub sections (eg BE8 encoding, ...). */
13836 {
13838 /* Only process it once, in its link_sec slot. */
13840 {
13846 }
13847 }
13849 /* Write out any glue sections now that we have created all the
13850 stubs. */
13852 {
13855 ARM2THUMB_GLUE_SECTION_NAME))
13860 THUMB2ARM_GLUE_SECTION_NAME))
13865 VFP11_ERRATUM_VENEER_SECTION_NAME))
13870 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13875 ARM_BX_GLUE_SECTION_NAME))
13877 }
13880 }
13882 /* Return a best guess for the machine number based on the attributes. */
13884 static unsigned int
13886 {
13890 {
13897 {
13904 {
13912 {
13918 {
13922 }
13923 }
13924 }
13927 }
13959 /* Force entry to be added for any new known Tag_CPU_arch value. */
13962 /* Unknown Tag_CPU_arch value. */
13964 }
13965 }
13967 /* Set the right machine number. */
13969 static bfd_boolean
13971 {
13977 {
13980 else
13982 }
13986 }
13988 /* Function to keep ARM specific flags in the ELF header. */
13990 static bfd_boolean
13992 {
13995 {
13997 {
13999 _bfd_error_handler
14000 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
14001 abfd);
14002 else
14003 _bfd_error_handler
14005 abfd);
14006 }
14007 }
14008 else
14009 {
14012 }
14015 }
14017 /* Copy backend specific data from one object module to another. */
14019 static bfd_boolean
14021 {
14022 flagword in_flags;
14023 flagword out_flags;
14034 {
14035 /* Cannot mix APCS26 and APCS32 code. */
14039 /* Cannot mix float APCS and non-float APCS code. */
14043 /* If the src and dest have different interworking flags
14044 then turn off the interworking bit. */
14046 {
14048 _bfd_error_handler
14049 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
14053 }
14055 /* Likewise for PIC, though don't warn for this case. */
14058 }
14064 }
14066 /* Values for Tag_ABI_PCS_R9_use. */
14067 enum
14068 {
14069 AEABI_R9_V6,
14070 AEABI_R9_SB,
14071 AEABI_R9_TLS,
14072 AEABI_R9_unused
14073 };
14075 /* Values for Tag_ABI_PCS_RW_data. */
14076 enum
14077 {
14078 AEABI_PCS_RW_data_absolute,
14079 AEABI_PCS_RW_data_PCrel,
14080 AEABI_PCS_RW_data_SBrel,
14081 AEABI_PCS_RW_data_unused
14082 };
14084 /* Values for Tag_ABI_enum_size. */
14085 enum
14086 {
14087 AEABI_enum_unused,
14088 AEABI_enum_short,
14089 AEABI_enum_wide,
14090 AEABI_enum_forced_wide
14091 };
14093 /* Determine whether an object attribute tag takes an integer, a
14094 string or both. */
14096 static int
14098 {
14107 else
14109 }
14111 /* The ABI defines that Tag_conformance should be emitted first, and that
14112 Tag_nodefaults should be second (if either is defined). This sets those
14113 two positions, and bumps up the position of all the remaining tags to
14114 compensate. */
14115 static int
14117 {
14127 }
14129 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
14130 static bfd_boolean
14132 {
14134 {
14135 _bfd_error_handler
14140 }
14141 else
14142 {
14143 _bfd_error_handler
14147 }
14148 }
14150 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
14151 Returns -1 if no architecture could be read. */
14153 static int
14155 {
14159 /* Note: the tag and its argument below are uleb128 values, though
14160 currently-defined values fit in one byte for each. */
14167 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14169 }
14171 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14172 The tag is removed if ARCH is -1. */
14174 static void
14176 {
14181 {
14184 }
14186 /* Note: the tag and its argument below are uleb128 values, though
14187 currently-defined values fit in one byte for each. */
14193 }
14195 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14196 into account. */
14198 static int
14201 {
14202 #define T(X) TAG_CPU_ARCH_##X
14205 {
14215 };
14217 {
14228 };
14230 {
14242 };
14244 {
14257 };
14259 {
14273 };
14275 {
14290 };
14292 {
14308 };
14310 {
14327 };
14329 {
14347 };
14349 {
14368 };
14370 {
14393 };
14395 {
14419 };
14421 {
14422 v6t2,
14423 v6k,
14424 v7,
14425 v6_m,
14426 v6s_m,
14427 v7e_m,
14428 v8,
14429 v8r,
14430 v8m_baseline,
14431 v8m_mainline,
14432 NULL,
14433 NULL,
14434 NULL,
14435 v8_1m_mainline,
14436 /* Pseudo-architecture. */
14437 v4t_plus_v6_m
14438 };
14440 /* Check we've not got a higher architecture than we know about. */
14443 {
14446 }
14448 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14454 /* And override the new tag if we have a Tag_also_compatible_with on the
14455 input. */
14464 /* Architectures before V6KZ add features monotonically. */
14470 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14471 as the canonical version. */
14473 {
14476 }
14477 else
14481 {
14485 }
14488 #undef T
14489 }
14491 /* Query attributes object to see if integer divide instructions may be
14492 present in an object. */
14493 static bfd_boolean
14495 {
14500 {
14502 /* Integer divide allowed if instruction contained in archetecture. */
14507 else
14511 /* Integer divide explicitly prohibited. */
14515 /* Unrecognised case - treat as allowing divide everywhere. */
14517 /* Integer divide allowed in ARM state. */
14519 }
14520 }
14522 /* Query attributes object to see if integer divide instructions are
14523 forbidden to be in the object. This is not the inverse of
14524 elf32_arm_attributes_accept_div. */
14525 static bfd_boolean
14527 {
14529 }
14531 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14532 are conflicting attributes. */
14534 static bfd_boolean
14536 {
14540 /* Some tags have 0 = don't care, 1 = strong requirement,
14541 2 = weak requirement. */
14547 /* Skip the linker stubs file. This preserves previous behavior
14548 of accepting unknown attributes in the first input file - but
14549 is that a bug? */
14553 /* Skip any input that hasn't attribute section.
14554 This enables to link object files without attribute section with
14555 any others. */
14560 {
14561 /* This is the first object. Copy the attributes. */
14566 /* Use the Tag_null value to indicate the attributes have been
14567 initialized. */
14570 /* We do not output objects with Tag_MPextension_use_legacy - we move
14571 the attribute's value to Tag_MPextension_use. */
14573 {
14577 {
14578 _bfd_error_handler
14582 }
14588 }
14591 }
14595 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14597 {
14598 /* Ignore mismatches if the object doesn't use floating point or is
14599 floating point ABI independent. */
14606 {
14607 _bfd_error_handler
14612 }
14613 }
14616 {
14617 /* Merge this attribute with existing attributes. */
14619 {
14622 /* These are merged after Tag_CPU_arch. */
14627 /* Use the first value seen. */
14631 {
14636 {
14637 /* These aren't real CPU names, but we can't guess
14638 that from the architecture version alone. */
14656 };
14658 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14664 secondary_compat);
14666 /* Return with error if failed to merge. */
14674 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14678 {
14679 /* The output architecture has been changed to match the
14680 input architecture. Use the input names. */
14687 }
14688 else
14689 {
14692 }
14694 /* If we still don't have a value for Tag_CPU_name,
14695 make one up now. Tag_CPU_raw_name remains blank. */
14700 }
14707 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14717 /* Use the largest value specified. */
14724 /* Use the smallest value specified. */
14733 {
14734 /* This error message should be enabled once all non-conformant
14735 binaries in the toolchain have had the attributes set
14736 properly.
14737 _bfd_error_handler
14738 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14739 obfd, ibfd);
14740 result = FALSE; */
14741 }
14742 /* Fall through. */
14745 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14746 value if greater than 2 (for future-proofing). */
14754 /* The virtualization tag effectively stores two bits of
14755 information: the intended use of TrustZone (in bit 0), and the
14756 intended use of Virtualization (in bit 1). */
14761 {
14764 else
14765 {
14766 _bfd_error_handler
14771 }
14772 }
14777 {
14778 /* 0 will merge with anything.
14779 'A' and 'S' merge to 'A'.
14780 'R' and 'S' merge to 'R'.
14781 'M' and 'A|R|S' is an error. */
14790 else
14791 {
14792 _bfd_error_handler
14794 ibfd,
14798 }
14799 }
14803 /* No need to change output value if any of:
14804 - pre (<=) ARMv5T input architecture (do not have DSP)
14805 - M input profile not ARMv7E-M and do not have DSP. */
14811 /* Output value should be 0 if DSP part of architecture, ie.
14812 - post (>=) ARMv5te architecture output
14813 - A, R or S profile output or ARMv7E-M output architecture. */
14820 /* Otherwise, DSP instructions are added and not part of output
14821 architecture. */
14822 else
14827 {
14828 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14829 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14830 when it's 0. It might mean absence of FP hardware if
14831 Tag_FP_arch is zero. */
14833 #define VFP_VERSION_COUNT 9
14834 static const struct
14835 {
14839 {
14849 };
14854 /* If the output has no requirement about FP hardware,
14855 follow the requirement of the input. */
14857 {
14858 /* This assert is still reasonable, we shouldn't
14859 produce the suspicious build attribute
14860 combination (See below for in_attr). */
14866 }
14867 /* If the input has no requirement about FP hardware, do
14868 nothing. */
14870 {
14871 /* We used to assert that Tag_ABI_HardFP_use was
14872 zero here, but we should never assert when
14873 consuming an object file that has suspicious
14874 build attributes. The single precision variant
14875 of 'no FP architecture' is still 'no FP
14876 architecture', so we just ignore the tag in this
14877 case. */
14879 }
14881 /* Both the input and the output have nonzero Tag_FP_arch.
14882 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14884 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14885 do nothing. */
14888 ;
14889 /* If the input and the output have different Tag_ABI_HardFP_use,
14890 the combination of them is 0 (implied by Tag_FP_arch). */
14895 /* Now we can handle Tag_FP_arch. */
14897 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14898 pick the biggest. */
14901 {
14904 }
14905 /* The output uses the superset of input features
14906 (ISA version) and registers. */
14913 /* This assumes all possible supersets are also a valid
14914 options. */
14916 {
14920 }
14922 }
14928 {
14929 /* It's sometimes ok to mix different configs, so this is only
14930 a warning. */
14931 _bfd_error_handler
14933 }
14939 {
14940 _bfd_error_handler
14943 }
14951 {
14952 _bfd_error_handler
14954 ibfd);
14956 }
14957 /* Use the smallest value specified. */
14964 {
14965 _bfd_error_handler
14966 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
14968 }
14974 {
14977 {
14978 /* The existing object is compatible with anything.
14979 Use whatever requirements the new object has. */
14981 }
14985 {
14996 _bfd_error_handler
14997 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
14999 }
15000 }
15003 /* Aready done. */
15007 {
15008 _bfd_error_handler
15012 }
15015 /* Merged in target-independent code. */
15018 /* This is handled along with Tag_FP_arch. */
15022 {
15024 {
15025 _bfd_error_handler
15029 }
15030 }
15036 /* A value of zero on input means that the divide instruction may
15037 be used if available in the base architecture as specified via
15038 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15039 the user did not want divide instructions. A value of 2
15040 explicitly means that divide instructions were allowed in ARM
15041 and Thumb state. */
15055 /* We don't output objects with Tag_MPextension_use_legacy - we
15056 move the value to Tag_MPextension_use. */
15058 {
15060 {
15061 _bfd_error_handler
15064 ibfd);
15066 }
15067 }
15075 /* This tag is set if it exists, but the value is unused (and is
15076 typically zero). We don't actually need to do anything here -
15077 the merge happens automatically when the type flags are merged
15078 below. */
15081 /* Already done in Tag_CPU_arch. */
15084 /* Keep the attribute if it matches. Throw it away otherwise.
15085 No attribute means no claim to conform. */
15092 result
15094 }
15096 /* If out_attr was copied from in_attr then it won't have a type yet. */
15099 }
15101 /* Merge Tag_compatibility attributes and any common GNU ones. */
15105 /* Check for any attributes not known on ARM. */
15109 }
15112 /* Return TRUE if the two EABI versions are incompatible. */
15114 static bfd_boolean
15116 {
15117 /* v4 and v5 are the same spec before and after it was released,
15118 so allow mixing them. */
15124 }
15126 /* Merge backend specific data from an object file to the output
15127 object file when linking. */
15129 static bfd_boolean
15132 /* Display the flags field. */
15134 static bfd_boolean
15136 {
15142 /* Print normal ELF private data. */
15146 /* Ignore init flag - it may not be set, despite the flags field
15147 containing valid data. */
15152 {
15154 /* The following flag bits are GNU extensions and not part of the
15155 official ARM ELF extended ABI. Hence they are only decoded if
15156 the EABI version is not set. */
15162 else
15169 else
15198 else
15209 else
15241 eabi:
15254 }
15275 }
15277 static int
15279 {
15281 {
15286 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15287 This allows us to distinguish between data used by Thumb instructions
15288 and non-data (which is probably code) inside Thumb regions of an
15289 executable. */
15296 }
15299 }
15307 {
15310 {
15314 }
15317 }
15319 /* Look through the relocs for a section during the first phase. */
15321 static bfd_boolean
15324 {
15332 bfd_boolean call_reloc_p;
15333 bfd_boolean may_become_dynamic_p;
15334 bfd_boolean may_need_local_target_p;
15348 /* Create dynamic sections for relocatable executables so that we can
15349 copy relocations. */
15352 {
15355 }
15370 {
15382 /* PR 9934: It is possible to have relocations that do not
15383 refer to symbols, thus it is also possible to have an
15384 object file containing relocations but no symbol table. */
15386 {
15388 r_symndx);
15390 }
15395 {
15397 {
15398 /* A local symbol. */
15403 }
15404 else
15405 {
15410 }
15411 }
15419 /* Could be done earlier, if h were already available. */
15422 {
15424 {
15426 {
15431 }
15432 else
15433 {
15435 }
15436 }
15440 {
15442 {
15443 /* Such a relocation is not supposed to be generated
15444 by gcc on a static function. */
15445 /* Anyway if needed it could be handled. */
15447 }
15448 else
15449 {
15451 }
15452 }
15456 {
15458 {
15463 }
15464 else
15465 {
15467 }
15468 }
15482 /* This symbol requires a global offset table entry. */
15483 {
15487 {
15500 }
15506 {
15509 }
15510 else
15511 {
15512 /* This is a global offset table entry for a local symbol. */
15517 }
15519 /* If a variable is accessed with both tls methods, two
15520 slots may be created. */
15525 /* We will already have issued an error message if there
15526 is a TLS/non-TLS mismatch, based on the symbol
15527 type. So just combine any TLS types needed. */
15532 /* If the symbol is accessed in both IE and GDESC
15533 method, we're able to relax. Turn off the GDESC flag,
15534 without messing up with any other kind of tls types
15535 that may be involved. */
15540 {
15543 else
15545 }
15546 }
15547 /* Fall through. */
15553 /* Fall through. */
15575 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15576 ldr __GOTT_INDEX__ offsets. */
15578 {
15581 }
15584 /* Fall through. */
15591 {
15592 _bfd_error_handler
15593 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15598 }
15600 /* Fall through. */
15603 jump_over:
15605 {
15607 }
15608 /* Fall through. */
15616 /* Should the interworking branches be listed here? */
15620 {
15623 {
15624 /* In shared libraries and relocatable executables,
15625 we treat local relative references as calls;
15626 see the related SYMBOL_CALLS_LOCAL code in
15627 allocate_dynrelocs. */
15630 }
15631 else
15632 /* We are creating a shared library or relocatable
15633 executable, and this is a reloc against a global symbol,
15634 or a non-PC-relative reloc against a local symbol.
15635 We may need to copy the reloc into the output. */
15637 }
15638 else
15642 /* This relocation describes the C++ object vtable hierarchy.
15643 Reconstruct it for later use during GC. */
15649 /* This relocation describes which C++ vtable entries are actually
15650 used. Record for later use during GC. */
15655 }
15658 {
15660 /* We may need a .plt entry if the function this reloc
15661 refers to is in a different object, regardless of the
15662 symbol's type. We can't tell for sure yet, because
15663 something later might force the symbol local. */
15666 /* If this reloc is in a read-only section, we might
15667 need a copy reloc. We can't check reliably at this
15668 stage whether the section is read-only, as input
15669 sections have not yet been mapped to output sections.
15670 Tentatively set the flag for now, and correct in
15671 adjust_dynamic_symbol. */
15673 }
15677 {
15683 {
15686 }
15687 else
15688 {
15694 }
15696 /* If the symbol is a function that doesn't bind locally,
15697 this relocation will need a PLT entry. */
15704 /* It's too early to use htab->use_blx here, so we have to
15705 record possible blx references separately from
15706 relocs that definitely need a thumb stub. */
15714 }
15717 {
15720 /* Create a reloc section in dynobj. */
15722 {
15723 sreloc = _bfd_elf_make_dynamic_reloc_section
15729 /* BPABI objects never have dynamic relocations mapped. */
15731 {
15732 flagword flags;
15737 }
15738 }
15740 /* If this is a global symbol, count the number of
15741 relocations we need for this symbol. */
15744 else
15745 {
15749 }
15753 {
15764 }
15771 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15772 that will become rofixup. */
15773 /* This is due to the fact that we suppose all will become rofixup. */
15774 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15775 _bfd_error_handler
15780 }
15781 }
15782 }
15785 }
15787 static void
15790 {
15812 {
15815 }
15817 {
15820 }
15821 else
15833 {
15836 {
15839 irela++;
15840 count++;
15841 }
15843 {
15847 bfd_size_type j;
15848 bfd_vma offset;
15864 else
15868 {
15870 {
15872 bfd_vma bias;
15873 bfd_vma reloc_index;
15883 {
15884 bias++;
15886 }
15890 {
15892 irela++;
15893 count++;
15894 }
15897 }
15900 {
15901 /* New relocation entity. */
15910 irela++;
15911 count++;
15912 }
15913 }
15914 else
15915 {
15917 {
15920 irela++;
15921 }
15924 }
15925 }
15926 }
15934 {
15937 irela++;
15938 count--;
15939 }
15943 /* Hashes are no longer valid. */
15946 }
15948 /* Unwinding tables are not referenced directly. This pass marks them as
15949 required if the corresponding code section is marked. Similarly, ARMv8-M
15950 secure entry functions can only be referenced by SG veneers which are
15951 created after the GC process. They need to be marked in case they reside in
15952 their own section (as would be the case if code was compiled with
15953 -ffunction-sections). */
15955 static bfd_boolean
15957 elf_gc_mark_hook_fn gc_mark_hook)
15958 {
15976 /* Marking EH data may cause additional code sections to be marked,
15977 requiring multiple passes. */
15980 {
15983 {
15991 {
16000 {
16004 }
16005 }
16007 /* Mark section holding ARMv8-M secure entry functions. We mark all
16008 of them so no need for a second browsing. */
16010 {
16017 /* Scan symbols. */
16019 {
16022 /* Assume it is a special symbol. If not, cmse_scan will
16023 warn about it and user can do something about it. */
16025 {
16030 }
16031 }
16032 }
16033 }
16035 }
16038 }
16040 /* Treat mapping symbols as special target symbols. */
16042 static bfd_boolean
16044 {
16046 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
16047 }
16049 /* This is a copy of elf_find_function() from elf.c except that
16050 ARM mapping symbols are ignored when looking for function names
16051 and STT_ARM_TFUNC is considered to a function type. */
16053 static bfd_boolean
16057 bfd_vma offset,
16060 {
16067 {
16073 {
16082 /* Skip mapping symbols. */
16085 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16087 /* Fall through. */
16091 {
16094 }
16096 }
16097 }
16108 }
16111 /* Find the nearest line to a particular section and offset, for error
16112 reporting. This code is a duplicate of the code in elf.c, except
16113 that it uses arm_elf_find_function. */
16115 static bfd_boolean
16119 bfd_vma offset,
16124 {
16132 {
16136 functionname_ptr);
16139 }
16141 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
16142 uses DWARF1. */
16162 }
16164 static bfd_boolean
16169 {
16170 bfd_boolean found;
16175 }
16177 /* Find dynamic relocs for H that apply to read-only sections. */
16181 {
16185 {
16190 }
16192 }
16194 /* Adjust a symbol defined by a dynamic object and referenced by a
16195 regular object. The current definition is in some section of the
16196 dynamic object, but we're not including those sections. We have to
16197 change the definition to something the rest of the link can
16198 understand. */
16200 static bfd_boolean
16203 {
16215 /* Make sure we know what is going on here. */
16226 /* If this is a function, put it in the procedure linkage table. We
16227 will fill in the contents of the procedure linkage table later,
16228 when we know the address of the .got section. */
16230 {
16231 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16232 symbol binds locally. */
16238 {
16239 /* This case can occur if we saw a PLT32 reloc in an input
16240 file, but the symbol was never referred to by a dynamic
16241 object, or if all references were garbage collected. In
16242 such a case, we don't actually need to build a procedure
16243 linkage table, and we can just do a PC24 reloc instead. */
16249 }
16252 }
16253 else
16254 {
16255 /* It's possible that we incorrectly decided a .plt reloc was
16256 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16257 in check_relocs. We can't decide accurately between function
16258 and non-function syms in check-relocs; Objects loaded later in
16259 the link may change h->type. So fix it now. */
16264 }
16266 /* If this is a weak symbol, and there is a real definition, the
16267 processor independent code will have arranged for us to see the
16268 real definition first, and we can just use the same value. */
16270 {
16276 }
16278 /* If there are no non-GOT references, we do not need a copy
16279 relocation. */
16283 /* This is a reference to a symbol defined by a dynamic object which
16284 is not a function. */
16286 /* If we are creating a shared library, we must presume that the
16287 only references to the symbol are via the global offset table.
16288 For such cases we need not do anything here; the relocations will
16289 be handled correctly by relocate_section. Relocatable executables
16290 can reference data in shared objects directly, so we don't need to
16291 do anything here. */
16295 /* We must allocate the symbol in our .dynbss section, which will
16296 become part of the .bss section of the executable. There will be
16297 an entry for this symbol in the .dynsym section. The dynamic
16298 object will contain position independent code, so all references
16299 from the dynamic object to this symbol will go through the global
16300 offset table. The dynamic linker will use the .dynsym entry to
16301 determine the address it must put in the global offset table, so
16302 both the dynamic object and the regular object will refer to the
16303 same memory location for the variable. */
16304 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16305 linker to copy the initial value out of the dynamic object and into
16306 the runtime process image. We need to remember the offset into the
16307 .rel(a).bss section we are going to use. */
16309 {
16312 }
16313 else
16314 {
16317 }
16321 {
16324 }
16327 }
16329 /* Allocate space in .plt, .got and associated reloc sections for
16330 dynamic relocs. */
16332 static bfd_boolean
16334 {
16352 {
16353 /* Make sure this symbol is output as a dynamic symbol.
16354 Undefined weak syms won't yet be marked as dynamic. */
16357 {
16360 }
16362 /* If the call in the PLT entry binds locally, the associated
16363 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16364 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16365 than the .plt section. */
16367 {
16371 /* All non-call references can be resolved directly.
16372 This means that they can (and in some cases, must)
16373 resolve directly to the run-time target, rather than
16374 to the PLT. That in turns means that any .got entry
16375 would be equal to the .igot.plt entry, so there's
16376 no point having both. */
16378 }
16383 {
16386 /* If this symbol is not defined in a regular file, and we are
16387 not generating a shared library, then set the symbol to this
16388 location in the .plt. This is required to make function
16389 pointers compare as equal between the normal executable and
16390 the shared library. */
16393 {
16397 /* Make sure the function is not marked as Thumb, in case
16398 it is the target of an ABS32 relocation, which will
16399 point to the PLT entry. */
16401 }
16403 /* VxWorks executables have a second set of relocations for
16404 each PLT entry. They go in a separate relocation section,
16405 which is processed by the kernel loader. */
16407 {
16408 /* There is a relocation for the initial PLT entry:
16409 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16413 /* There are two extra relocations for each subsequent
16414 PLT entry: an R_ARM_32 relocation for the GOT entry,
16415 and an R_ARM_32 relocation for the PLT entry. */
16417 }
16418 }
16419 else
16420 {
16423 }
16424 }
16425 else
16426 {
16429 }
16435 {
16437 bfd_boolean dyn;
16441 /* Make sure this symbol is output as a dynamic symbol.
16442 Undefined weak syms won't yet be marked as dynamic. */
16445 {
16448 }
16451 {
16459 /* Non-TLS symbols need one GOT slot. */
16461 else
16462 {
16464 {
16465 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16466 eh->tlsdesc_got
16471 /* plt.got_offset needs to know there's a TLS_DESC
16472 reloc in the middle of .got.plt. */
16474 }
16477 {
16478 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16479 consecutive GOT slots. If the symbol is both GD
16480 and GDESC, got.offset may have been
16481 overwritten. */
16484 }
16487 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16488 slot. */
16490 }
16497 h)
16506 {
16514 {
16516 /* GDESC needs a trampoline to jump to. */
16518 }
16520 /* Only GD needs it. GDESC just emits one relocation per
16521 2 entries. */
16524 }
16527 {
16529 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16531 }
16534 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16535 they all resolve dynamically instead. Reserve room for the
16536 GOT entry's R_ARM_IRELATIVE relocation. */
16541 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16544 /* Reserve room for rofixup for FDPIC executable. */
16545 /* TLS relocs do not need space since they are completely
16546 resolved. */
16548 }
16549 }
16550 else
16553 /* FDPIC support. */
16555 {
16556 /* Symbol musn't be exported. */
16560 /* We only allocate one function descriptor with its associated relocation. */
16562 {
16567 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16570 else
16572 }
16573 }
16576 {
16585 {
16586 /* We only allocate one function descriptor with its associated relocation. q */
16588 {
16592 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16595 else
16597 }
16598 }
16600 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16601 R_ARM_RELATIVE/rofixup relocation on it. */
16606 else
16608 }
16611 {
16618 {
16619 /* We only allocate one function descriptor with its associated relocation. */
16621 {
16626 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16629 else
16631 }
16632 }
16634 {
16635 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16637 }
16638 else
16639 {
16640 /* Will need one dynamic reloc per reference. will be either
16641 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16644 }
16645 }
16647 /* Allocate stubs for exported Thumb functions on v4t. */
16652 {
16659 /* Create a new symbol to regist the real location of the function. */
16673 /* Point the symbol at the stub. */
16678 }
16683 /* In the shared -Bsymbolic case, discard space allocated for
16684 dynamic pc-relative relocs against symbols which turn out to be
16685 defined in regular objects. For the normal shared case, discard
16686 space for pc-relative relocs that have become local due to symbol
16687 visibility changes. */
16690 {
16691 /* Relocs that use pc_count are PC-relative forms, which will appear
16692 on something like ".long foo - ." or "movw REG, foo - .". We want
16693 calls to protected symbols to resolve directly to the function
16694 rather than going via the plt. If people want function pointer
16695 comparisons to work as expected then they should avoid writing
16696 assembly like ".long foo - .". */
16698 {
16702 {
16707 else
16709 }
16710 }
16713 {
16717 {
16720 else
16722 }
16723 }
16725 /* Also discard relocs on undefined weak syms with non-default
16726 visibility. */
16729 {
16734 /* Make sure undefined weak symbols are output as a dynamic
16735 symbol in PIEs. */
16738 {
16741 }
16742 }
16746 {
16747 /* Output absolute symbols so that we can create relocations
16748 against them. For normal symbols we output a relocation
16749 against the section that contains them. */
16752 }
16754 }
16755 else
16756 {
16757 /* For the non-shared case, discard space for relocs against
16758 symbols which turn out to need copy relocs or are not
16759 dynamic. */
16767 {
16768 /* Make sure this symbol is output as a dynamic symbol.
16769 Undefined weak syms won't yet be marked as dynamic. */
16772 {
16775 }
16777 /* If that succeeded, we know we'll be keeping all the
16778 relocs. */
16781 }
16785 keep: ;
16786 }
16788 /* Finally, allocate space. */
16790 {
16801 else
16803 }
16806 }
16808 /* Set DF_TEXTREL if we find any dynamic relocs that apply to
16809 read-only sections. */
16811 static bfd_boolean
16813 {
16821 {
16829 /* Not an error, just cut short the traversal. */
16831 }
16834 }
16836 void
16839 {
16847 }
16849 /* Set the sizes of the dynamic sections. */
16851 static bfd_boolean
16854 {
16857 bfd_boolean plt;
16858 bfd_boolean relocs;
16871 {
16872 /* Set the contents of the .interp section to the interpreter. */
16874 {
16879 }
16880 }
16882 /* Set up .got offsets for local syms, and space for local dynamic
16883 relocs. */
16885 {
16891 bfd_size_type locsymcount;
16902 {
16907 {
16910 {
16911 /* Input section has been discarded, either because
16912 it is a copy of a linkonce section or due to
16913 linker script /DISCARD/, so we'll be discarding
16914 the relocs too. */
16915 }
16919 {
16920 /* Relocations in vxworks .tls_vars sections are
16921 handled specially by the loader. */
16922 }
16924 {
16928 else
16932 }
16933 }
16934 }
16953 {
16957 /* FDPIC support. */
16959 {
16961 {
16965 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16968 else
16970 }
16971 }
16974 {
16976 {
16980 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16983 else
16985 }
16987 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16990 else
16992 }
16995 {
16999 {
17004 /* All references to the PLT are calls, so all
17005 non-call references can resolve directly to the
17006 run-time target. This means that the .got entry
17007 would be the same as the .igot.plt entry, so there's
17008 no point creating both. */
17010 }
17011 else
17012 {
17015 }
17018 {
17024 else
17026 }
17027 }
17029 {
17034 /* TLS_GD relocs need an 8-byte structure in the GOT. */
17037 {
17042 /* plt.got_offset needs to know there's a TLS_DESC
17043 reloc in the middle of .got.plt. */
17045 }
17050 {
17051 /* If the symbol is both GD and GDESC, *local_got
17052 may have been overwritten. */
17055 }
17061 /* If all references to an STT_GNU_IFUNC PLT are calls,
17062 then all non-call references, including this GOT entry,
17063 resolve directly to the run-time target. */
17069 {
17077 {
17081 }
17082 }
17083 }
17084 else
17086 }
17087 }
17090 {
17091 /* Allocate two GOT entries and one dynamic relocation (if necessary)
17092 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
17097 }
17098 else
17101 /* At the very end of the .rofixup section is a pointer to the GOT,
17102 reserve space for it. */
17106 /* Allocate global sym .plt and .got entries, and space for global
17107 sym dynamic relocs. */
17110 /* Here we rummage through the found bfds to collect glue information. */
17112 {
17116 /* Initialise mapping tables for code/data. */
17123 }
17125 /* Allocate space for the glue sections now that we've sized them. */
17128 /* For every jump slot reserved in the sgotplt, reloc_count is
17129 incremented. However, when we reserve space for TLS descriptors,
17130 it's not incremented, so in order to compute the space reserved
17131 for them, it suffices to multiply the reloc count by the jump
17132 slot size. */
17137 {
17144 /* If we're not using lazy TLS relocations, don't generate the
17145 PLT and GOT entries they require. */
17147 {
17153 }
17154 }
17156 /* The check_relocs and adjust_dynamic_symbol entry points have
17157 determined the sizes of the various dynamic sections. Allocate
17158 memory for them. */
17162 {
17168 /* It's OK to base decisions on the section name, because none
17169 of the dynobj section names depend upon the input files. */
17173 {
17174 /* Remember whether there is a PLT. */
17176 }
17178 {
17180 {
17181 /* Remember whether there are any reloc sections other
17182 than .rel(a).plt and .rela.plt.unloaded. */
17186 /* We use the reloc_count field as a counter if we need
17187 to copy relocs into the output file. */
17189 }
17190 }
17198 {
17199 /* It's not one of our sections, so don't allocate space. */
17201 }
17204 {
17205 /* If we don't need this section, strip it from the
17206 output file. This is mostly to handle .rel(a).bss and
17207 .rel(a).plt. We must create both sections in
17208 create_dynamic_sections, because they must be created
17209 before the linker maps input sections to output
17210 sections. The linker does that before
17211 adjust_dynamic_symbol is called, and it is that
17212 function which decides whether anything needs to go
17213 into these sections. */
17216 }
17221 /* Allocate memory for the section contents. */
17225 }
17228 {
17229 /* Add some entries to the .dynamic section. We fill in the
17230 values later, in elf32_arm_finish_dynamic_sections, but we
17231 must add the entries now so that we get the correct size for
17232 the .dynamic section. The DT_DEBUG entry is filled in by the
17233 dynamic linker and used by the debugger. */
17234 #define add_dynamic_entry(TAG, VAL) \
17235 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
17238 {
17241 }
17244 {
17256 }
17259 {
17261 {
17266 }
17267 else
17268 {
17273 }
17274 }
17276 /* If any dynamic relocs apply to a read-only section,
17277 then we need a DT_TEXTREL entry. */
17282 {
17285 }
17289 }
17290 #undef add_dynamic_entry
17293 }
17295 /* Size sections even though they're not dynamic. We use it to setup
17296 _TLS_MODULE_BASE_, if needed. */
17298 static bfd_boolean
17301 {
17313 {
17316 tlsbase = elf_link_hash_lookup
17320 {
17336 }
17337 }
17345 }
17347 /* Finish up dynamic symbol handling. We set the contents of various
17348 dynamic sections here. */
17350 static bfd_boolean
17355 {
17366 {
17368 {
17373 }
17376 {
17377 /* Mark the symbol as undefined, rather than as defined in
17378 the .plt section. */
17380 /* If the symbol is weak we need to clear the value.
17381 Otherwise, the PLT entry would provide a definition for
17382 the symbol even if the symbol wasn't defined anywhere,
17383 and so the symbol would never be NULL. Leave the value if
17384 there were any relocations where pointer equality matters
17385 (this is a clue for the dynamic linker, to make function
17386 pointer comparisons work between an application and shared
17387 library). */
17390 }
17392 {
17393 /* At least one non-call relocation references this .iplt entry,
17394 so the .iplt entry is the function's canonical address. */
17402 }
17403 }
17406 {
17408 Elf_Internal_Rela rel;
17410 /* This symbol needs a copy reloc. Set it up. */
17422 else
17425 }
17427 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17428 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17429 it is relative to the ".got" section. */
17435 }
17437 static void
17441 {
17445 {
17448 /* Emit mov pc,rx if bx is not permitted. */
17452 }
17453 }
17455 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17456 other variants, NaCl needs this entry in a static executable's
17457 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17458 zero. For .iplt really only the last bundle is useful, and .iplt
17459 could have a shorter first entry, with each individual PLT entry's
17460 relative branch calculated differently so it targets the last
17461 bundle instead of the instruction before it (labelled .Lplt_tail
17462 above). But it's simpler to keep the size and layout of PLT0
17463 consistent with the dynamic case, at the cost of some dead code at
17464 the start of .iplt and the one dead store to the stack at the start
17465 of .Lplt_tail. */
17466 static void
17469 {
17485 }
17487 /* Finish up the dynamic sections. */
17489 static bfd_boolean
17491 {
17504 /* A broken linker script might have discarded the dynamic sections.
17505 Catch this here so that we do not seg-fault later on. */
17511 {
17523 {
17524 Elf_Internal_Dyn dyn;
17531 {
17564 get_vma:
17567 {
17568 _bfd_error_handler
17572 }
17575 else
17576 /* In the BPABI, tags in the PT_DYNAMIC section point
17577 at the file offset, not the memory address, for the
17578 convenience of the post linker. */
17583 get_vma_if_bpabi:
17599 /* In the BPABI, the DT_REL tag must point at the file
17600 offset, not the VMA, of the first relocation
17601 section. So, we use code similar to that in
17602 elflink.c, but do not check for SHF_ALLOC on the
17603 relocation section, since relocation sections are
17604 never allocated under the BPABI. PLT relocs are also
17605 included. */
17607 {
17613 {
17614 Elf_Internal_Shdr *hdr
17617 {
17624 }
17625 }
17627 }
17644 /* Set the bottom bit of DT_INIT/FINI if the
17645 corresponding function is Thumb. */
17651 get_sym:
17652 /* If it wasn't set by elf_bfd_final_link
17653 then there is nothing to adjust. */
17655 {
17663 {
17666 }
17667 }
17669 }
17670 }
17672 /* Fill in the first entry in the procedure linkage table. */
17674 {
17678 /* Calculate the addresses of the GOT and PLT. */
17683 {
17684 /* The VxWorks GOT is relocated by the dynamic linker.
17685 Therefore, we must emit relocations rather than simply
17686 computing the values now. */
17687 Elf_Internal_Rela rel;
17698 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17704 }
17709 {
17721 }
17722 else
17723 {
17736 #ifdef FOUR_WORD_PLT
17737 /* The displacement value goes in the otherwise-unused
17738 last word of the second entry. */
17740 #else
17742 #endif
17743 }
17744 }
17746 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17747 really seem like the right value. */
17752 {
17753 bfd_vma got_address
17757 bfd_vma plt_address
17773 }
17776 {
17780 #ifdef FOUR_WORD_PLT
17783 #endif
17784 }
17789 {
17790 /* Correct the .rel(a).plt.unloaded relocations. They will have
17791 incorrect symbol indexes. */
17800 {
17801 Elf_Internal_Rela rel;
17812 }
17813 }
17814 }
17817 /* NaCl uses a special first entry in .iplt too. */
17820 /* Fill in the first three entries in the global offset table. */
17822 {
17824 {
17827 else
17833 }
17836 }
17838 /* At the very end of the .rofixup section is a pointer to the GOT. */
17840 {
17849 /* Make sure we allocated and generated the same number of fixups. */
17851 }
17854 }
17856 static void
17857 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
17858 {
17867 else
17872 {
17879 }
17883 {
17887 else
17889 }
17891 /* Scan segment to set p_flags attribute if it contains only sections with
17892 SHF_ARM_PURECODE flag. */
17894 {
17900 {
17903 }
17905 {
17908 }
17909 }
17910 }
17912 static enum elf_reloc_type_class
17916 {
17918 {
17929 }
17930 }
17932 static void
17934 {
17936 }
17938 /* Return TRUE if this is an unwinding table entry. */
17940 static bfd_boolean
17942 {
17945 }
17948 /* Set the type and flags for an ARM section. We do this by
17949 the section name, which is a hack, but ought to work. */
17951 static bfd_boolean
17953 {
17959 {
17962 }
17968 }
17970 /* Handle an ARM specific section when reading an object file. This is
17971 called when bfd_section_from_shdr finds a section with an unknown
17972 type. */
17974 static bfd_boolean
17979 {
17980 /* There ought to be a place to keep ELF backend specific flags, but
17981 at the moment there isn't one. We just keep track of the
17982 sections by their name, instead. Fortunately, the ABI gives
17983 names for all the ARM specific sections, so we will probably get
17984 away with this. */
17986 {
17994 }
18000 }
18004 {
18007 else
18009 }
18012 {
18021 enum map_symbol_type
18022 {
18023 ARM_MAP_ARM,
18024 ARM_MAP_THUMB,
18025 ARM_MAP_DATA
18026 };
18029 /* Output a single mapping symbol. */
18031 static bfd_boolean
18034 bfd_vma offset)
18035 {
18037 Elf_Internal_Sym sym;
18049 }
18051 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
18052 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
18054 static bfd_boolean
18056 bfd_boolean is_iplt_entry_p,
18059 {
18071 {
18074 }
18075 else
18076 {
18079 }
18085 {
18090 }
18092 {
18101 }
18103 {
18106 }
18108 {
18110 ? ARM_MAP_THUMB
18123 }
18125 {
18128 }
18129 else
18130 {
18131 bfd_boolean thumb_stub_p;
18135 {
18138 }
18139 #ifdef FOUR_WORD_PLT
18144 #else
18145 /* A three-word PLT with no Thumb thunk contains only Arm code,
18146 so only need to output a mapping symbol for the first PLT entry and
18147 entries with thumb thunks. */
18149 {
18152 }
18153 #endif
18154 }
18157 }
18159 /* Output mapping symbols for PLT entries associated with H. */
18161 static bfd_boolean
18163 {
18171 /* When warning symbols are created, they **replace** the "real"
18172 entry in the hash table, thus we never get to see the real
18173 symbol in a hash traversal. So look at it now. */
18179 }
18181 /* Bind a veneered symbol to its veneer identified by its hash entry
18182 STUB_ENTRY. The veneered location thus loose its symbol. */
18184 static void
18186 {
18193 }
18195 /* Output a single local symbol for a generated stub. */
18197 static bfd_boolean
18200 {
18201 Elf_Internal_Sym sym;
18212 }
18214 static bfd_boolean
18217 {
18220 bfd_vma addr;
18229 /* Massage our args to the form they really have. */
18235 /* Ensure this stub is attached to the current section being
18236 processed. */
18245 else
18246 {
18249 {
18264 }
18265 }
18270 {
18272 {
18289 }
18292 {
18296 }
18299 {
18316 }
18317 }
18320 }
18322 /* Output mapping symbols for linker generated sections,
18323 and for those data-only sections that do not have a
18324 $d. */
18326 static bfd_boolean
18331 Elf_Internal_Sym *,
18332 asection *,
18334 {
18335 output_arch_syminfo osi;
18337 bfd_vma offset;
18338 bfd_size_type size;
18351 /* Add a $d mapping symbol to data-only sections that
18352 don't have any mapping symbol. This may result in (harmless) redundant
18353 mapping symbols. */
18357 {
18362 {
18367 == SEC_HAS_CONTENTS
18372 {
18377 }
18378 }
18379 }
18381 /* ARM->Thumb glue. */
18383 {
18385 ARM2THUMB_GLUE_SECTION_NAME);
18394 else
18398 {
18401 }
18402 }
18404 /* Thumb->ARM glue. */
18406 {
18408 THUMB2ARM_GLUE_SECTION_NAME);
18415 {
18418 }
18419 }
18421 /* ARMv4 BX veneers. */
18423 {
18425 ARM_BX_GLUE_SECTION_NAME);
18431 }
18433 /* Long calls stubs. */
18435 {
18441 {
18442 /* Ignore non-stub sections. */
18452 }
18453 }
18455 /* Finally, output mapping symbols for the PLT. */
18457 {
18462 /* Output mapping symbols for the plt header. SymbianOS does not have a
18463 plt header. */
18465 {
18466 /* VxWorks shared libraries have no PLT header. */
18468 {
18473 }
18474 }
18476 {
18479 }
18481 {
18488 }
18490 {
18493 #ifndef FOUR_WORD_PLT
18496 #endif
18497 }
18498 }
18500 {
18501 /* NaCl uses a special first entry in .iplt too. */
18507 }
18510 {
18515 {
18521 {
18529 }
18530 }
18531 }
18533 {
18534 /* Mapping symbols for the lazy tls trampoline. */
18541 }
18543 {
18544 /* Mapping symbols for the tls trampoline. */
18547 #ifdef FOUR_WORD_PLT
18551 #endif
18552 }
18555 }
18557 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18558 the import library. All SYMCOUNT symbols of ABFD can be examined
18559 from their pointers in SYMS. Pointers of symbols to keep should be
18560 stored continuously at the beginning of that array.
18562 Returns the number of symbols to keep. */
18564 static unsigned int
18568 {
18581 {
18584 flagword flags;
18599 {
18603 }
18618 }
18624 }
18626 /* Filter symbols of ABFD to include in the import library. All
18627 SYMCOUNT symbols of ABFD can be examined from their pointers in
18628 SYMS. Pointers of symbols to keep should be stored continuously at
18629 the beginning of that array.
18631 Returns the number of symbols to keep. */
18633 static unsigned int
18637 {
18640 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18641 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18642 library to be a relocatable object file. */
18646 else
18648 }
18650 /* Allocate target specific section data. */
18652 static bfd_boolean
18654 {
18656 {
18664 }
18667 }
18670 /* Used to order a list of mapping symbols by address. */
18672 static int
18674 {
18683 /* Ensure results do not depend on the host qsort for objects with
18684 multiple mapping symbols at the same address by sorting on type
18685 after vma. */
18689 else
18691 }
18693 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18695 static unsigned long
18697 {
18699 }
18701 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18702 relocations. */
18704 static void
18706 {
18710 /* High bit of first word is supposed to be zero. */
18714 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18715 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18721 }
18723 /* Data for make_branch_to_a8_stub(). */
18725 struct a8_branch_to_stub_data
18726 {
18729 };
18732 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18733 places for a particular section. */
18735 static bfd_boolean
18738 {
18744 bfd_signed_vma branch_offset;
18757 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18758 generated when both source and target are in the same section. */
18775 /* We attempt to avoid this condition by setting stubs_always_after_branch
18776 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18777 This check is just to be on the safe side... */
18779 {
18783 }
18786 {
18797 {
18802 jump24:
18804 {
18805 /* There's not much we can do apart from complain if this
18806 happens. */
18810 }
18812 /* i1 = not(j1 eor s), so:
18813 not i1 = j1 eor s
18814 j1 = (not i1) eor s. */
18826 }
18832 }
18838 }
18840 /* Beginning of stm32l4xx work-around. */
18842 /* Functions encoding instructions necessary for the emission of the
18843 fix-stm32l4xx-629360.
18844 Encoding is extracted from the
18845 ARM (C) Architecture Reference Manual
18846 ARMv7-A and ARMv7-R edition
18847 ARM DDI 0406C.b (ID072512). */
18851 {
18852 /* A8.8.18 B (A8-334)
18853 B target_address (Encoding T4). */
18854 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18855 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18856 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18873 }
18877 {
18878 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18879 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18886 }
18890 {
18891 /* A8.8.60 LDMDB/LDMEA (A8-402)
18892 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18899 }
18903 {
18904 /* A8.8.103 MOV (register) (A8-486)
18905 MOV Rd, Rm (Encoding T1). */
18912 }
18916 {
18917 /* A8.8.221 SUB (immediate) (A8-708)
18918 SUB Rd, Rn, #value (Encoding T3). */
18928 }
18933 {
18934 /* A8.8.332 VLDM (A8-922)
18935 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18944 }
18949 {
18950 /* A8.8.332 VLDM (A8-922)
18951 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18959 }
18963 {
18964 /* A8.8.247 UDF (A8-758)
18965 Undefined (Encoding T2). */
18971 }
18975 {
18976 /* A8.8.247 UDF (A8-758)
18977 Undefined (Encoding T1). */
18982 }
18984 /* Functions writing an instruction in memory, returning the next
18985 memory position to write to. */
18990 {
18993 }
18998 {
19001 }
19003 /* Function filling up a region in memory with T1 and T2 UDFs taking
19004 care of alignment. */
19012 {
19015 /* Fill the remaining of the stub with deterministic contents : UDF
19016 instructions.
19017 Check if realignment is needed on modulo 4 frontier using T1, to
19018 further use T2. */
19022 current_stub_contents =
19027 current_stub_contents =
19032 }
19034 /* Functions writing the stream of instructions equivalent to the
19035 derived sequence for ldmia, ldmdb, vldm respectively. */
19037 static void
19043 {
19056 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19057 smaller than 8 registers load sequences that do not cause the
19058 hardware issue. */
19060 {
19061 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19062 current_stub_contents =
19064 initial_insn);
19066 /* B initial_insn_addr+4. */
19068 current_stub_contents =
19070 create_instruction_branch_absolute
19073 /* Fill the remaining of the stub with deterministic contents. */
19074 current_stub_contents =
19077 base_stub_contents +
19078 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19081 }
19083 /* - reg_list[13] == 0. */
19086 /* - reg_list[14] & reg_list[15] != 1. */
19089 /* - if (wback==1) reg_list[rn] == 0. */
19092 /* - nb_registers > 8. */
19095 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19097 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19098 - One with the 7 lowest registers (register mask 0x007F)
19099 This LDM will finally contain between 2 and 7 registers
19100 - One with the 7 highest registers (register mask 0xDF80)
19101 This ldm will finally contain between 2 and 7 registers. */
19105 /* A spare register may be needed during this veneer to temporarily
19106 handle the base register. This register will be restored with the
19107 last LDM operation.
19108 The usable register may be any general purpose register (that
19109 excludes PC, SP, LR : register mask is 0x1FFF). */
19112 /* Generate the stub function. */
19114 {
19115 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19116 current_stub_contents =
19118 create_instruction_ldmia
19121 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19122 current_stub_contents =
19124 create_instruction_ldmia
19127 {
19128 /* B initial_insn_addr+4. */
19129 current_stub_contents =
19131 create_instruction_branch_absolute
19133 }
19134 }
19136 {
19139 /* If Rn is not part of the high-register-list, move it there. */
19141 {
19142 /* Choose a Ri in the high-register-list that will be restored. */
19145 /* MOV Ri, Rn. */
19146 current_stub_contents =
19149 }
19151 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19152 current_stub_contents =
19154 create_instruction_ldmia
19157 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19158 current_stub_contents =
19160 create_instruction_ldmia
19164 {
19165 /* B initial_insn_addr+4. */
19166 current_stub_contents =
19168 create_instruction_branch_absolute
19170 }
19171 }
19173 /* Fill the remaining of the stub with deterministic contents. */
19174 current_stub_contents =
19177 base_stub_contents +
19178 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19179 }
19181 static void
19187 {
19200 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19201 smaller than 8 registers load sequences that do not cause the
19202 hardware issue. */
19204 {
19205 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19206 current_stub_contents =
19208 initial_insn);
19210 /* B initial_insn_addr+4. */
19211 current_stub_contents =
19213 create_instruction_branch_absolute
19216 /* Fill the remaining of the stub with deterministic contents. */
19217 current_stub_contents =
19220 base_stub_contents +
19221 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19224 }
19226 /* - reg_list[13] == 0. */
19229 /* - reg_list[14] & reg_list[15] != 1. */
19232 /* - if (wback==1) reg_list[rn] == 0. */
19235 /* - nb_registers > 8. */
19238 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19240 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19241 - One with the 7 lowest registers (register mask 0x007F)
19242 This LDM will finally contain between 2 and 7 registers
19243 - One with the 7 highest registers (register mask 0xDF80)
19244 This ldm will finally contain between 2 and 7 registers. */
19248 /* A spare register may be needed during this veneer to temporarily
19249 handle the base register. This register will be restored with
19250 the last LDM operation.
19251 The usable register may be any general purpose register (that excludes
19252 PC, SP, LR : register mask is 0x1FFF). */
19255 /* Generate the stub function. */
19257 {
19258 /* Choose a Ri in the low-register-list that will be restored. */
19261 /* MOV Ri, Rn. */
19262 current_stub_contents =
19266 /* LDMDB Ri!, {R-high-register-list}. */
19267 current_stub_contents =
19269 create_instruction_ldmdb
19272 /* LDMDB Ri, {R-low-register-list}. */
19273 current_stub_contents =
19275 create_instruction_ldmdb
19278 /* B initial_insn_addr+4. */
19279 current_stub_contents =
19281 create_instruction_branch_absolute
19283 }
19285 {
19286 /* LDMDB Rn!, {R-high-register-list}. */
19287 current_stub_contents =
19289 create_instruction_ldmdb
19292 /* LDMDB Rn!, {R-low-register-list}. */
19293 current_stub_contents =
19295 create_instruction_ldmdb
19298 /* B initial_insn_addr+4. */
19299 current_stub_contents =
19301 create_instruction_branch_absolute
19303 }
19305 {
19306 /* Choose a Ri in the high-register-list that will be restored. */
19309 /* SUB Ri, Rn, #(4*nb_registers). */
19310 current_stub_contents =
19314 /* LDMIA Ri!, {R-low-register-list}. */
19315 current_stub_contents =
19317 create_instruction_ldmia
19320 /* LDMIA Ri, {R-high-register-list}. */
19321 current_stub_contents =
19323 create_instruction_ldmia
19325 }
19327 {
19328 /* Choose a Ri in the high-register-list that will be restored. */
19331 /* SUB Rn, Rn, #(4*nb_registers) */
19332 current_stub_contents =
19336 /* MOV Ri, Rn. */
19337 current_stub_contents =
19341 /* LDMIA Ri!, {R-low-register-list}. */
19342 current_stub_contents =
19344 create_instruction_ldmia
19347 /* LDMIA Ri, {R-high-register-list}. */
19348 current_stub_contents =
19350 create_instruction_ldmia
19352 }
19354 {
19357 {
19358 /* Choose a Ri in the low-register-list that will be restored. */
19361 /* MOV Ri, Rn. */
19362 current_stub_contents =
19365 }
19367 /* LDMDB Ri!, {R-high-register-list}. */
19368 current_stub_contents =
19370 create_instruction_ldmdb
19373 /* LDMDB Ri, {R-low-register-list}. */
19374 current_stub_contents =
19376 create_instruction_ldmdb
19379 /* B initial_insn_addr+4. */
19380 current_stub_contents =
19382 create_instruction_branch_absolute
19384 }
19386 {
19389 {
19390 /* Choose a Ri in the high-register-list that will be restored. */
19392 }
19394 /* SUB Ri, Rn, #(4*nb_registers). */
19395 current_stub_contents =
19399 /* LDMIA Ri!, {R-low-register-list}. */
19400 current_stub_contents =
19402 create_instruction_ldmia
19405 /* LDMIA Ri, {R-high-register-list}. */
19406 current_stub_contents =
19408 create_instruction_ldmia
19410 }
19412 {
19413 /* The assembler should not have accepted to encode this. */
19416 }
19418 /* Fill the remaining of the stub with deterministic contents. */
19419 current_stub_contents =
19422 base_stub_contents +
19423 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19425 }
19427 static void
19433 {
19439 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19440 smaller than 8 words load sequences that do not cause the
19441 hardware issue. */
19443 {
19444 /* Untouched instruction. */
19445 current_stub_contents =
19447 initial_insn);
19449 /* B initial_insn_addr+4. */
19450 current_stub_contents =
19452 create_instruction_branch_absolute
19454 }
19455 else
19456 {
19466 /* d = UInt (Vd:D);. */
19470 /* Compute the number of 8-words chunks needed to split. */
19474 /* The test coverage has been done assuming the following
19475 hypothesis that exactly one of the previous is_ predicates is
19476 true. */
19480 /* We treat the cutting of the words in one pass for all
19481 cases, then we emit the adjustments:
19483 vldm rx, {...}
19484 -> vldm rx!, {8_words_or_less} for each needed 8_word
19485 -> sub rx, rx, #size (list)
19487 vldm rx!, {...}
19488 -> vldm rx!, {8_words_or_less} for each needed 8_word
19489 This also handles vpop instruction (when rx is sp)
19491 vldmd rx!, {...}
19492 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19494 {
19498 {
19499 new_insn = create_instruction_vldmia
19501 is_dp,
19506 }
19508 {
19509 new_insn = create_instruction_vldmdb
19511 is_dp,
19515 }
19518 current_stub_contents =
19520 new_insn);
19521 }
19523 /* Only this case requires the base register compensation
19524 subtract. */
19526 {
19527 current_stub_contents =
19529 create_instruction_sub
19531 }
19533 /* B initial_insn_addr+4. */
19534 current_stub_contents =
19536 create_instruction_branch_absolute
19538 }
19540 /* Fill the remaining of the stub with deterministic contents. */
19541 current_stub_contents =
19544 base_stub_contents +
19545 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19546 }
19548 static void
19554 {
19558 stub_contents);
19562 stub_contents);
19566 stub_contents);
19567 }
19569 /* End of stm32l4xx work-around. */
19572 /* Do code byteswapping. Return FALSE afterwards so that the section is
19573 written out as normal. */
19575 static bfd_boolean
19580 {
19587 bfd_vma ptr;
19588 bfd_vma end;
19590 bfd_byte tmp;
19596 /* If this section has not been allocated an _arm_elf_section_data
19597 structure then we cannot record anything. */
19607 {
19612 {
19616 {
19618 {
19619 bfd_vma branch_to_veneer;
19620 /* Original condition code of instruction, plus bit mask for
19621 ARM B instruction. */
19625 /* The instruction is before the label. */
19628 /* Above offset included in -4 below. */
19642 }
19646 {
19647 bfd_vma branch_from_veneer;
19650 /* Take size of veneer into account. */
19659 /* Original instruction. */
19666 /* Branch back to insn after original insn. */
19672 }
19677 }
19678 }
19679 }
19682 {
19686 {
19690 {
19692 {
19694 bfd_vma branch_to_veneer =
19699 {
19700 bfd_vma out_of_range =
19706 _bfd_error_handler
19708 "cannot create STM32L4XX veneer; "
19711 output_bfd,
19715 }
19717 insn = create_instruction_branch_absolute
19720 /* The instruction is before the label. */
19725 }
19729 {
19735 veneer_r = veneer
19740 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19741 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19742 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19745 {
19749 }
19751 /* Original instruction. */
19754 stm32l4xx_create_replacing_stub
19756 }
19761 }
19762 }
19763 }
19766 {
19767 arm_unwind_table_edit *edit_node
19769 /* Now, sec->size is the size of the section we will write. The original
19770 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19771 markers) was sec->rawsize. (This isn't the case if we perform no
19772 edits, then rawsize will be zero and we should use size). */
19779 {
19781 {
19785 {
19788 out_index++;
19789 in_index++;
19790 }
19794 {
19796 {
19798 in_index++;
19803 {
19811 /* Note: this is meant to be equivalent to an
19812 R_ARM_PREL31 relocation. These synthetic
19813 EXIDX_CANTUNWIND markers are not relocated by the
19814 usual BFD method. */
19818 {
19819 /* Here relocation for new EXIDX_CANTUNWIND is
19820 created, so there is no need to
19821 adjust offset by hand. */
19824 }
19826 /* First address we can't unwind. */
19830 /* Code for EXIDX_CANTUNWIND. */
19834 out_index++;
19836 }
19838 }
19841 }
19842 }
19843 else
19844 {
19845 /* No more edits, copy remaining entries verbatim. */
19848 out_index++;
19849 in_index++;
19850 }
19851 }
19855 edited_contents,
19859 }
19861 /* Fix code to point to Cortex-A8 erratum stubs. */
19863 {
19871 }
19877 {
19882 {
19885 else
19889 {
19891 /* Byte swap code words. */
19893 {
19901 }
19905 /* Byte swap code halfwords. */
19907 {
19912 }
19916 /* Leave data alone. */
19918 }
19920 }
19921 }
19929 }
19931 /* Mangle thumb function symbols as we read them in. */
19933 static bfd_boolean
19938 {
19946 /* New EABI objects mark thumb function symbols by setting the low bit of
19947 the address. */
19950 {
19952 {
19955 ST_BRANCH_TO_THUMB);
19956 }
19957 else
19959 }
19961 {
19964 }
19967 else
19970 /* Mark CMSE special symbols. */
19978 }
19981 /* Mangle thumb function symbols as we write them out. */
19983 static void
19988 {
19989 Elf_Internal_Sym newsym;
19991 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19992 of the address set, as per the new EABI. We do this unconditionally
19993 because objcopy does not set the elf header flags until after
19994 it writes out the symbol table. */
19996 {
20001 {
20002 /* Do this only for defined symbols. At link type, the static
20003 linker will simulate the work of dynamic linker of resolving
20004 symbols and will carry over the thumbness of found symbols to
20005 the output symbol table. It's not clear how it happens, but
20006 the thumbness of undefined symbols can well be different at
20007 runtime, and writing '1' for them will be confusing for users
20008 and possibly for dynamic linker itself.
20009 */
20011 }
20014 }
20016 }
20018 /* Add the PT_ARM_EXIDX program header. */
20020 static bfd_boolean
20023 {
20029 {
20030 /* If there is already a PT_ARM_EXIDX header, then we do not
20031 want to add another one. This situation arises when running
20032 "strip"; the input binary already has the header. */
20037 {
20048 }
20049 }
20052 }
20054 /* We may add a PT_ARM_EXIDX program header. */
20056 static int
20059 {
20065 else
20067 }
20069 /* Hook called by the linker routine which adds symbols from an object
20070 file. */
20072 static bfd_boolean
20076 {
20086 }
20088 /* We use this to override swap_symbol_in and swap_symbol_out. */
20090 {
20103 bfd_elf32_write_out_phdrs,
20104 bfd_elf32_write_shdrs_and_ehdr,
20105 bfd_elf32_checksum_contents,
20106 bfd_elf32_write_relocs,
20107 elf32_arm_swap_symbol_in,
20108 elf32_arm_swap_symbol_out,
20109 bfd_elf32_slurp_reloc_table,
20110 bfd_elf32_slurp_symbol_table,
20111 bfd_elf32_swap_dyn_in,
20112 bfd_elf32_swap_dyn_out,
20113 bfd_elf32_swap_reloc_in,
20114 bfd_elf32_swap_reloc_out,
20115 bfd_elf32_swap_reloca_in,
20116 bfd_elf32_swap_reloca_out
20117 };
20119 static bfd_vma
20121 {
20122 /* V7 BE8 code is always little endian. */
20127 }
20129 static bfd_vma
20131 {
20132 /* V7 BE8 code is always little endian. */
20137 }
20139 /* Return size of plt0 entry starting at ADDR
20140 or (bfd_vma) -1 if size can not be determined. */
20142 static bfd_vma
20144 {
20145 bfd_vma first_word;
20146 bfd_vma plt0_size;
20154 else
20155 /* We don't yet handle this PLT format. */
20159 }
20161 /* Return size of plt entry starting at offset OFFSET
20162 of plt section located at address START
20163 or (bfd_vma) -1 if size can not be determined. */
20165 static bfd_vma
20167 {
20168 bfd_vma first_insn;
20172 /* PLT entry size if fixed on Thumb-only platforms. */
20176 /* Respect Thumb stub if necessary. */
20178 {
20180 }
20182 /* Strip immediate from first add. */
20185 #ifdef FOUR_WORD_PLT
20188 #else
20193 #endif
20194 else
20195 /* We don't yet handle this PLT format. */
20199 }
20201 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20203 static long
20210 {
20219 bfd_vma offset;
20248 {
20252 }
20258 {
20262 }
20276 {
20284 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20285 we are defining a symbol, ensure one of them is set. */
20297 {
20304 ;
20308 }
20313 }
20316 }
20318 static bfd_boolean
20320 {
20324 }
20326 static flagword
20328 {
20333 }
20335 static unsigned int
20337 {
20342 }
20344 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20345 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20346 FALSE otherwise. ISECTION is the best guess matching section from the
20347 input bfd IBFD, but it might be NULL. */
20349 static bfd_boolean
20354 {
20356 {
20358 {
20366 /* The sh_link field must be set to the text section associated with
20367 this index section. Unfortunately the ARM EHABI does not specify
20368 exactly how to determine this association. Our caller does try
20369 to match up OSECTION with its corresponding input section however
20370 so that is a good first guess. */
20381 )
20382 {
20387 }
20390 {
20391 /* Failing that we have to find a matching section ourselves. If
20392 we had the output section name available we could compare that
20393 with input section names. Unfortunately we don't. So instead
20394 we use a simple heuristic and look for the nearest executable
20395 section before this one. */
20407 }
20410 {
20412 /* If the text section was part of a group
20413 then the index section should be too. */
20417 }
20418 }
20430 }
20433 }
20435 /* Returns TRUE if NAME is an ARM mapping symbol.
20436 Traditionally the symbols $a, $d and $t have been used.
20437 The ARM ELF standard also defines $x (for A64 code). It also allows a
20438 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20439 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20440 not support them here. $t.x indicates the start of ThumbEE instructions. */
20442 static bfd_boolean
20444 {
20447 the mapping symbols could have acquired a prefix.
20448 We do not support this here, since such symbols no
20449 longer conform to the ARM ELF ABI. */
20452 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20453 any characters that follow the period are legal characters for the body
20454 of a symbol's name. For now we just assume that this is the case. */
20455 }
20457 /* Make sure that mapping symbols in object files are not removed via the
20458 "strip --strip-unneeded" tool. These symbols are needed in order to
20459 correctly generate interworking veneers, and for byte swapping code
20460 regions. Once an object file has been linked, it is safe to remove the
20461 symbols as they will no longer be needed. */
20463 static void
20465 {
20470 }
20472 #undef elf_backend_copy_special_section_fields
20473 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20475 #define ELF_ARCH bfd_arch_arm
20476 #define ELF_TARGET_ID ARM_ELF_DATA
20477 #define ELF_MACHINE_CODE EM_ARM
20478 #ifdef __QNXTARGET__
20479 #define ELF_MAXPAGESIZE 0x1000
20480 #else
20481 #define ELF_MAXPAGESIZE 0x10000
20482 #endif
20483 #define ELF_MINPAGESIZE 0x1000
20484 #define ELF_COMMONPAGESIZE 0x1000
20486 #define bfd_elf32_mkobject elf32_arm_mkobject
20488 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20489 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20490 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20491 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20492 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20493 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20494 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20495 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20496 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20497 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20498 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20499 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20500 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20502 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20503 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20504 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20505 #define elf_backend_check_relocs elf32_arm_check_relocs
20506 #define elf_backend_update_relocs elf32_arm_update_relocs
20507 #define elf_backend_relocate_section elf32_arm_relocate_section
20508 #define elf_backend_write_section elf32_arm_write_section
20509 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20510 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20511 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20512 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20513 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
20514 #define elf_backend_always_size_sections elf32_arm_always_size_sections
20515 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20516 #define elf_backend_post_process_headers elf32_arm_post_process_headers
20517 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20518 #define elf_backend_object_p elf32_arm_object_p
20519 #define elf_backend_fake_sections elf32_arm_fake_sections
20520 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20521 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20522 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20523 #define elf_backend_size_info elf32_arm_size_info
20524 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20525 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20526 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20527 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20528 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20529 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20530 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20531 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20533 #define elf_backend_can_refcount 1
20534 #define elf_backend_can_gc_sections 1
20535 #define elf_backend_plt_readonly 1
20536 #define elf_backend_want_got_plt 1
20537 #define elf_backend_want_plt_sym 0
20538 #define elf_backend_want_dynrelro 1
20539 #define elf_backend_may_use_rel_p 1
20540 #define elf_backend_may_use_rela_p 0
20541 #define elf_backend_default_use_rela_p 0
20542 #define elf_backend_dtrel_excludes_plt 1
20544 #define elf_backend_got_header_size 12
20545 #define elf_backend_extern_protected_data 1
20547 #undef elf_backend_obj_attrs_vendor
20549 #undef elf_backend_obj_attrs_section
20551 #undef elf_backend_obj_attrs_arg_type
20552 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20553 #undef elf_backend_obj_attrs_section_type
20554 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20555 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20556 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20558 #undef elf_backend_section_flags
20559 #define elf_backend_section_flags elf32_arm_section_flags
20560 #undef elf_backend_lookup_section_flags_hook
20561 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20563 #define elf_backend_linux_prpsinfo32_ugid16 TRUE
20567 /* Native Client targets. */
20569 #undef TARGET_LITTLE_SYM
20570 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20571 #undef TARGET_LITTLE_NAME
20573 #undef TARGET_BIG_SYM
20574 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20575 #undef TARGET_BIG_NAME
20578 /* Like elf32_arm_link_hash_table_create -- but overrides
20579 appropriately for NaCl. */
20583 {
20588 {
20596 }
20598 }
20600 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20601 really need to use elf32_arm_modify_segment_map. But we do it
20602 anyway just to reduce gratuitous differences with the stock ARM backend. */
20604 static bfd_boolean
20606 {
20609 }
20611 static void
20613 {
20616 }
20618 static bfd_vma
20621 {
20625 }
20627 #undef elf32_bed
20628 #define elf32_bed elf32_arm_nacl_bed
20629 #undef bfd_elf32_bfd_link_hash_table_create
20630 #define bfd_elf32_bfd_link_hash_table_create \
20631 elf32_arm_nacl_link_hash_table_create
20632 #undef elf_backend_plt_alignment
20633 #define elf_backend_plt_alignment 4
20634 #undef elf_backend_modify_segment_map
20635 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20636 #undef elf_backend_modify_program_headers
20637 #define elf_backend_modify_program_headers nacl_modify_program_headers
20638 #undef elf_backend_final_write_processing
20639 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20640 #undef bfd_elf32_get_synthetic_symtab
20641 #undef elf_backend_plt_sym_val
20642 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20643 #undef elf_backend_copy_special_section_fields
20645 #undef ELF_MINPAGESIZE
20646 #undef ELF_COMMONPAGESIZE
20651 /* Reset to defaults. */
20652 #undef elf_backend_plt_alignment
20653 #undef elf_backend_modify_segment_map
20654 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20655 #undef elf_backend_modify_program_headers
20656 #undef elf_backend_final_write_processing
20657 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20658 #undef ELF_MINPAGESIZE
20659 #define ELF_MINPAGESIZE 0x1000
20660 #undef ELF_COMMONPAGESIZE
20661 #define ELF_COMMONPAGESIZE 0x1000
20664 /* FDPIC Targets. */
20666 #undef TARGET_LITTLE_SYM
20667 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20668 #undef TARGET_LITTLE_NAME
20670 #undef TARGET_BIG_SYM
20671 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20672 #undef TARGET_BIG_NAME
20674 #undef elf_match_priority
20675 #define elf_match_priority 128
20676 #undef ELF_OSABI
20677 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20679 /* Like elf32_arm_link_hash_table_create -- but overrides
20680 appropriately for FDPIC. */
20684 {
20689 {
20693 }
20695 }
20697 /* We need dynamic symbols for every section, since segments can
20698 relocate independently. */
20699 static bfd_boolean
20702 ATTRIBUTE_UNUSED,
20704 {
20706 {
20709 /* If sh_type is yet undecided, assume it could be
20710 SHT_PROGBITS/SHT_NOBITS. */
20714 /* There shouldn't be section relative relocations
20715 against any other section. */
20718 }
20719 }
20721 #undef elf32_bed
20722 #define elf32_bed elf32_arm_fdpic_bed
20724 #undef bfd_elf32_bfd_link_hash_table_create
20725 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20727 #undef elf_backend_omit_section_dynsym
20728 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20732 #undef elf_match_priority
20733 #undef ELF_OSABI
20734 #undef elf_backend_omit_section_dynsym
20736 /* VxWorks Targets. */
20738 #undef TARGET_LITTLE_SYM
20739 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20740 #undef TARGET_LITTLE_NAME
20742 #undef TARGET_BIG_SYM
20743 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20744 #undef TARGET_BIG_NAME
20747 /* Like elf32_arm_link_hash_table_create -- but overrides
20748 appropriately for VxWorks. */
20752 {
20757 {
20762 }
20764 }
20766 static void
20768 {
20771 }
20773 #undef elf32_bed
20774 #define elf32_bed elf32_arm_vxworks_bed
20776 #undef bfd_elf32_bfd_link_hash_table_create
20777 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20778 #undef elf_backend_final_write_processing
20779 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20780 #undef elf_backend_emit_relocs
20781 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20783 #undef elf_backend_may_use_rel_p
20784 #define elf_backend_may_use_rel_p 0
20785 #undef elf_backend_may_use_rela_p
20786 #define elf_backend_may_use_rela_p 1
20787 #undef elf_backend_default_use_rela_p
20788 #define elf_backend_default_use_rela_p 1
20789 #undef elf_backend_want_plt_sym
20790 #define elf_backend_want_plt_sym 1
20791 #undef ELF_MAXPAGESIZE
20792 #define ELF_MAXPAGESIZE 0x1000
20797 /* Merge backend specific data from an object file to the output
20798 object file when linking. */
20800 static bfd_boolean
20802 {
20804 flagword out_flags;
20805 flagword in_flags;
20809 /* Check if we have the same endianness. */
20819 /* The input BFD must have had its flags initialised. */
20820 /* The following seems bogus to me -- The flags are initialized in
20821 the assembler but I don't think an elf_flags_init field is
20822 written into the object. */
20823 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20828 /* In theory there is no reason why we couldn't handle this. However
20829 in practice it isn't even close to working and there is no real
20830 reason to want it. */
20834 {
20836 ibfd);
20838 }
20841 {
20842 /* If the input is the default architecture and had the default
20843 flags then do not bother setting the flags for the output
20844 architecture, instead allow future merges to do this. If no
20845 future merges ever set these flags then they will retain their
20846 uninitialised values, which surprise surprise, correspond
20847 to the default values. */
20860 }
20862 /* Determine what should happen if the input ARM architecture
20863 does not match the output ARM architecture. */
20867 /* Identical flags must be compatible. */
20871 /* Check to see if the input BFD actually contains any sections. If
20872 not, its flags may not have been initialised either, but it
20873 cannot actually cause any incompatiblity. Do not short-circuit
20874 dynamic objects; their section list may be emptied by
20875 elf_link_add_object_symbols.
20877 Also check to see if there are no code sections in the input.
20878 In this case there is no need to check for code specific flags.
20879 XXX - do we need to worry about floating-point format compatability
20880 in data sections ? */
20882 {
20887 {
20888 /* Ignore synthetic glue sections. */
20891 {
20899 }
20900 }
20904 }
20906 /* Complain about various flag mismatches. */
20909 {
20910 _bfd_error_handler
20915 }
20917 /* Not sure what needs to be checked for EABI versions >= 1. */
20918 /* VxWorks libraries do not use these flags. */
20922 {
20924 {
20925 _bfd_error_handler
20930 }
20933 {
20935 _bfd_error_handler
20936 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20938 else
20939 _bfd_error_handler
20940 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20944 }
20947 {
20949 _bfd_error_handler
20952 else
20953 _bfd_error_handler
20958 }
20961 {
20963 _bfd_error_handler
20966 else
20967 _bfd_error_handler
20972 }
20974 #ifdef EF_ARM_SOFT_FLOAT
20976 {
20977 /* We can allow interworking between code that is VFP format
20978 layout, and uses either soft float or integer regs for
20979 passing floating point arguments and results. We already
20980 know that the APCS_FLOAT flags match; similarly for VFP
20981 flags. */
20984 {
20986 _bfd_error_handler
20989 else
20990 _bfd_error_handler
20995 }
20996 }
20997 #endif
20999 /* Interworking mismatch is only a warning. */
21001 {
21003 {
21004 _bfd_error_handler
21007 }
21008 else
21009 {
21010 _bfd_error_handler
21013 }
21014 }
21015 }
21018 }
21021 /* Symbian OS Targets. */
21023 #undef TARGET_LITTLE_SYM
21024 #define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
21025 #undef TARGET_LITTLE_NAME
21027 #undef TARGET_BIG_SYM
21028 #define TARGET_BIG_SYM arm_elf32_symbian_be_vec
21029 #undef TARGET_BIG_NAME
21032 /* Like elf32_arm_link_hash_table_create -- but overrides
21033 appropriately for Symbian OS. */
21037 {
21042 {
21045 /* There is no PLT header for Symbian OS. */
21047 /* The PLT entries are each one instruction and one word. */
21050 /* Symbian uses armv5t or above, so use_blx is always true. */
21053 }
21055 }
21057 static const struct bfd_elf_special_section
21058 elf32_arm_symbian_special_sections[] =
21059 {
21060 /* In a BPABI executable, the dynamic linking sections do not go in
21061 the loadable read-only segment. The post-linker may wish to
21062 refer to these sections, but they are not part of the final
21063 program image. */
21069 /* These sections do not need to be writable as the SymbianOS
21070 postlinker will arrange things so that no dynamic relocation is
21071 required. */
21076 };
21078 static void
21081 {
21082 /* BPABI objects are never loaded directly by an OS kernel; they are
21083 processed by a postlinker first, into an OS-specific format. If
21084 the D_PAGED bit is set on the file, BFD will align segments on
21085 page boundaries, so that an OS can directly map the file. With
21086 BPABI objects, that just results in wasted space. In addition,
21087 because we clear the D_PAGED bit, map_sections_to_segments will
21088 recognize that the program headers should not be mapped into any
21089 loadable segment. */
21092 }
21094 static bfd_boolean
21097 {
21101 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21102 segment. However, because the .dynamic section is not marked
21103 with SEC_LOAD, the generic ELF code will not create such a
21104 segment. */
21107 {
21113 {
21117 }
21118 }
21120 /* Also call the generic arm routine. */
21122 }
21124 /* Return address for Ith PLT stub in section PLT, for relocation REL
21125 or (bfd_vma) -1 if it should not be included. */
21127 static bfd_vma
21130 {
21132 }
21134 #undef elf32_bed
21135 #define elf32_bed elf32_arm_symbian_bed
21137 /* The dynamic sections are not allocated on SymbianOS; the postlinker
21138 will process them and then discard them. */
21139 #undef ELF_DYNAMIC_SEC_FLAGS
21140 #define ELF_DYNAMIC_SEC_FLAGS \
21141 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21143 #undef elf_backend_emit_relocs
21145 #undef bfd_elf32_bfd_link_hash_table_create
21146 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21147 #undef elf_backend_special_sections
21148 #define elf_backend_special_sections elf32_arm_symbian_special_sections
21149 #undef elf_backend_begin_write_processing
21150 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21151 #undef elf_backend_final_write_processing
21152 #define elf_backend_final_write_processing elf32_arm_final_write_processing
21154 #undef elf_backend_modify_segment_map
21155 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21157 /* There is no .got section for BPABI objects, and hence no header. */
21158 #undef elf_backend_got_header_size
21159 #define elf_backend_got_header_size 0
21161 /* Similarly, there is no .got.plt section. */
21162 #undef elf_backend_want_got_plt
21163 #define elf_backend_want_got_plt 0
21165 #undef elf_backend_plt_sym_val
21166 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21168 #undef elf_backend_may_use_rel_p
21169 #define elf_backend_may_use_rel_p 1
21170 #undef elf_backend_may_use_rela_p
21171 #define elf_backend_may_use_rela_p 0
21172 #undef elf_backend_default_use_rela_p
21173 #define elf_backend_default_use_rela_p 0
21174 #undef elf_backend_want_plt_sym
21175 #define elf_backend_want_plt_sym 0
21176 #undef elf_backend_dtrel_excludes_plt
21177 #define elf_backend_dtrel_excludes_plt 0
21178 #undef ELF_MAXPAGESIZE
21179 #define ELF_MAXPAGESIZE 0x8000