| blob | 2f6bd885550c102cc85bd07d24216c69fc22cf0e |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2020 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
34 /* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36 #define RELOC_SECTION(HTAB, NAME) \
39 /* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41 #define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
46 /* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48 #define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
53 /* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55 #define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
60 #define elf_info_to_howto NULL
61 #define elf_info_to_howto_rel elf32_arm_info_to_howto
63 #define ARM_ELF_ABI_VERSION 0
64 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
66 /* The Adjusted Place, as defined by AAELF. */
67 #define Pa(X) ((X) & 0xfffffffc)
74 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
79 {
80 /* No relocation. */
109 /* 32 bit absolute */
124 /* standard 32bit pc-relative reloc */
139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
154 /* 16 bit absolute */
169 /* 12 bit absolute */
198 /* 8 bit absolute */
297 /* BLX instruction for the ARM. */
312 /* BLX instruction for the Thumb. */
327 /* Dynamic TLS relocations. */
371 /* Relocs used in ARM Linux */
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
894 /* Group relocations. */
1274 /* End of group relocations. */
1488 /* GNU extension to record C++ vtable member usage */
1503 /* GNU extension to record C++ vtable hierarchy */
1546 /* TLS relocations */
1659 /* 112-127 private relocations. */
1677 /* R_ARM_ME_TOO, obsolete. */
1747 /* Relocations for Armv8.1-M Mainline. */
1787 };
1789 /* 160 onwards: */
1791 {
1896 };
1898 /* 249-255 extended, currently unused, relocations: */
1900 {
1956 };
1960 {
1973 }
1975 static bfd_boolean
1978 {
1983 {
1984 /* xgettext:c-format */
1989 }
1991 }
1993 struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
1997 };
1999 /* All entries in this list must also be present in elf32_arm_howto_table. */
2001 {
2102 };
2106 bfd_reloc_code_real_type code)
2107 {
2115 }
2120 {
2139 }
2141 /* Support for core dump NOTE sections. */
2143 static bfd_boolean
2145 {
2150 {
2155 /* pr_cursig */
2158 /* pr_pid */
2161 /* pr_reg */
2166 }
2168 /* Make a ".reg/999" section. */
2171 }
2173 static bfd_boolean
2175 {
2177 {
2188 }
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
2193 {
2199 }
2202 }
2207 {
2209 {
2214 {
2221 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2222 DIAGNOSTIC_PUSH;
2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228 #endif
2230 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2231 DIAGNOSTIC_POP;
2232 #endif
2237 }
2240 {
2259 }
2260 }
2261 }
2263 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2265 #define TARGET_BIG_SYM arm_elf32_be_vec
2268 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2270 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2275 /* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
2277 #define INTERWORK_FLAG(abfd) \
2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
2282 /* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
2285 name can be changed. The only requirement is the %s be present. */
2307 /* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2311 /* FDPIC default stack size. */
2312 #define DEFAULT_STACK_SIZE 0x8000
2315 {
2319 };
2322 {
2330 + dl_tlsdesc_lazy_resolver(GOT) */
2332 };
2334 /* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2339 /* ARM FDPIC PLT entry. */
2340 /* The last 5 words contain PLT lazy fragment code and data. */
2342 {
2353 };
2355 /* Thumb FDPIC PLT entry. */
2356 /* The last 5 words contain PLT lazy fragment code and data. */
2358 {
2369 };
2371 #ifdef FOUR_WORD_PLT
2373 /* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
2375 called before the relocation has been set up calls the dynamic
2376 linker first. */
2378 {
2383 };
2385 /* Subsequent entries in a procedure linkage table look like
2386 this. */
2388 {
2393 };
2397 /* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
2402 {
2408 };
2410 /* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2413 {
2417 };
2419 /* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2422 {
2427 };
2433 /* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2437 {
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
2442 /* add lr, pc */
2445 };
2447 /* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2450 {
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
2457 /* b .-4 */
2458 };
2460 /* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2463 {
2468 };
2470 /* The format of subsequent entries in a VxWorks executable. */
2472 {
2479 };
2481 /* The format of entries in a VxWorks shared library. */
2483 {
2490 };
2492 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2493 #define PLT_THUMB_STUB_SIZE 4
2495 {
2498 };
2500 /* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
2503 {
2506 };
2508 /* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2513 {
2514 /* First bundle: */
2519 /* Second bundle: */
2524 /* Third bundle: */
2528 /* .Lplt_tail: */
2530 /* Fourth bundle: */
2535 };
2536 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2538 /* Subsequent entries in a procedure linkage table look like this. */
2540 {
2545 };
2547 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2553 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2556 enum stub_insn_type
2557 {
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562 };
2564 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2569 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2571 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2577 {
2578 bfd_vma data;
2584 /* See note [Thumb nop sequence] when adding a veneer. */
2586 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
2589 {
2592 };
2594 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
2597 {
2601 };
2603 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2605 {
2613 };
2615 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2617 {
2620 };
2622 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2625 {
2629 };
2631 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2634 {
2640 };
2642 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
2645 {
2650 };
2652 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
2655 {
2659 };
2661 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2662 blx to reach the stub if necessary. */
2664 {
2668 };
2670 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2675 {
2680 };
2682 /* V4T ARM -> ARM long branch stub, PIC. */
2684 {
2689 };
2691 /* V4T Thumb -> ARM long branch stub, PIC. */
2693 {
2699 };
2701 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
2704 {
2712 };
2714 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2717 {
2724 };
2726 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2729 {
2733 };
2735 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2738 {
2744 };
2746 /* NaCl ARM -> ARM long branch stub. */
2748 {
2757 };
2759 /* NaCl ARM -> ARM long branch stub, PIC. */
2761 {
2770 };
2772 /* Stub used for transition to secure state (aka SG veneer). */
2774 {
2777 };
2780 /* Cortex-A8 erratum-workaround stubs. */
2782 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2786 {
2790 };
2792 /* Stub used for b.w and bl.w instructions. */
2795 {
2797 };
2800 {
2802 };
2804 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2809 {
2811 };
2813 /* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
2822 const char * stubborn_problems[] = { "np" };
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2827 .data.rel.local.stubborn_problems
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2840 /* One entry per long/short branch stub defined above. */
2841 #define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2853 DEF_STUB(long_branch_thumb_only_pic) \
2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
2858 DEF_STUB(cmse_branch_thumb_only) \
2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
2864 DEF_STUB(long_branch_thumb2_only_pure)
2866 #define DEF_STUB(x) arm_stub_##x,
2867 enum elf32_arm_stub_type
2868 {
2869 arm_stub_none,
2870 DEF_STUBS
2871 max_stub_type
2872 };
2873 #undef DEF_STUB
2875 /* Note the first a8_veneer type. */
2879 {
2884 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2886 {
2888 DEF_STUBS
2889 };
2891 struct elf32_arm_stub_hash_entry
2892 {
2893 /* Base hash table entry structure. */
2896 /* The stub section. */
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2918 /* The stub type. */
2920 /* Its encoding size in bytes. */
2922 /* Its template. */
2924 /* The size of the template (number of entries). */
2927 /* The symbol table entry, if any, that this was derived from. */
2930 /* Type of branch. */
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2941 };
2943 /* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2947 {
2948 bfd_vma vma;
2950 }
2951 elf32_arm_section_map;
2953 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2956 {
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961 }
2962 elf32_vfp11_erratum_type;
2965 {
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2975 struct
2976 {
2981 elf32_vfp11_erratum_type type;
2982 }
2983 elf32_vfp11_erratum_list;
2985 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2988 {
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991 }
2992 elf32_stm32l4xx_erratum_type;
2995 {
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3005 struct
3006 {
3011 elf32_stm32l4xx_erratum_type type;
3012 }
3013 elf32_stm32l4xx_erratum_list;
3016 {
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019 }
3020 arm_unwind_edit_type;
3022 /* A (sorted) list of edits to apply to an unwind table. */
3024 {
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3032 }
3033 arm_unwind_table_edit;
3036 {
3037 /* Information about mapping symbols. */
3042 /* Information about CPU errata. */
3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3064 }
3065 _arm_elf_section_data;
3067 #define elf32_arm_section_data(sec) \
3068 ((_arm_elf_section_data *) elf_section_data (sec))
3070 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3076 struct a8_erratum_fix
3077 {
3080 bfd_vma offset;
3081 bfd_vma target_offset;
3086 };
3088 /* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3091 struct a8_erratum_reloc
3092 {
3093 bfd_vma from;
3094 bfd_vma destination;
3099 bfd_boolean non_a8_stub;
3100 };
3102 /* The size of the thread control block. */
3103 #define TCB_SIZE 8
3105 /* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
3107 struct arm_plt_info
3108 {
3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128 };
3130 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3131 struct arm_local_iplt_info
3132 {
3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3141 /* A list of all potential dynamic relocations against this symbol. */
3143 };
3145 /* Structure to handle FDPIC support for local functions. */
3150 };
3152 struct elf_arm_obj_tdata
3153 {
3156 /* tls_type for each local got entry. */
3159 /* GOTPLT entries for TLS descriptors. */
3162 /* Information for local symbols that need entries in .iplt. */
3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3171 /* Maintains FDPIC counters and funcdesc info. */
3173 };
3175 #define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3178 #define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3181 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3184 #define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3187 #define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3190 #define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
3193 && elf_object_id (bfd) == ARM_ELF_DATA)
3195 static bfd_boolean
3197 {
3199 ARM_ELF_DATA);
3200 }
3202 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3204 /* Structure to handle FDPIC support for extern functions. */
3211 };
3213 /* Arm ELF linker hash entry. */
3214 struct elf32_arm_link_hash_entry
3215 {
3218 /* ARM-specific PLT information. */
3221 #define GOT_UNKNOWN 0
3222 #define GOT_NORMAL 1
3223 #define GOT_TLS_GD 2
3224 #define GOT_TLS_IE 4
3225 #define GOT_TLS_GDESC 8
3226 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3229 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3234 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3235 starting at the end of the jump table. */
3236 bfd_vma tlsdesc_got;
3238 /* The symbol marking the real symbol location for exported thumb
3239 symbols with Arm stubs. */
3242 /* A pointer to the most recently used stub hash entry against this
3243 symbol. */
3246 /* Counter for FDPIC relocations against this symbol. */
3248 };
3250 /* Traverse an arm ELF linker hash table. */
3251 #define elf32_arm_link_hash_traverse(table, func, info) \
3252 (elf_link_hash_traverse \
3253 (&(table)->root, \
3254 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
3255 (info)))
3257 /* Get the ARM elf linker hash table from a link_info structure. */
3258 #define elf32_arm_hash_table(p) \
3259 ((is_elf_hash_table ((p)->hash) \
3260 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3261 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
3263 #define arm_stub_hash_lookup(table, string, create, copy) \
3264 ((struct elf32_arm_stub_hash_entry *) \
3265 bfd_hash_lookup ((table), (string), (create), (copy)))
3267 /* Array to keep track of which stub sections have been created, and
3268 information on stub grouping. */
3269 struct map_stub
3270 {
3271 /* This is the section to which stubs in the group will be
3272 attached. */
3274 /* The stub section. */
3276 };
3278 #define elf32_arm_compute_jump_table_size(htab) \
3279 ((htab)->next_tls_desc_index * 4)
3281 /* ARM ELF linker hash table. */
3282 struct elf32_arm_link_hash_table
3283 {
3284 /* The main hash table. */
3287 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3288 bfd_size_type thumb_glue_size;
3290 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3291 bfd_size_type arm_glue_size;
3293 /* The size in bytes of section containing the ARMv4 BX veneers. */
3294 bfd_size_type bx_glue_size;
3296 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3297 veneer has been populated. */
3300 /* The size in bytes of the section containing glue for VFP11 erratum
3301 veneers. */
3302 bfd_size_type vfp11_erratum_glue_size;
3304 /* The size in bytes of the section containing glue for STM32L4XX erratum
3305 veneers. */
3306 bfd_size_type stm32l4xx_erratum_glue_size;
3308 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3309 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3310 elf32_arm_write_section(). */
3314 /* An arbitrary input BFD chosen to hold the glue sections. */
3317 /* Nonzero to output a BE8 image. */
3320 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3321 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3324 /* The relocation to use for R_ARM_TARGET2 relocations. */
3327 /* 0 = Ignore R_ARM_V4BX.
3328 1 = Convert BX to MOV PC.
3329 2 = Generate v4 interworing stubs. */
3332 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3335 /* Whether we should fix the ARM1176 BLX immediate issue. */
3338 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3341 /* What sort of code sequences we should look for which may trigger the
3342 VFP11 denorm erratum. */
3343 bfd_arm_vfp11_fix vfp11_fix;
3345 /* Global counter for the number of fixes we have emitted. */
3348 /* What sort of code sequences we should look for which may trigger the
3349 STM32L4XX erratum. */
3350 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3352 /* Global counter for the number of fixes we have emitted. */
3355 /* Nonzero to force PIC branch veneers. */
3358 /* The number of bytes in the initial entry in the PLT. */
3359 bfd_size_type plt_header_size;
3361 /* The number of bytes in the subsequent PLT etries. */
3362 bfd_size_type plt_entry_size;
3364 /* True if the target uses REL relocations. */
3365 bfd_boolean use_rel;
3367 /* Nonzero if import library must be a secure gateway import library
3368 as per ARMv8-M Security Extensions. */
3371 /* The import library whose symbols' address must remain stable in
3372 the import library generated. */
3375 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3376 bfd_vma next_tls_desc_index;
3378 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3379 bfd_vma num_tls_desc;
3381 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3384 /* Offset in .plt section of tls_arm_trampoline. */
3385 bfd_vma tls_trampoline;
3387 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3388 union
3389 {
3390 bfd_signed_vma refcount;
3391 bfd_vma offset;
3394 /* For convenience in allocate_dynrelocs. */
3397 /* The amount of space used by the reserved portion of the sgotplt
3398 section, plus whatever space is used by the jump slots. */
3399 bfd_vma sgotplt_jump_table_size;
3401 /* The stub hash table. */
3404 /* Linker stub bfd. */
3407 /* Linker call-backs. */
3412 /* Array to keep track of which stub sections have been created, and
3413 information on stub grouping. */
3416 /* Input stub section holding secure gateway veneers. */
3419 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3420 start to be allocated. */
3421 bfd_vma new_cmse_stub_offset;
3423 /* Number of elements in stub_group. */
3426 /* Assorted information used by elf32_arm_size_stubs. */
3431 /* True if the target system uses FDPIC. */
3434 /* Fixup section. Used for FDPIC. */
3436 };
3438 /* Add an FDPIC read-only fixup. */
3439 static void
3441 {
3442 bfd_vma fixup_offset;
3447 }
3451 {
3452 #if GCC_VERSION >= 3004
3454 #else
3458 {
3462 }
3464 #endif
3465 }
3469 {
3470 #if GCC_VERSION >= 3004
3472 #else
3477 {
3479 sum++;
3481 }
3483 #endif
3484 }
3489 static void
3495 bfd_vma addr,
3496 bfd_vma dynreloc_value,
3497 bfd_vma seg)
3498 {
3500 {
3505 {
3507 Elf_Internal_Rela outrel;
3516 }
3517 else
3518 {
3532 }
3534 }
3535 }
3537 /* Create an entry in an ARM ELF linker hash table. */
3543 {
3547 /* Allocate the structure if it has not already been allocated by a
3548 subclass. */
3555 /* Call the allocation method of the superclass. */
3560 {
3577 }
3580 }
3582 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3583 symbols. */
3585 static bfd_boolean
3587 {
3589 {
3590 bfd_size_type num_syms;
3591 bfd_size_type size;
3604 /* It is important that these all be allocated in descending
3605 order of required alignment, so that arrays allocated later
3606 will be sufficiently aligned. */
3620 #if GCC_VERSION >= 3000
3629 #endif
3630 }
3632 }
3634 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3635 to input bfd ABFD. Create the information if it doesn't already exist.
3636 Return null if an allocation fails. */
3640 {
3651 }
3653 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3654 in ABFD's symbol table. If the symbol is global, H points to its
3655 hash table entry, otherwise H is null.
3657 Return true if the symbol does have PLT information. When returning
3658 true, point *ROOT_PLT at the target-independent reference count/offset
3659 union and *ARM_PLT at the ARM-specific information. */
3661 static bfd_boolean
3666 {
3673 {
3677 }
3689 }
3693 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3694 before it. */
3696 static bfd_boolean
3699 {
3706 }
3708 /* Return a pointer to the head of the dynamic reloc list that should
3709 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3710 ABFD's symbol table. Return null if an error occurs. */
3715 {
3717 {
3724 }
3725 else
3726 {
3727 /* Track dynamic relocs needed for local syms too.
3728 We really need local syms available to do this
3729 easily. Oh well. */
3739 }
3740 }
3742 /* Initialize an entry in the stub hash table. */
3748 {
3749 /* Allocate the structure if it has not already been allocated by a
3750 subclass. */
3752 {
3757 }
3759 /* Call the allocation method of the superclass. */
3762 {
3765 /* Initialize the local fields. */
3780 }
3783 }
3785 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3786 shortcuts to them in our hash table. */
3788 static bfd_boolean
3790 {
3797 /* BPABI objects never have a GOT, or associated sections. */
3804 /* Also create .rofixup. */
3806 {
3813 }
3816 }
3818 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3820 static bfd_boolean
3822 {
3827 flagword flags;
3835 {
3842 }
3845 {
3853 }
3856 {
3862 }
3864 }
3866 /* Determine if we're dealing with a Thumb only architecture. */
3868 static bfd_boolean
3870 {
3873 Tag_CPU_arch_profile);
3880 /* Force return logic to be reviewed for each new architecture. */
3892 }
3894 /* Determine if we're dealing with a Thumb-2 object. */
3896 static bfd_boolean
3898 {
3901 Tag_THUMB_ISA_use);
3908 /* Force return logic to be reviewed for each new architecture. */
3918 }
3920 /* Determine whether Thumb-2 BL instruction is available. */
3922 static bfd_boolean
3924 {
3928 /* Force return logic to be reviewed for each new architecture. */
3931 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3934 }
3936 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3937 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3938 hash table. */
3940 static bfd_boolean
3942 {
3956 {
3961 {
3963 htab->plt_entry_size
3965 }
3966 else
3967 {
3968 htab->plt_header_size
3970 htab->plt_entry_size
3972 }
3976 }
3977 else
3978 {
3979 /* PR ld/16017
3980 Test for thumb only architectures. Note - we cannot just call
3981 using_thumb_only() as the attributes in the output bfd have not been
3982 initialised at this point, so instead we use the input bfd. */
3987 {
3990 }
3992 }
3998 else
4000 }
4009 }
4011 /* Copy the extra info we tack onto an elf_link_hash_entry. */
4013 static void
4017 {
4024 {
4025 /* Copy over PLT info. */
4033 /* Copy FDPIC counters. */
4038 /* We should only allocate a function to .iplt once the final
4039 symbol information is known. */
4043 {
4046 }
4047 }
4050 }
4052 /* Destroy an ARM elf linker hash table. */
4054 static void
4056 {
4062 }
4064 /* Create an ARM elf linker hash table. */
4068 {
4077 elf32_arm_link_hash_newfunc,
4079 ARM_ELF_DATA))
4080 {
4083 }
4087 #ifdef FOUR_WORD_PLT
4090 #else
4093 #endif
4100 {
4103 }
4107 }
4109 /* Determine what kind of NOPs are available. */
4111 static bfd_boolean
4113 {
4115 Tag_CPU_arch);
4117 /* Force return logic to be reviewed for each new architecture. */
4125 }
4127 static bfd_boolean
4129 {
4131 {
4148 }
4149 }
4151 /* Determine the type of stub needed, if any, for a call. */
4153 static enum elf32_arm_stub_type
4160 bfd_vma destination,
4164 {
4165 bfd_vma location;
4166 bfd_signed_vma branch_offset;
4191 /* True for architectures that implement the thumb2 movw instruction. */
4194 /* Determine where the call point is. */
4201 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4202 are considering a function call relocation. */
4208 /* For TLS call relocs, it is the caller's responsibility to provide
4209 the address of the appropriate trampoline. */
4216 {
4221 else
4224 {
4227 /* Note when dealing with PLT entries: the main PLT stub is in
4228 ARM mode, so if the branch is in Thumb mode, another
4229 Thumb->ARM stub will be inserted later just before the ARM
4230 PLT stub. If a long branch stub is needed, we'll add a
4231 Thumb->Arm one and branch directly to the ARM PLT entry.
4232 Here, we have to check if a pre-PLT Thumb->ARM stub
4233 is needed and if it will be close enough. */
4240 /* Thumb branch/call to PLT: it can become a branch to ARM
4241 or to Thumb. We must perform the same checks and
4242 corrections as in elf32_arm_final_link_relocate. */
4245 {
4249 {
4250 /* If the Thumb BLX instruction is available, convert
4251 the BL to a BLX instruction to call the ARM-mode
4252 PLT entry. */
4254 }
4255 else
4256 {
4258 /* Target the Thumb stub before the ARM PLT entry. */
4261 }
4262 }
4263 else
4264 {
4266 }
4267 }
4268 }
4269 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4276 {
4277 /* Handle cases where:
4278 - this call goes too far (different Thumb/Thumb2 max
4279 distance)
4280 - it's a Thumb->Arm call and blx is not available, or it's a
4281 Thumb->Arm branch (not bl). A stub is needed in this case,
4282 but only if this call is not through a PLT entry. Indeed,
4283 PLT stubs handle mode switching already. */
4287 || (thumb2_bl
4290 || (thumb2
4300 {
4301 /* If we need to insert a Thumb-Thumb long branch stub to a
4302 PLT, use one that branches directly to the ARM PLT
4303 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4304 stub, undo this now. */
4306 {
4309 }
4312 {
4313 /* Thumb to thumb. */
4315 {
4317 _bfd_error_handler
4319 " section with SHF_ARM_PURECODE section"
4320 " attribute is only supported for M-profile"
4325 /* PIC stubs. */
4328 /* V5T and above. Stub starts with ARM code, so
4329 we must be able to switch mode before
4330 reaching it, which is only possible for 'bl'
4331 (ie R_ARM_THM_CALL relocation). */
4332 ? arm_stub_long_branch_any_thumb_pic
4333 /* On V4T, use Thumb code only. */
4336 /* non-PIC stubs. */
4339 /* V5T and above. */
4340 ? arm_stub_long_branch_any_any
4341 /* V4T. */
4343 }
4344 else
4345 {
4348 else
4349 {
4351 _bfd_error_handler
4353 " section with SHF_ARM_PURECODE section"
4354 " attribute is only supported for M-profile"
4359 /* PIC stub. */
4360 ? arm_stub_long_branch_thumb_only_pic
4361 /* non-PIC stub. */
4364 }
4365 }
4366 }
4367 else
4368 {
4370 _bfd_error_handler
4372 " section with SHF_ARM_PURECODE section"
4377 /* Thumb to arm. */
4381 {
4382 _bfd_error_handler
4386 }
4388 stub_type =
4390 /* PIC stubs. */
4392 /* TLS PIC stubs. */
4396 /* V5T PIC and above. */
4397 ? arm_stub_long_branch_any_arm_pic
4398 /* V4T PIC stub. */
4401 /* non-PIC stubs. */
4403 /* V5T and above. */
4404 ? arm_stub_long_branch_any_any
4405 /* V4T. */
4408 /* Handle v4t short branches. */
4413 }
4414 }
4415 }
4420 {
4422 _bfd_error_handler
4424 " section with SHF_ARM_PURECODE section"
4425 " attribute is only supported for M-profile"
4429 {
4430 /* Arm to thumb. */
4435 {
4436 _bfd_error_handler
4440 }
4442 /* We have an extra 2-bytes reach because of
4443 the mode change (bit 24 (H) of BLX encoding). */
4449 {
4451 /* PIC stubs. */
4453 /* V5T and above. */
4454 ? arm_stub_long_branch_any_thumb_pic
4455 /* V4T stub. */
4458 /* non-PIC stubs. */
4460 /* V5T and above. */
4461 ? arm_stub_long_branch_any_any
4462 /* V4T. */
4464 }
4465 }
4466 else
4467 {
4468 /* Arm to arm. */
4471 {
4472 stub_type =
4474 /* PIC stubs. */
4476 /* TLS PIC Stub. */
4477 ? arm_stub_long_branch_any_tls_pic
4479 ? arm_stub_long_branch_arm_nacl_pic
4481 /* non-PIC stubs. */
4483 ? arm_stub_long_branch_arm_nacl
4485 }
4486 }
4487 }
4489 /* If a stub is needed, record the actual destination type. */
4494 }
4496 /* Build a name for an entry in the stub hash table. */
4504 {
4506 bfd_size_type len;
4509 {
4518 }
4519 else
4520 {
4532 }
4535 }
4537 /* Look up an entry in the stub hash. Stub entries are cached because
4538 creating the stub name takes a bit of time. */
4547 {
4555 /* If the input section is the CMSE stubs one and it needs a long
4556 branch stub to reach it's final destination, give up with an
4557 error message: this is not supported. See PR ld/24709. */
4559 {
4565 CMSE_STUB_NAME,
4571 /* Exit, rather than leave incompletely processed
4572 relocations. */
4574 }
4576 /* If this input section is part of a group of sections sharing one
4577 stub section, then use the id of the first section in the group.
4578 Stub names need to include a section id, as there may well be
4579 more than one stub used to reach say, printf, and we need to
4580 distinguish between them. */
4588 {
4590 }
4591 else
4592 {
4605 }
4608 }
4610 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4611 section. */
4613 static bfd_boolean
4615 {
4620 {
4626 }
4629 }
4631 /* Required alignment (as a power of 2) for the dedicated section holding
4632 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4633 with input sections. */
4635 static int
4636 arm_dedicated_stub_output_section_required_alignment
4638 {
4643 {
4644 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4645 boundary. */
4652 }
4655 }
4657 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4658 NULL if veneers of this type are interspersed with input sections. */
4662 {
4667 {
4674 }
4677 }
4679 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4680 returns the address of the hash table field in HTAB holding a pointer to the
4681 corresponding input section. Otherwise, returns NULL. */
4686 {
4691 {
4698 }
4701 }
4703 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4704 is the section that branch into veneer and can be NULL if stub should go in
4705 a dedicated output section. Returns a pointer to the stub section, and the
4706 section to which the stub section will be attached (in *LINK_SEC_P).
4707 LINK_SEC_P may be NULL. */
4713 {
4716 bfd_boolean dedicated_output_section =
4721 {
4731 {
4735 }
4736 }
4737 else
4738 {
4748 }
4751 {
4753 bfd_size_type len;
4765 align);
4772 }
4781 }
4783 /* Add a new stub entry to the stub hash. Not all fields of the new
4784 stub entry are initialised. */
4790 {
4796 stub_type);
4800 /* Enter this entry into the linker stub hash table. */
4804 {
4810 }
4817 }
4819 /* Store an Arm insn into an output section not processed by
4820 elf32_arm_write_section. */
4822 static void
4825 {
4828 else
4830 }
4832 /* Store a 16-bit Thumb insn into an output section not processed by
4833 elf32_arm_write_section. */
4835 static void
4838 {
4841 else
4843 }
4845 /* Store a Thumb2 insn into an output section not processed by
4846 elf32_arm_write_section. */
4848 static void
4851 {
4852 /* T2 instructions are 16-bit streamed. */
4854 {
4857 }
4858 else
4859 {
4862 }
4863 }
4865 /* If it's possible to change R_TYPE to a more efficient access
4866 model, return the new reloc type. */
4868 static unsigned
4871 {
4878 /* We do not support relaxations for Old TLS models. */
4880 {
4887 }
4890 }
4892 static bfd_reloc_status_type elf32_arm_final_link_relocate
4898 static unsigned int
4900 {
4902 {
4934 }
4935 }
4937 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4938 veneering (TRUE) or have their own symbol (FALSE). */
4940 static bfd_boolean
4942 {
4947 {
4953 }
4956 }
4958 /* Returns the padding needed for the dedicated section used stubs of type
4959 STUB_TYPE. */
4961 static int
4963 {
4968 {
4974 }
4977 }
4979 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4980 returns the address of the hash table field in HTAB holding the offset at
4981 which new veneers should be layed out in the stub section. */
4986 {
4988 {
4995 }
4996 }
4998 static bfd_boolean
5001 {
5002 #define MAXRELOCS 3
5003 bfd_boolean removed_sg_veneer;
5010 bfd_vma sym_value;
5020 /* Massage our args to the form they really have. */
5024 /* Fail if the target section could not be assigned to an output
5025 section. The user should fix his linker script. */
5040 /* We have to do less-strictly-aligned fixes last. */
5043 /* Assign a slot at the end of section if none assigned yet. */
5045 {
5048 }
5053 /* This is the address of the stub destination. */
5063 {
5065 {
5067 {
5070 {
5071 /* We've borrowed the reloc_addend field to mean we should
5072 insert a condition code into this (Thumb-1 branch)
5073 instruction. See THUMB16_BCOND_INSN. */
5076 }
5079 }
5089 {
5092 }
5099 /* Handle cases where the target is encoded within the
5100 instruction. */
5102 {
5105 }
5119 }
5120 }
5125 /* Stub size has already been computed in arm_size_one_stub. Check
5126 consistency. */
5129 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5133 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5134 to relocate in each stub. */
5135 removed_sg_veneer =
5140 {
5141 Elf_Internal_Rela rel;
5142 bfd_boolean unresolved_reloc;
5144 bfd_vma points_to =
5153 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5154 template should refer back to the instruction after the original
5155 branch. We use target_section as Cortex-A8 erratum workaround stubs
5156 are only generated when both source and target are in the same
5157 section. */
5169 }
5172 #undef MAXRELOCS
5173 }
5175 /* Calculate the template, template size and instruction size for a stub.
5176 Return value is the instruction size. */
5178 static unsigned int
5182 {
5197 {
5199 {
5213 }
5214 }
5217 }
5219 /* As above, but don't actually build the stub. Just bump offset so
5220 we know stub section sizes. */
5222 static bfd_boolean
5225 {
5230 /* Massage our args to the form they really have. */
5239 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5241 {
5245 }
5247 /* Already accounted for. */
5255 }
5257 /* External entry points for sizing and building linker stubs. */
5259 /* Set up various things so that we can make a list of input sections
5260 for each output section included in the link. Returns -1 on error,
5261 0 when no stubs will be needed, and 1 on success. */
5263 int
5266 {
5280 /* Count the number of input BFDs and find the top input section id. */
5284 {
5289 {
5292 }
5293 }
5302 /* We can't use output_bfd->section_count here to find the top output
5303 section index as some sections may have been removed, and
5304 _bfd_strip_section_from_output doesn't renumber the indices. */
5308 {
5311 }
5320 /* For sections we aren't interested in, mark their entries with a
5321 value we can check later. */
5323 do
5330 {
5333 }
5336 }
5338 /* The linker repeatedly calls this function for each input section,
5339 in the order that input sections are linked into output sections.
5340 Build lists of input sections to determine groupings between which
5341 we may insert linker stubs. */
5343 void
5346 {
5353 {
5357 {
5358 /* Steal the link_sec pointer for our list. */
5359 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5360 /* This happens to make the list in reverse order,
5361 which we reverse later. */
5364 }
5365 }
5366 }
5368 /* See whether we can group stub sections together. Grouping stub
5369 sections may result in fewer stubs. More importantly, we need to
5370 put all .init* and .fini* stubs at the end of the .init or
5371 .fini output sections respectively, because glibc splits the
5372 _init and _fini functions into multiple parts. Putting a stub in
5373 the middle of a function is not a good idea. */
5375 static void
5377 bfd_size_type stub_group_size,
5378 bfd_boolean stubs_always_after_branch)
5379 {
5382 do
5383 {
5390 /* Reverse the list: we must avoid placing stubs at the
5391 beginning of the section because the beginning of the text
5392 section may be required for an interrupt vector in bare metal
5393 code. */
5394 #define NEXT_SEC PREV_SEC
5397 {
5398 /* Pop from tail. */
5402 /* Push on head. */
5405 }
5408 {
5412 bfd_vma end_of_next;
5416 {
5420 /* End of NEXT is too far from start, so stop. */
5422 /* Add NEXT to the group. */
5424 }
5426 /* OK, the size from the start to the start of CURR is less
5427 than stub_group_size and thus can be handled by one stub
5428 section. (Or the head section is itself larger than
5429 stub_group_size, in which case we may be toast.)
5430 We should really be keeping track of the total size of
5431 stubs added here, as stubs contribute to the final output
5432 section size. */
5433 do
5434 {
5436 /* Set up this stub group. */
5438 }
5441 /* But wait, there's more! Input sections up to stub_group_size
5442 bytes after the stub section can be handled by it too. */
5444 {
5448 {
5451 /* End of NEXT is too far from stubs, so stop. */
5453 /* Add NEXT to the stub group. */
5457 }
5458 }
5460 }
5461 }
5465 #undef PREV_SEC
5466 #undef NEXT_SEC
5467 }
5469 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5470 erratum fix. */
5472 static int
5474 {
5482 else
5484 }
5489 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5490 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5491 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5492 otherwise. */
5494 static bfd_boolean
5504 {
5517 {
5521 bfd_vma base_vma;
5540 {
5551 /* Span is entirely within a single 4KB region: skip scanning. */
5556 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5558 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5559 * The branch target is in the same 4KB region as the
5560 first half of the branch.
5561 * The instruction before the branch is a 32-bit
5562 length non-branch instruction. */
5564 {
5573 {
5574 /* Load the rest of the insn (in manual-friendly order). */
5577 /* Encoding T4: B<c>.W. */
5579 /* Encoding T1: BL<c>.W. */
5581 /* Encoding T2: BLX<c>.W. */
5583 /* Encoding T3: B<c>.W (not permitted in IT block). */
5586 }
5591 && insn_32bit
5592 && is_32bit_branch
5593 && last_was_32bit
5595 {
5599 bfd_vma target;
5611 {
5615 /* We don't care about the error returned from this
5616 function, only if there is glue or not. */
5623 /* Keep a simpler condition, for the sake of clarity. */
5629 {
5633 else
5635 }
5636 }
5638 /* Check if we have an offending branch instruction. */
5641 /* We've already made a stub for this instruction, e.g.
5642 it's a long branch or a Thumb->ARM stub. Assume that
5643 stub will suffice to work around the A8 erratum (see
5644 setting of always_after_branch above). */
5645 ;
5647 {
5656 }
5658 {
5678 }
5681 {
5684 /* The original instruction is a BL, but the target is
5685 an ARM instruction. If we were not making a stub,
5686 the BL would have been converted to a BLX. Use the
5687 BLX stub instead in that case. */
5690 {
5694 }
5695 /* Conversely, if the original instruction was
5696 BLX but the target is Thumb mode, use the BL
5697 stub. */
5700 {
5704 }
5709 /* If we found a relocation, use the proper destination,
5710 not the offset in the (unrelocated) instruction.
5711 Note this is always done if we switched the stub type
5712 above. */
5714 offset =
5717 /* If the stub will use a Thumb-mode branch to a
5718 PLT target, redirect it to the preceding Thumb
5719 entry point. */
5725 /* The BLX stub is ARM-mode code. Adjust the offset to
5726 take the different PC value (+8 instead of +4) into
5727 account. */
5732 {
5736 {
5742 }
5745 {
5746 /* If we're doing a subsequent scan,
5747 check if we've found the same fix as
5748 before, and try and reuse the stub
5749 name. */
5753 {
5757 }
5758 }
5761 {
5765 }
5778 num_a8_fixes++;
5779 }
5780 }
5781 }
5786 }
5787 }
5791 }
5798 }
5800 /* Create or update a stub entry depending on whether the stub can already be
5801 found in HTAB. The stub is identified by:
5802 - its type STUB_TYPE
5803 - its source branch (note that several can share the same stub) whose
5804 section and relocation (if any) are given by SECTION and IRELA
5805 respectively
5806 - its target symbol whose input section, hash, name, value and branch type
5807 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5808 respectively
5810 If found, the value of the stub's target symbol is updated from SYM_VALUE
5811 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5812 TRUE and the stub entry is initialized.
5814 Returns the stub that was created or updated, or NULL if an error
5815 occurred. */
5824 {
5836 else
5837 {
5842 /* Support for grouping stub sections. */
5845 /* Get the name of this stub. */
5847 stub_type);
5850 }
5853 FALSE);
5854 /* The proper stub has already been created, just update its value. */
5856 {
5861 }
5865 {
5869 }
5879 else
5880 {
5887 {
5890 }
5892 /* For historical reasons, use the existing names for ARM-to-Thumb and
5893 Thumb-to-ARM stubs. */
5904 else
5906 }
5910 }
5912 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5913 gateway veneer to transition from non secure to secure state and create them
5914 accordingly.
5916 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5917 defines the conditions that govern Secure Gateway veneer creation for a
5918 given symbol <SYM> as follows:
5919 - it has function type
5920 - it has non local binding
5921 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5922 same type, binding and value as <SYM> (called normal symbol).
5923 An entry function can handle secure state transition itself in which case
5924 its special symbol would have a different value from the normal symbol.
5926 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5927 entry mapping while HTAB gives the name to hash entry mapping.
5928 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5929 created.
5931 The return value gives whether a stub failed to be allocated. */
5933 static bfd_boolean
5937 {
5945 bfd_vma sym_value;
5961 NULL);
5965 /* Scan symbols. */
5967 {
5971 {
5979 /* Special symbol with local binding. */
5981 }
5982 else
5983 {
5989 /* Special symbol has incorrect binding or type. */
5994 }
5997 {
6003 }
6006 {
6013 }
6019 /* No associated normal symbol or it is neither global nor weak. */
6024 {
6025 /* Initialize here to avoid warning about use of possibly
6026 uninitialized variable. */
6030 {
6031 /* Searching for a normal symbol with local binding. */
6033 {
6034 lsym_name =
6040 }
6041 }
6044 {
6045 _bfd_error_handler
6049 }
6050 else
6051 _bfd_error_handler
6056 }
6062 {
6063 _bfd_error_handler
6067 }
6071 /* If this section is a link-once section that will be discarded, then
6072 don't create any stubs. */
6074 {
6075 _bfd_error_handler
6078 }
6081 {
6082 _bfd_error_handler
6085 }
6090 stub_entry
6097 else
6098 {
6101 }
6102 }
6107 }
6109 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6110 code entry function, ie can be called from non secure code without using a
6111 veneer. */
6113 static bfd_boolean
6115 {
6119 file_ptr offset;
6122 /* Defined symbol of function type. */
6129 /* Read first instruction. */
6139 /* Starts by SG instruction. */
6141 }
6143 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6144 secure gateway veneers (ie. the veneers was not in the input import library)
6145 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6147 static bfd_boolean
6149 {
6153 /* Massage our args to the form they really have. */
6167 }
6169 /* Set offset of each secure gateway veneers so that its address remain
6170 identical to the one in the input import library referred by
6171 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6172 (present in input import library but absent from the executable being
6173 linked) or if new veneers appeared and there is no output import library
6174 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6175 number of secure gateway veneers found in the input import library.
6177 The function returns whether an error occurred. If no error occurred,
6178 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6179 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6180 veneer observed set for new veneers to be layed out after. */
6182 static bfd_boolean
6186 {
6189 flagword flags;
6196 bfd_size_type cmse_stub_size;
6205 /* No input secure gateway import library. */
6211 {
6215 }
6217 /* Get symbol table size. */
6222 /* Read in the input secure gateway import library's symbol table. */
6229 {
6232 }
6235 cmse_stub_size =
6239 out_sec_name =
6241 stub_out_sec =
6246 /* Set addresses of veneers mentionned in input secure gateway import
6247 library's symbol table. */
6249 {
6260 {
6262 "symbol should be absolute, global and "
6267 }
6276 /* Stub entry should have been created by cmse_scan or the symbol be of
6277 a secure function callable from non secure code. */
6279 {
6280 bfd_boolean new_stub;
6282 _bfd_error_handler
6286 stub_entry
6293 else
6294 {
6296 new_cmse_stubs_created++;
6298 }
6301 }
6302 /* Symbol found is not callable from non secure code. */
6304 {
6306 {
6308 sym_name);
6310 }
6312 }
6313 else
6314 {
6315 /* Only stubs for SG veneers should have been created. */
6318 /* Check visibility hasn't changed. */
6321 _bfd_error_handler
6323 sym_name);
6326 }
6328 /* Size should match that of a SG veneer. */
6330 {
6334 }
6336 /* Previous veneer address is before current SG veneer section. */
6338 {
6339 /* Avoid offset underflow. */
6344 }
6346 /* Complain if stub offset not a multiple of stub size. */
6348 {
6349 _bfd_error_handler
6353 }
6358 new_cmse_stubs_created--;
6364 }
6367 {
6369 _bfd_error_handler
6373 }
6376 {
6377 _bfd_error_handler
6379 out_sec_name);
6381 }
6383 free_sym_buf:
6386 }
6388 /* Determine and set the size of the stub section for a final link.
6390 The basic idea here is to examine all the relocations looking for
6391 PC-relative calls to a target that is unreachable with a "bl"
6392 instruction. */
6394 bfd_boolean
6398 bfd_signed_vma group_size,
6400 asection *,
6403 {
6407 bfd_size_type stub_group_size;
6419 {
6424 }
6426 /* Propagate mach to stub bfd, because it may not have been
6427 finalized when we created stub_bfd. */
6431 /* Stash our params away. */
6440 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6441 as the first half of a 32-bit branch straddling two 4K pages. This is a
6442 crude way of enforcing that. */
6448 else
6452 {
6453 /* Default values. */
6454 /* Thumb branch range is +-4MB has to be used as the default
6455 maximum size (a given section can contain both ARM and Thumb
6456 code, so the worst case has to be taken into account).
6458 This value is 24K less than that, which allows for 2025
6459 12-byte stubs. If we exceed that, then we will fail to link.
6460 The user will have to relink with an explicit group size
6461 option. */
6463 }
6467 /* If we're applying the cortex A8 fix, we need to determine the
6468 program header size now, because we cannot change it later --
6469 that could alter section placements. Notice the A8 erratum fix
6470 ends up requiring the section addresses to remain unchanged
6471 modulo the page size. That's something we cannot represent
6472 inside BFD, and we don't want to force the section alignment to
6473 be the page size. */
6478 {
6490 {
6504 /* We'll need the symbol table in a second. */
6509 /* Limit scan of symbols to object file whose profile is
6510 Microcontroller to not hinder performance in the general case. */
6512 {
6522 }
6524 /* Walk over each section attached to the input bfd. */
6528 {
6531 /* If there aren't any relocs, then there's nothing more
6532 to do. */
6538 /* If this section is a link-once section that will be
6539 discarded, then don't create any stubs. */
6544 /* Get the relocs. */
6545 internal_relocs
6551 /* Now examine each relocation. */
6555 {
6558 bfd_vma sym_value;
6559 bfd_vma destination;
6570 {
6572 error_ret_free_internal:
6575 /* Fall through. */
6576 error_ret_free_local:
6580 }
6584 hash = elf32_arm_hash_entry
6588 /* Only look for stubs on branch instructions, or
6589 non-relaxed TLSCALL */
6602 : (elf32_arm_local_got_tls_type
6607 /* Now determine the call target, its name, value,
6608 section. */
6616 {
6617 /* A non-relaxed TLS call. The target is the
6618 plt-resident trampoline and nothing to do
6619 with the symbol. */
6626 }
6628 {
6629 /* It's a local symbol. */
6633 {
6634 local_syms
6637 local_syms
6643 }
6652 else
6653 sym_sec =
6657 /* This is an undefined symbol. It can never
6658 be resolved. */
6667 branch_type =
6669 sym_name
6673 }
6674 else
6675 {
6676 /* It's an external symbol. */
6684 {
6691 /* For a destination in a shared library,
6692 use the PLT stub as target address to
6693 decide whether a branch stub is
6694 needed. */
6699 {
6703 destination = (sym_value
6706 }
6711 }
6714 {
6715 /* For a shared library, use the PLT stub as
6716 target address to decide whether a long
6717 branch stub is needed.
6718 For absolute code, they cannot be handled. */
6726 {
6730 destination = (sym_value
6733 }
6734 else
6736 }
6737 else
6738 {
6741 }
6743 branch_type =
6746 }
6748 do
6749 {
6750 bfd_boolean new_stub;
6753 /* Determine what (if any) linker stub is needed. */
6761 /* We've either created a stub for this reloc already,
6762 or we are about to. */
6763 stub_entry =
6774 else
6776 }
6779 /* Look for relocations which might trigger Cortex-A8
6780 erratum. */
6786 {
6792 {
6793 /* Found a candidate. Note we haven't checked the
6794 destination is within 4K here: if we do so (and
6795 don't create an entry in a8_relocs) we can't tell
6796 that a branch should have been relocated when
6797 scanning later. */
6799 {
6805 }
6815 num_a8_relocs++;
6816 }
6817 }
6818 }
6820 /* We're done with the internal relocs, free them. */
6823 }
6826 {
6827 /* Sort relocs which might apply to Cortex-A8 erratum. */
6832 /* Scan for branches which might trigger Cortex-A8 erratum. */
6839 }
6843 {
6846 else
6848 }
6849 }
6862 /* OK, we've added some stubs. Find out the new size of the
6863 stub sections. */
6867 {
6868 /* Ignore non-stub sections. */
6873 }
6875 /* Add new SG veneers after those already in the input import
6876 library. */
6878 stub_type++)
6879 {
6891 }
6893 /* Compute stub section size, considering padding. */
6896 stub_type++)
6897 {
6903 /* Skip if no stub input section or no stub section padding
6904 required. */
6907 /* Stub section padding required but no dedicated section. */
6913 }
6915 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6918 {
6925 stub_sec->size
6927 NULL);
6928 }
6931 /* Ask the linker to do its stuff. */
6934 }
6936 /* Add stubs for Cortex-A8 erratum fixes now. */
6938 {
6940 {
6953 {
6957 }
6976 }
6978 /* Stash the Cortex-A8 erratum fix array for use later in
6979 elf32_arm_write_section(). */
6982 }
6983 else
6984 {
6987 }
6989 }
6991 /* Build all the stubs associated with the current output file. The
6992 stubs are kept in a hash table attached to the main linker hash
6993 table. We also set up the .plt entries for statically linked PIC
6994 functions here. This function is called via arm_elf_finish in the
6995 linker. */
6997 bfd_boolean
6999 {
7012 {
7013 bfd_size_type size;
7015 /* Ignore non-stub sections. */
7019 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
7020 must at least be done for stub section requiring padding and for SG
7021 veneers to ensure that a non secure code branching to a removed SG
7022 veneer causes an error. */
7029 }
7031 /* Add new SG veneers after those already in the input import library. */
7033 {
7045 }
7047 /* Build the stubs as directed by the stub hash table. */
7051 {
7052 /* Place the cortex a8 stubs last. */
7055 }
7058 }
7060 /* Locate the Thumb encoded calling stub for NAME. */
7066 {
7071 /* We need a pointer to the armelf specific hash table. */
7083 hash = elf_link_hash_lookup
7094 }
7096 /* Locate the ARM encoded calling stub for NAME. */
7102 {
7107 /* We need a pointer to the elfarm specific hash table. */
7118 myh = elf_link_hash_lookup
7129 }
7131 /* ARM->Thumb glue (static images):
7133 .arm
7134 __func_from_arm:
7135 ldr r12, __func_addr
7136 bx r12
7137 __func_addr:
7138 .word func @ behave as if you saw a ARM_32 reloc.
7140 (v5t static images)
7141 .arm
7142 __func_from_arm:
7143 ldr pc, __func_addr
7144 __func_addr:
7145 .word func @ behave as if you saw a ARM_32 reloc.
7147 (relocatable images)
7148 .arm
7149 __func_from_arm:
7150 ldr r12, __func_offset
7151 add r12, r12, pc
7152 bx r12
7153 __func_offset:
7154 .word func - . */
7156 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7161 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7165 #define ARM2THUMB_PIC_GLUE_SIZE 16
7170 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7172 .thumb .thumb
7173 .align 2 .align 2
7174 __func_from_thumb: __func_from_thumb:
7175 bx pc push {r6, lr}
7176 nop ldr r6, __func_addr
7177 .arm mov lr, pc
7178 b func bx r6
7179 .arm
7180 ;; back_to_thumb
7181 ldmia r13! {r6, lr}
7182 bx lr
7183 __func_addr:
7184 .word func */
7186 #define THUMB2ARM_GLUE_SIZE 8
7191 #define VFP11_ERRATUM_VENEER_SIZE 8
7192 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7193 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7195 #define ARM_BX_VENEER_SIZE 12
7200 #ifndef ELFARM_NABI_C_INCLUDED
7201 static void
7203 {
7208 {
7209 /* Do not include empty glue sections in the output. */
7211 {
7215 }
7217 }
7228 }
7230 bfd_boolean
7232 {
7240 ARM2THUMB_GLUE_SECTION_NAME);
7244 THUMB2ARM_GLUE_SECTION_NAME);
7248 VFP11_ERRATUM_VENEER_SECTION_NAME);
7252 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7256 ARM_BX_GLUE_SECTION_NAME);
7259 }
7261 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7262 returns the symbol identifying the stub. */
7267 {
7274 bfd_vma val;
7275 bfd_size_type size;
7281 s = bfd_get_linker_section
7292 myh = elf_link_hash_lookup
7296 {
7297 /* We've already seen this guy. */
7300 }
7302 /* The only trick here is using hash_table->arm_glue_size as the value.
7303 Even though the section isn't allocated yet, this is where we will be
7304 putting it. The +1 on the value marks that the stub has not been
7305 output yet - not that it is a Thumb function. */
7324 else
7331 }
7333 /* Allocate space for ARMv4 BX veneers. */
7335 static void
7337 {
7343 bfd_vma val;
7345 /* BX PC does not need a veneer. */
7353 /* Check if this veneer has already been allocated. */
7357 s = bfd_get_linker_section
7362 /* Add symbol for veneer. */
7369 myh = elf_link_hash_lookup
7387 }
7390 /* Add an entry to the code/data map for section SEC. */
7392 static void
7394 {
7399 {
7404 }
7409 {
7414 }
7417 {
7420 }
7421 }
7424 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7425 veneers are handled for now. */
7427 static bfd_vma
7433 {
7439 bfd_vma val;
7447 s = bfd_get_linker_section
7461 myh = elf_link_hash_lookup
7476 /* Link veneer back to calling location. */
7490 /* A symbol for the return from the veneer. */
7494 myh = elf_link_hash_lookup
7511 /* Generate a mapping symbol for the veneer section, and explicitly add an
7512 entry for that symbol to the code/data map for the section. */
7514 {
7516 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7517 ever requires this erratum fix. */
7527 /* The elf32_arm_init_maps function only cares about symbols from input
7528 BFDs. We must make a note of this generated mapping symbol
7529 ourselves so that code byteswapping works properly in
7530 elf32_arm_write_section. */
7532 }
7538 /* The offset of the veneer. */
7540 }
7542 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7543 veneers need to be handled because used only in Cortex-M. */
7545 static bfd_vma
7551 bfd_size_type veneer_size)
7552 {
7558 bfd_vma val;
7566 s = bfd_get_linker_section
7580 myh = elf_link_hash_lookup
7595 /* Link veneer back to calling location. */
7609 /* A symbol for the return from the veneer. */
7613 myh = elf_link_hash_lookup
7630 /* Generate a mapping symbol for the veneer section, and explicitly add an
7631 entry for that symbol to the code/data map for the section. */
7633 {
7635 /* Creates a THUMB symbol since there is no other choice. */
7645 /* The elf32_arm_init_maps function only cares about symbols from input
7646 BFDs. We must make a note of this generated mapping symbol
7647 ourselves so that code byteswapping works properly in
7648 elf32_arm_write_section. */
7650 }
7656 /* The offset of the veneer. */
7658 }
7660 #define ARM_GLUE_SECTION_FLAGS \
7661 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7662 | SEC_READONLY | SEC_LINKER_CREATED)
7664 /* Create a fake section for use by the ARM backend of the linker. */
7666 static bfd_boolean
7668 {
7673 /* Already made. */
7682 /* Set the gc mark to prevent the section from being removed by garbage
7683 collection, despite the fact that no relocs refer to this section. */
7687 }
7689 /* Set size of .plt entries. This function is called from the
7690 linker scripts in ld/emultempl/{armelf}.em. */
7692 void
7694 {
7696 }
7698 /* Add the glue sections to ABFD. This function is called from the
7699 linker scripts in ld/emultempl/{armelf}.em. */
7701 bfd_boolean
7704 {
7706 bfd_boolean dostm32l4xx = globals
7708 bfd_boolean addglue;
7710 /* If we are only performing a partial
7711 link do not bother adding the glue. */
7723 return addglue
7725 }
7727 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7728 ensures they are not marked for deletion by
7729 strip_excluded_output_sections () when veneers are going to be created
7730 later. Not doing so would trigger assert on empty section size in
7731 lang_size_sections_1 (). */
7733 void
7735 {
7738 /* If we are only performing a partial
7739 link do not bother adding the glue. */
7744 {
7755 }
7756 }
7758 /* Select a BFD to be used to hold the sections used by the glue code.
7759 This function is called from the linker scripts in ld/emultempl/
7760 {armelf/pe}.em. */
7762 bfd_boolean
7764 {
7767 /* If we are only performing a partial link
7768 do not bother getting a bfd to hold the glue. */
7772 /* Make sure we don't attach the glue sections to a dynamic object. */
7781 /* Save the bfd for later use. */
7785 }
7787 static void
7789 {
7793 Tag_CPU_arch);
7796 {
7799 }
7800 else
7801 {
7804 }
7805 }
7807 bfd_boolean
7810 {
7819 /* If we are only performing a partial link do not bother
7820 to construct any glue. */
7824 /* Here we have a bfd that is to be included on the link. We have a
7825 hook to do reloc rummaging, before section sizes are nailed down. */
7832 {
7834 abfd);
7836 }
7838 /* PR 5398: If we have not decided to include any loadable sections in
7839 the output then we will not have a glue owner bfd. This is OK, it
7840 just means that there is nothing else for us to do here. */
7844 /* Rummage around all the relocs and map the glue vectors. */
7851 {
7860 /* Load the relocs. */
7861 internal_relocs
7869 {
7878 /* These are the only relocation types we care about. */
7883 /* Get the section contents if we haven't done so already. */
7885 {
7886 /* Get cached copy if it exists. */
7889 else
7890 {
7891 /* Go get them off disk. */
7894 }
7895 }
7898 {
7904 }
7906 /* If the relocation is not against a symbol it cannot concern us. */
7909 /* We don't care about local symbols. */
7913 /* This is an external symbol. */
7918 /* If the relocation is against a static symbol it must be within
7919 the current section and so cannot be a cross ARM/Thumb relocation. */
7923 /* If the call will go through a PLT entry then we do not need
7924 glue. */
7929 {
7931 /* This one is a call from arm code. We need to look up
7932 the target of the call. If it is a thumb target, we
7933 insert glue. */
7941 }
7942 }
7951 }
7955 error_return:
7962 }
7963 #endif
7966 /* Initialise maps of ARM/Thumb/data for input BFDs. */
7968 void
7970 {
7975 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7985 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7986 should contain the number of local symbols, which should come before any
7987 global symbols. Mapping symbols are always local. */
7989 NULL);
7991 /* No internal symbols read? Skip this BFD. */
7996 {
8003 {
8008 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
8010 }
8011 }
8012 }
8015 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8016 say what they wanted. */
8018 void
8020 {
8028 {
8029 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8034 else
8036 }
8037 }
8040 void
8042 {
8048 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8050 {
8052 {
8059 /* Give a warning, but do as the user requests anyway. */
8062 }
8063 }
8065 /* For earlier architectures, we might need the workaround, but do not
8066 enable it by default. If users is running with broken hardware, they
8067 must enable the erratum fix explicitly. */
8069 }
8071 void
8073 {
8080 /* We assume only Cortex-M4 may require the fix. */
8083 {
8085 /* Give a warning, but do as the user requests anyway. */
8086 _bfd_error_handler
8089 }
8090 }
8092 enum bfd_arm_vfp11_pipe
8093 {
8094 VFP11_FMAC,
8095 VFP11_LS,
8096 VFP11_DS,
8097 VFP11_BAD
8098 };
8100 /* Return a VFP register number. This is encoded as RX:X for single-precision
8101 registers, or X:RX for double-precision registers, where RX is the group of
8102 four bits in the instruction encoding and X is the single extension bit.
8103 RX and X fields are specified using their lowest (starting) bit. The return
8104 value is:
8106 0...31: single-precision registers s0...s31
8107 32...63: double-precision registers d0...d31.
8109 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8110 encounter VFP3 instructions, so we allow the full range for DP registers. */
8112 static unsigned int
8115 {
8118 else
8120 }
8122 /* Set bits in *WMASK according to a register number REG as encoded by
8123 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8125 static void
8127 {
8132 }
8134 /* Return TRUE if WMASK overwrites anything in REGS. */
8136 static bfd_boolean
8138 {
8142 {
8155 }
8158 }
8160 /* In this function, we're interested in two things: finding input registers
8161 for VFP data-processing instructions, and finding the set of registers which
8162 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8163 hold the written set, so FLDM etc. are easy to deal with (we're only
8164 interested in 32 SP registers or 16 dp registers, due to the VFP version
8165 implemented by the chip in question). DP registers are marked by setting
8166 both SP registers in the write mask). */
8168 static enum bfd_arm_vfp11_pipe
8171 {
8176 {
8186 {
8208 vfp_binop:
8216 {
8221 {
8235 /* These instructions will not bounce due to underflow. */
8241 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8242 registers to cause the erratum in previous instructions. */
8248 {
8253 /* Only FCVTSD can underflow. */
8260 }
8265 }
8266 }
8271 }
8272 }
8273 /* Two-register transfer. */
8275 {
8279 {
8282 else
8283 {
8286 }
8287 }
8290 }
8292 {
8297 {
8304 {
8312 }
8322 }
8325 }
8326 /* Single-register transfer. Note L==0. */
8328 {
8333 {
8336 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8337 destination register. I don't know if this is exactly right,
8338 but it is the conservative choice. */
8344 }
8347 }
8350 }
8356 /* Look for potentially-troublesome code sequences which might trigger the
8357 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8358 (available from ARM) for details of the erratum. A short version is
8359 described in ld.texinfo. */
8361 bfd_boolean
8363 {
8374 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8375 The states transition as follows:
8377 0 -> 1 (vector) or 0 -> 2 (scalar)
8378 A VFP FMAC-pipeline instruction has been seen. Fill
8379 regs[0]..regs[numregs-1] with its input operands. Remember this
8380 instruction in 'first_fmac'.
8382 1 -> 2
8383 Any instruction, except for a VFP instruction which overwrites
8384 regs[*].
8386 1 -> 3 [ -> 0 ] or
8387 2 -> 3 [ -> 0 ]
8388 A VFP instruction has been seen which overwrites any of regs[*].
8389 We must make a veneer! Reset state to 0 before examining next
8390 instruction.
8392 2 -> 0
8393 If we fail to match anything in state 2, reset to state 0 and reset
8394 the instruction pointer to the instruction after 'first_fmac'.
8396 If the VFP11 vector mode is in use, there must be at least two unrelated
8397 instructions between anti-dependent VFP11 instructions to properly avoid
8398 triggering the erratum, hence the use of the extra state 1. */
8400 /* If we are only performing a partial link do not bother
8401 to construct any glue. */
8405 /* Skip if this bfd does not correspond to an ELF image. */
8409 /* We should have chosen a fix type by the time we get here. */
8415 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8420 {
8424 /* If we don't have executable progbits, we're not interested in this
8425 section. Also skip if section is to be excluded. */
8445 elf32_arm_compare_mapping);
8448 {
8454 /* FIXME: Only ARM mode is supported at present. We may need to
8455 support Thumb-2 mode also at some point. */
8460 {
8475 {
8479 /* I'm assuming the VFP11 erratum can trigger with denorm
8480 operands on either the FMAC or the DS pipeline. This might
8481 lead to slightly overenthusiastic veneer insertion. */
8483 {
8487 }
8491 {
8494 other_regs,
8498 numregs))
8500 else
8502 }
8506 {
8509 other_regs,
8513 numregs))
8515 else
8516 {
8519 }
8520 }
8525 }
8528 {
8537 {
8544 }
8547 first_fmac);
8555 }
8558 }
8559 }
8564 }
8568 error_return:
8573 }
8575 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8576 after sections have been laid out, using specially-named symbols. */
8578 void
8581 {
8589 /* Skip if this bfd does not correspond to an ELF image. */
8602 {
8607 {
8609 bfd_vma vma;
8612 {
8615 /* Find veneer symbol. */
8619 myh = elf_link_hash_lookup
8635 /* Find return location. */
8639 myh = elf_link_hash_lookup
8655 }
8656 }
8657 }
8660 }
8662 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8663 return locations after sections have been laid out, using
8664 specially-named symbols. */
8666 void
8669 {
8677 /* Skip if this bfd does not correspond to an ELF image. */
8690 {
8695 {
8697 bfd_vma vma;
8700 {
8702 /* Find veneer symbol. */
8706 myh = elf_link_hash_lookup
8721 /* Find return location. */
8725 myh = elf_link_hash_lookup
8741 }
8742 }
8743 }
8746 }
8750 {
8751 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8752 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8754 }
8758 {
8759 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8760 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8762 }
8766 {
8767 /* A6.5 Extension register load or store instruction
8768 A7.7.229
8769 We look for SP 32-bit and DP 64-bit registers.
8770 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8771 <list> is consecutive 64-bit registers
8772 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8773 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8774 <list> is consecutive 32-bit registers
8775 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8776 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8777 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8778 return
8783 /* (IA with !), includes VPOP (when reg number is SP). */
8785 /* (DB with !). */
8787 }
8789 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8790 VLDM opcode and:
8791 - computes the number and the mode of memory accesses
8792 - decides if the replacement should be done:
8793 . replaces only if > 8-word accesses
8794 . or (testing purposes only) replaces all accesses. */
8796 static bfd_boolean
8798 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8799 {
8802 /* The field encoding the register list is the same for both LDMIA
8803 and LDMDB encodings. */
8809 /* DEFAULT mode accounts for the real bug condition situation,
8810 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8811 return
8814 }
8816 /* Look for potentially-troublesome code sequences which might trigger
8817 the STM STM32L4XX erratum. */
8819 bfd_boolean
8822 {
8830 /* If we are only performing a partial link do not bother
8831 to construct any glue. */
8835 /* Skip if this bfd does not correspond to an ELF image. */
8842 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8847 {
8851 /* If we don't have executable progbits, we're not interested in this
8852 section. Also skip if section is to be excluded. */
8872 elf32_arm_compare_mapping);
8875 {
8882 /* Only Thumb2 mode need be supported with this CM4 specific
8883 code, we should not encounter any arm mode eg span_type
8884 != 'a'. */
8889 {
8896 /* The first 16-bits of all 32-bit thumb2 instructions start
8897 with opcode[15..13]=0b111 and the encoded op1 can be anything
8898 except opcode[12..11]!=0b00.
8899 See 32-bit Thumb instruction encoding. */
8903 /* Compute the predicate that tells if the instruction
8904 is concerned by the IT block
8905 - Creates an error if there is a ldm that is not
8906 last in the IT block thus cannot be replaced
8907 - Otherwise we can create a branch at the end of the
8908 IT block, it will be controlled naturally by IT
8909 with the proper pseudo-predicate
8910 - So the only interesting predicate is the one that
8911 tells that we are not on the last item of an IT
8912 block. */
8917 {
8918 /* Load the rest of the insn (in manual-friendly order). */
8923 /* Veneers are created for (v)ldm depending on
8924 option flags and memory accesses conditions; but
8925 if the instruction is not the last instruction of
8926 an IT block, we cannot create a jump there, so we
8927 bail out. */
8929 && stm32l4xx_need_create_replacing_stub
8931 {
8933 {
8934 _bfd_error_handler
8935 /* xgettext:c-format */
8937 " in non-last IT block instruction:"
8938 " STM32L4XX veneer cannot be generated; "
8939 "use gcc option -mrestrict-it to generate"
8942 }
8943 else
8944 {
8947 bfd_zmalloc
8953 /* We create only thumb branches. */
8955 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8956 record_stm32l4xx_erratum_veneer
8958 i,
8959 is_ldm ?
8960 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8961 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8965 }
8966 }
8967 }
8968 else
8969 {
8970 /* A7.7.37 IT p208
8971 IT blocks are only encoded in T1
8972 Encoding T1: IT{x{y{z}}} <firstcond>
8973 1 0 1 1 - 1 1 1 1 - firstcond - mask
8974 if mask = '0000' then see 'related encodings'
8975 We don't deal with UNPREDICTABLE, just ignore these.
8976 There can be no nested IT blocks so an IT block
8977 is naturally a new one for which it is worth
8978 computing its size. */
8981 /* If we have a new IT block we compute its size. */
8983 {
8984 /* Compute the number of instructions controlled
8985 by the IT block, it will be used to decide
8986 whether we are inside an IT block or not. */
8989 }
8990 }
8993 }
8994 }
8999 }
9003 error_return:
9008 }
9010 /* Set target relocation values needed during linking. */
9012 void
9016 {
9032 else
9033 {
9036 }
9043 else
9055 }
9057 /* Replace the target offset of a Thumb bl or b.w instruction. */
9059 static void
9061 {
9062 bfd_vma upper;
9063 bfd_vma lower;
9080 }
9082 /* Thumb code calling an ARM function. */
9084 static int
9092 bfd_vma offset,
9093 bfd_signed_vma addend,
9094 bfd_vma val,
9096 {
9098 bfd_vma my_offset;
9114 THUMB2ARM_GLUE_SECTION_NAME);
9121 {
9125 {
9126 _bfd_error_handler
9132 }
9143 ret_offset =
9144 /* Address of destination of the stub. */
9147 /* Offset from the start of the current section
9148 to the start of the stubs. */
9150 /* Offset of the start of this stub from the start of the stubs. */
9151 + my_offset
9152 /* Address of the start of the current section. */
9154 /* The branch instruction is 4 bytes into the stub. */
9156 /* ARM branches work from the pc of the instruction + 8. */
9162 }
9166 /* Now go back and fix up the original BL insn to point to here. */
9167 ret_offset =
9168 /* Address of where the stub is located. */
9170 /* Address of where the BL is located. */
9173 /* Addend in the relocation. */
9174 - addend
9175 /* Biassing for PC-relative addressing. */
9181 }
9183 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9191 bfd_vma val,
9194 {
9195 bfd_vma my_offset;
9211 {
9215 {
9216 _bfd_error_handler
9220 }
9228 {
9229 /* For relocatable objects we can't use absolute addresses,
9230 so construct the address from a relative offset. */
9231 /* TODO: If the offset is small it's probably worth
9232 constructing the address with adds. */
9239 /* Adjust the offset by 4 for the position of the add,
9240 and 8 for the pipeline offset. */
9247 }
9249 {
9253 /* It's a thumb address. Add the low order bit. */
9256 }
9257 else
9258 {
9265 /* It's a thumb address. Add the low order bit. */
9270 }
9271 }
9276 }
9278 /* Arm code calling a Thumb function. */
9280 static int
9288 bfd_vma offset,
9289 bfd_signed_vma addend,
9290 bfd_vma val,
9292 {
9294 bfd_vma my_offset;
9305 ARM2THUMB_GLUE_SECTION_NAME);
9319 /* Somehow these are both 4 too far, so subtract 8. */
9321 + my_offset
9333 }
9335 /* Populate Arm stub for an exported Thumb function. */
9337 static bfd_boolean
9339 {
9346 bfd_vma val;
9350 /* Allocate stubs for exported Thumb functions on v4t. */
9359 ARM2THUMB_GLUE_SECTION_NAME);
9377 }
9379 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9381 static bfd_vma
9383 {
9385 bfd_vma glue_addr;
9394 ARM_BX_GLUE_SECTION_NAME);
9404 {
9410 }
9413 }
9415 /* Generate Arm stubs for exported Thumb symbols. */
9416 static void
9419 {
9423 /* Ignore this if we are not called by the ELF backend linker. */
9430 /* If blx is available then exported Thumb symbols are OK and there is
9431 nothing to do. */
9436 link_info);
9437 }
9439 /* Reserve space for COUNT dynamic relocations in relocation selection
9440 SRELOC. */
9442 static void
9444 bfd_size_type count)
9445 {
9453 }
9455 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9456 dynamic, the relocations should go in SRELOC, otherwise they should
9457 go in the special .rel.iplt section. */
9459 static void
9461 bfd_size_type count)
9462 {
9468 else
9469 {
9472 }
9473 }
9475 /* Add relocation REL to the end of relocation section SRELOC. */
9477 static void
9480 {
9495 }
9497 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9498 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9499 to .plt. */
9501 static void
9503 bfd_boolean is_iplt_entry,
9506 {
9514 {
9518 /* NaCl uses a special first entry in .iplt too. */
9522 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9524 }
9525 else
9526 {
9531 {
9532 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9533 /* For lazy binding, relocations will be put into .rel.plt, in
9534 .rel.got otherwise. */
9535 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9538 else
9540 }
9541 else
9542 {
9543 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9545 }
9547 /* If this is the first .plt entry, make room for the special
9548 first entry. */
9553 }
9555 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9562 {
9563 /* We also need to make an entry in the .got.plt section, which
9564 will be placed in the .got section by the linker script. */
9567 else
9570 /* Function descriptor takes 64 bits in GOT. */
9572 else
9574 }
9575 }
9577 static bfd_vma
9579 {
9581 }
9583 static bfd_vma
9585 {
9587 }
9589 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9590 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9591 Otherwise, DYNINDX is the index of the symbol in the dynamic
9592 symbol table and SYM_VALUE is undefined.
9594 ROOT_PLT points to the offset of the PLT entry from the start of its
9595 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9596 bookkeeping information.
9598 Returns FALSE if there was a problem. */
9600 static bfd_boolean
9605 {
9611 bfd_vma plt_index;
9612 Elf_Internal_Rela rel;
9613 bfd_vma plt_header_size;
9614 bfd_vma got_header_size;
9618 /* Pick the appropriate sections and sizes. */
9620 {
9625 /* There are no reserved entries in .igot.plt, and no special
9626 first entry in .iplt. */
9629 }
9630 else
9631 {
9638 }
9641 /* Fill in the entry in the procedure linkage table. */
9643 {
9652 /* Fill in the entry in the .rel.plt section. */
9658 /* Get the index in the procedure linkage table which
9659 corresponds to this symbol. This is the index of this symbol
9660 in all the symbols for which we are making plt entries. The
9661 first entry in the procedure linkage table is reserved. */
9664 }
9665 else
9666 {
9673 /* Get the offset into the .(i)got.plt table of the entry that
9674 corresponds to this function. */
9677 /* Get the index in the procedure linkage table which
9678 corresponds to this symbol. This is the index of this symbol
9679 in all the symbols for which we are making plt entries.
9680 After the reserved .got.plt entries, all symbols appear in
9681 the same order as in .plt. */
9683 /* Function descriptor takes 8 bytes. */
9685 else
9688 /* Calculate the address of the GOT entry. */
9693 /* ...and the address of the PLT entry. */
9700 {
9702 bfd_vma val;
9705 {
9713 else
9715 }
9716 }
9718 {
9720 bfd_vma val;
9723 {
9733 else
9735 }
9740 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9741 referencing the GOT for this PLT entry. */
9748 /* Create the R_ARM_ABS32 relocation referencing the
9749 beginning of the PLT for this GOT entry. */
9754 }
9756 {
9757 /* Calculate the displacement between the PLT slot and the
9758 common tail that's part of the special initial PLT slot. */
9759 int32_t tail_displacement
9769 /* Calculate the displacement between the PLT slot and the entry
9770 in the GOT. The offset accounts for the value produced by
9771 adding to pc in the penultimate instruction of the PLT stub. */
9772 got_displacement = (got_address
9775 /* NaCl does not support interworking at all. */
9793 }
9795 {
9797 ? elf32_arm_fdpic_thumb_plt_entry
9800 /* Fill-up Thumb stub if needed. */
9802 {
9807 }
9808 /* As we are using 32 bit instructions even for the Thumb
9809 version, we have to use 'put_arm_insn' instead of
9810 'put_thumb_insn'. */
9818 {
9819 /* funcdesc_value_reloc_offset. */
9827 }
9828 }
9830 {
9831 /* PR ld/16017: Generate thumb only PLT entries. */
9833 {
9834 /* FIXME: We ought to be able to generate thumb-1 PLT
9835 instructions... */
9837 output_bfd);
9839 }
9841 /* Calculate the displacement between the PLT slot and the entry in
9842 the GOT. The 12-byte offset accounts for the value produced by
9843 adding to pc in the 3rd instruction of the PLT stub. */
9846 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9847 instead of 'put_thumb_insn'. */
9868 }
9869 else
9870 {
9871 /* Calculate the displacement between the PLT slot and the
9872 entry in the GOT. The eight-byte offset accounts for the
9873 value produced by adding to pc in the first instruction
9874 of the PLT stub. */
9878 {
9883 }
9886 {
9901 #ifdef FOUR_WORD_PLT
9903 #endif
9904 }
9905 else
9906 {
9923 }
9924 }
9926 /* Fill in the entry in the .rel(a).(i)plt section. */
9930 {
9931 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9932 The dynamic linker or static executable then calls SYM_VALUE
9933 to determine the correct run-time value of the .igot.plt entry. */
9936 }
9937 else
9938 {
9939 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9940 used by PLT entry. */
9942 {
9945 }
9946 else
9947 {
9952 /* PR ld/16017
9953 When thumb only we need to set the LSB for any address that
9954 will be used with an interworking branch instruction. */
9957 }
9958 }
9960 /* Fill in the entry in the global offset table. */
9965 {
9966 /* Setup initial funcdesc value. */
9967 /* FIXME: we don't support lazy binding because there is a
9968 race condition between both words getting written and
9969 some other thread attempting to read them. The ARM
9970 architecture does not have an atomic 64 bit load/store
9971 instruction that could be used to prevent it; it is
9972 recommended that threaded FDPIC applications run with the
9973 LD_BIND_NOW environment variable set. */
9978 }
9979 }
9983 else
9984 {
9986 {
9987 /* For FDPIC we put PLT relocationss into .rel.got when not
9988 lazy binding otherwise we put them in .rel.plt. For now,
9989 we don't support lazy binding so put it in .rel.got. */
9992 else
9994 }
9995 else
9996 {
9999 }
10000 }
10003 }
10005 /* Some relocations map to different relocations depending on the
10006 target. Return the real relocation. */
10008 static int
10011 {
10013 {
10017 else
10025 }
10026 }
10028 /* Return the base VMA address which should be subtracted from real addresses
10029 when resolving @dtpoff relocation.
10030 This is PT_TLS segment p_vaddr. */
10032 static bfd_vma
10034 {
10035 /* If tls_sec is NULL, we should have signalled an error already. */
10039 }
10041 /* Return the relocation value for @tpoff relocation
10042 if STT_TLS virtual address is ADDRESS. */
10044 static bfd_vma
10046 {
10048 bfd_vma base;
10050 /* If tls_sec is NULL, we should have signalled an error already. */
10055 }
10057 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10058 VALUE is the relocation value. */
10060 static bfd_reloc_status_type
10062 {
10069 }
10071 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10072 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10073 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10075 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10076 is to then call final_link_relocate. Return other values in the
10077 case of error.
10079 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10080 the pre-relaxed code. It would be nice if the relocs were updated
10081 to match the optimization. */
10083 static bfd_reloc_status_type
10087 {
10091 {
10098 else
10099 {
10103 else
10105 }
10110 /* Thumb insn. */
10113 {
10115 /* nop */
10117 }
10119 {
10121 /* nop */
10123 else
10124 /* ldr rx,[ry] */
10126 }
10128 {
10130 /* nop */
10132 else
10133 /* mov r0, rx */
10136 }
10137 else
10138 {
10140 /* It's a 32 bit instruction, fetch the rest of it for
10141 error generation. */
10144 _bfd_error_handler
10145 /* xgettext:c-format */
10151 }
10155 /* arm insn. */
10158 {
10160 /* mov rx, ry */
10163 }
10165 {
10167 /* nop */
10169 else
10170 /* ldr rx,[ry] */
10173 }
10175 {
10177 /* nop */
10179 else
10180 /* mov r0, rx */
10183 }
10184 else
10185 {
10186 _bfd_error_handler
10187 /* xgettext:c-format */
10193 }
10197 /* GD->IE relaxation, turn the instruction into 'nop' or
10198 'ldr r0, [pc,r0]' */
10204 /* GD->IE relaxation. */
10206 /* add r0,pc; ldr r0, [r0] */
10209 /* nop.w */
10211 else
10212 /* nop; nop */
10218 }
10220 }
10222 /* For a given value of n, calculate the value of G_n as required to
10223 deal with group relocations. We return it in the form of an
10224 encoded constant-and-rotation, together with the final residual. If n is
10225 specified as less than zero, then final_residual is filled with the
10226 input value and no further action is performed. */
10228 static bfd_vma
10230 {
10232 bfd_vma g_n;
10237 {
10240 /* Calculate which part of the value to mask. */
10243 else
10244 {
10247 /* Determine the most significant bit in the residual and
10248 align the resulting value to a 2-bit boundary. */
10253 /* The desired shift is now (msb - 6), or zero, whichever
10254 is the greater. */
10258 }
10260 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10265 /* Calculate the residual for the next time around. */
10267 }
10272 }
10274 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10275 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10277 static int
10279 {
10289 }
10291 /* Perform a relocation as part of a final link. */
10293 static bfd_reloc_status_type
10300 bfd_vma value,
10309 {
10319 bfd_vma addend;
10320 bfd_signed_vma signed_addend;
10322 bfd_vma dynreloc_value;
10327 bfd_vma plt_offset;
10328 bfd_vma gotplt_offset;
10329 bfd_boolean has_iplt_entry;
10330 bfd_boolean resolved_to_zero;
10339 /* Some relocation types map to different relocations depending on the
10340 target. We pick the right one here. */
10343 /* It is possible to have linker relaxations on some TLS access
10344 models. Update our information here. */
10357 else
10363 {
10364 bfd_vma sign;
10367 {
10372 }
10373 /* Note: the addend and signed_addend calculated here are
10374 incorrect for any split field. */
10380 }
10381 else
10384 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10385 are resolving a function call relocation. */
10392 /* Record the symbol information that should be used in dynamic
10393 relocations. */
10399 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10400 VALUE appropriately for relocations that we resolve at link time. */
10405 {
10410 {
10414 /* Populate .iplt entries here, because not all of them will
10415 be seen by finish_dynamic_symbol. The lower bit is set if
10416 we have already populated the entry. */
10418 plt_offset--;
10419 else
10420 {
10424 else
10426 }
10428 /* Static relocations always resolve to the .iplt entry. */
10435 /* If there are non-call relocations that resolve to the .iplt
10436 entry, then all dynamic ones must too. */
10438 {
10441 }
10442 }
10443 else
10444 /* We populate the .plt entry in finish_dynamic_symbol. */
10446 }
10447 else
10448 {
10452 }
10458 {
10460 /* We don't need to find a value for this symbol. It's just a
10461 marker. */
10468 /* Fall through. */
10480 /* Handle relocations which should use the PLT entry. ABS32/REL32
10481 will use the symbol's value, which may point to a PLT entry, but we
10482 don't need to handle that here. If we created a PLT entry, all
10483 branches in this object should go to it, except if the PLT is too
10484 far away, in which case a long branch stub should be inserted. */
10491 {
10492 /* If we've created a .plt section, and assigned a PLT entry
10493 to this function, it must either be a STT_GNU_IFUNC reference
10494 or not be known to bind locally. In other cases, we should
10495 have cleared the PLT entry by now. */
10505 }
10507 /* When generating a shared object or relocatable executable, these
10508 relocations are copied into the output file to be resolved at
10509 run time. */
10530 {
10531 Elf_Internal_Rela outrel;
10537 {
10543 _bfd_error_handler
10548 }
10553 {
10559 }
10584 else
10585 {
10588 /* This symbol is local, or marked to become local. */
10592 {
10595 /* On Symbian OS, the data segment and text segement
10596 can be relocated independently. Therefore, we
10597 must indicate the segment to which this
10598 relocation is relative. The BPABI allows us to
10599 use any symbol in the right segment; we just use
10600 the section symbol as it is convenient. (We
10601 cannot use the symbol given by "h" directly as it
10602 will not appear in the dynamic symbol table.)
10604 Note that the dynamic linker ignores the section
10605 symbol value, so we don't subtract osec->vma
10606 from the emitted reloc addend. */
10609 else
10615 {
10621 else
10624 }
10626 }
10627 else
10628 /* On SVR4-ish systems, the dynamic loader cannot
10629 relocate the text and data segments independently,
10630 so the symbol does not matter. */
10633 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10634 to the .iplt entry. Instead, every non-call reference
10635 must use an R_ARM_IRELATIVE relocation to obtain the
10636 correct run-time address. */
10640 else
10644 else
10646 }
10650 else
10653 /* If this reloc is against an external symbol, we do not want to
10654 fiddle with the addend. Otherwise, we need to include the symbol
10655 value so that it becomes an addend for the dynamic reloc. */
10662 }
10664 {
10673 {
10677 {
10678 /* Check for Arm calling Arm function. */
10679 /* FIXME: Should we translate the instruction into a BL
10680 instruction instead ? */
10682 _bfd_error_handler
10687 }
10689 {
10690 /* Check for Arm calling Thumb function. */
10692 {
10697 error_message))
10699 else
10701 }
10702 }
10704 /* Check if a stub has to be inserted because the
10705 destination is too far or we are changing mode. */
10709 {
10720 {
10721 /* The target is out of reach, so redirect the
10722 branch to the local stub for this function. */
10726 stub_type);
10727 {
10735 }
10736 }
10737 else
10738 {
10739 /* If the call goes through a PLT entry, make sure to
10740 check distance to the right destination address. */
10742 {
10747 /* The PLT entry is in ARM mode, regardless of the
10748 target function. */
10750 }
10751 }
10752 }
10754 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10755 where:
10756 S is the address of the symbol in the relocation.
10757 P is address of the instruction being relocated.
10758 A is the addend (extracted from the instruction) in bytes.
10760 S is held in 'value'.
10761 P is the base address of the section containing the
10762 instruction plus the offset of the reloc into that
10763 section, ie:
10764 (input_section->output_section->vma +
10765 input_section->output_offset +
10766 rel->r_offset).
10767 A is the addend, converted into bytes, ie:
10768 (signed_addend * 4)
10770 Note: None of these operations have knowledge of the pipeline
10771 size of the processor, thus it is up to the assembler to
10772 encode this information into the addend. */
10781 /* A branch to an undefined weak symbol is turned into a jump to
10782 the next instruction unless a PLT entry will be created.
10783 Do the same for local undefined symbols (but not for STN_UNDEF).
10784 The jump to the next instruction is optimized as a NOP depending
10785 on the architecture. */
10789 {
10794 else
10796 }
10797 else
10798 {
10799 /* Perform a signed range check. */
10810 {
10811 /* Set the H bit in the BLX instruction. */
10813 {
10816 else
10818 }
10820 /* Select the correct instruction (BL or BLX). */
10821 /* Only if we are not handling a BL to a stub. In this
10822 case, mode switching is performed by the stub. */
10826 {
10829 }
10830 }
10831 }
10832 }
10864 {
10865 /* Check for overflow. */
10868 }
10874 }
10882 /* There is no way to tell whether the user intended to use a signed or
10883 unsigned addend. When checking for overflow we accept either,
10884 as specified by the AAELF. */
10894 /* See comment for R_ARM_ABS8. */
10902 /* Support ldr and str instructions for the thumb. */
10904 {
10905 /* Need to refetch addend. */
10907 /* ??? Need to determine shift amount from operand size. */
10909 }
10912 /* ??? Isn't value unsigned? */
10916 /* ??? Value needs to be properly shifted into place first. */
10922 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10923 {
10924 bfd_vma insn;
10925 bfd_signed_vma relocation;
10931 {
10936 }
10943 /* PR 21523: Use an absolute value. The user of this reloc will
10944 have already selected an ADD or SUB insn appropriately. */
10950 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10964 }
10967 /* PR 10073: This reloc is not generated by the GNU toolchain,
10968 but it is supported for compatibility with third party libraries
10969 generated by other compilers, specifically the ARM/IAR. */
10970 {
10971 bfd_vma insn;
10972 bfd_signed_vma relocation;
10986 /* We do not check for overflow of this reloc. Although strictly
10987 speaking this is incorrect, it appears to be necessary in order
10988 to work with IAR generated relocs. Since GCC and GAS do not
10989 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10990 a problem for them. */
10998 }
11001 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11002 {
11003 bfd_vma insn;
11004 bfd_signed_vma relocation;
11010 {
11014 }
11034 }
11039 /* Thumb BL (branch long instruction). */
11040 {
11041 bfd_vma relocation;
11042 bfd_vma reloc_sign;
11046 bfd_signed_vma reloc_signed_max;
11047 bfd_signed_vma reloc_signed_min;
11048 bfd_vma check;
11049 bfd_signed_vma signed_check;
11054 /* A branch to an undefined weak symbol is turned into a jump to
11055 the next instruction unless a PLT entry will be created.
11056 The jump to the next instruction is optimized as a NOP.W for
11057 Thumb-2 enabled architectures. */
11060 {
11062 {
11065 }
11066 else
11067 {
11070 }
11072 }
11074 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11075 with Thumb-1) involving the J1 and J2 bits. */
11077 {
11087 /* Sign extend. */
11091 }
11094 {
11095 /* Check for Thumb to Thumb call. */
11096 /* FIXME: Should we translate the instruction into a BL
11097 instruction instead ? */
11099 _bfd_error_handler
11104 }
11105 else
11106 {
11107 /* If it is not a call to Thumb, assume call to Arm.
11108 If it is a call relative to a section name, then it is not a
11109 function call at all, but rather a long jump. Calls through
11110 the PLT do not require stubs. */
11112 {
11114 {
11115 /* Convert BL to BLX. */
11117 }
11120 {
11124 error_message))
11126 else
11128 }
11129 }
11133 {
11134 /* Make sure this is a BL. */
11136 }
11137 }
11141 {
11142 /* Check if a stub has to be inserted because the destination
11143 is too far. */
11155 {
11156 /* The target is out of reach or we are changing modes, so
11157 redirect the branch to the local stub for this
11158 function. */
11162 stub_type);
11164 {
11171 }
11173 /* If this call becomes a call to Arm, force BLX. */
11175 {
11180 }
11181 }
11182 }
11184 /* Handle calls via the PLT. */
11186 {
11194 {
11195 /* If the Thumb BLX instruction is available, convert
11196 the BL to a BLX instruction to call the ARM-mode
11197 PLT entry. */
11200 }
11201 else
11202 {
11204 /* Target the Thumb stub before the ARM PLT entry. */
11207 }
11209 }
11219 /* If this is a signed value, the rightshift just dropped
11220 leading 1 bits (assuming twos complement). */
11223 else
11226 /* Calculate the permissable maximum and minimum values for
11227 this relocation according to whether we're relocating for
11228 Thumb-2 or not. */
11235 /* Assumes two's complement. */
11240 /* For a BLX instruction, make sure that the relocation is rounded up
11241 to a word boundary. This follows the semantics of the instruction
11242 which specifies that bit 1 of the target address will come from bit
11243 1 of the base address. */
11246 /* Put RELOCATION back into the insn. Assumes two's complement.
11247 We use the Thumb-2 encoding, which is safe even if dealing with
11248 a Thumb-1 instruction by virtue of our overflow check above. */
11258 /* Put the relocated value back in the object file: */
11263 }
11267 /* Thumb32 conditional branch instruction. */
11268 {
11269 bfd_vma relocation;
11275 bfd_signed_vma signed_check;
11280 /* Need to refetch the addend, reconstruct the top three bits,
11281 and squish the two 11 bit pieces together. */
11283 {
11297 }
11299 /* Handle calls via the PLT. */
11301 {
11305 /* Target the Thumb stub before the ARM PLT entry. */
11308 }
11317 {
11321 stub_type);
11323 {
11327 }
11328 }
11339 /* Put RELOCATION back into the insn. */
11340 {
11349 }
11351 /* Put the relocated value back in the object file: */
11356 }
11361 /* Thumb B (branch) instruction). */
11362 {
11363 bfd_signed_vma relocation;
11366 bfd_signed_vma signed_check;
11368 /* CZB cannot jump backward. */
11370 {
11374 }
11387 else
11393 /* Assumes two's complement. */
11398 }
11403 {
11404 bfd_vma insn;
11405 bfd_vma relocation;
11409 {
11410 /* Extract the addend. */
11413 }
11423 }
11431 /* Relocation is relative to the start of the
11432 global offset table. */
11438 /* If we are addressing a Thumb function, we need to adjust the
11439 address by one, so that attempts to call the function pointer will
11440 correctly interpret it as Thumb code. */
11444 /* Note that sgot->output_offset is not involved in this
11445 calculation. We always want the start of .got. If we
11446 define _GLOBAL_OFFSET_TABLE in a different way, as is
11447 permitted by the ABI, we might have to change this
11448 calculation. */
11455 /* Use global offset table as symbol value. */
11469 /* Relocation is to the entry for this symbol in the
11470 global offset table. */
11477 {
11478 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11479 symbol, and the relocation resolves directly to the runtime
11480 target rather than to the .iplt entry. This means that any
11481 .got entry would be the same value as the .igot.plt entry,
11482 so there's no point creating both. */
11485 }
11487 {
11488 bfd_vma off;
11493 {
11494 /* We have already processsed one GOT relocation against
11495 this symbol. */
11500 }
11501 else
11502 {
11503 Elf_Internal_Rela outrel;
11508 {
11509 /* If the symbol doesn't resolve locally in a static
11510 object, we have an undefined reference. If the
11511 symbol doesn't resolve locally in a dynamic object,
11512 it should be resolved by the dynamic linker. */
11514 {
11517 }
11518 else
11521 }
11522 else
11523 {
11529 else
11530 {
11534 }
11536 }
11538 /* The GOT entry is initialized to zero by default.
11539 See if we should install a different value. */
11542 {
11546 }
11555 {
11560 }
11563 }
11565 }
11566 else
11567 {
11568 bfd_vma off;
11575 /* The offset must always be a multiple of 4. We use the
11576 least significant bit to record whether we have already
11577 generated the necessary reloc. */
11580 else
11581 {
11582 Elf_Internal_Rela outrel;
11589 else
11590 {
11594 }
11596 /* The GOT entry is initialized to zero by default.
11597 See if we should install a different value. */
11608 {
11614 }
11617 }
11620 }
11637 {
11638 bfd_vma off;
11647 else
11648 {
11649 /* If we don't know the module number, create a relocation
11650 for it. */
11652 {
11653 Elf_Internal_Rela outrel;
11668 }
11669 else
11673 }
11676 {
11682 }
11683 else
11684 {
11692 }
11693 }
11704 {
11712 {
11713 bfd_boolean dyn;
11717 h)
11720 {
11723 }
11727 }
11728 else
11729 {
11734 }
11736 /* Linker relaxations happens from one of the
11737 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11745 else
11746 {
11748 Elf_Internal_Rela outrel;
11751 /* The GOT entries have not been initialized yet. Do it
11752 now, and emit any relocations. If both an IE GOT and a
11753 GD GOT are necessary, we emit the GD first. */
11760 {
11763 }
11766 {
11769 /* We should have relaxed, unless this is an undefined
11770 weak symbol. */
11779 + offplt
11791 /* For globals, the first word in the relocation gets
11792 the relocation index and the top bit set, or zero,
11793 if we're binding now. For locals, it gets the
11794 symbol's offset in the tls section. */
11802 /* Second word in the relocation is always zero. */
11806 }
11808 {
11810 {
11826 else
11827 {
11830 R_ARM_TLS_DTPOFF32);
11839 }
11840 }
11841 else
11842 {
11843 /* If we are not emitting relocations for a
11844 general dynamic reference, then we must be in a
11845 static link or an executable link with the
11846 symbol binding locally. Mark it as belonging
11847 to module 1, the executable. */
11852 }
11855 }
11858 {
11860 {
11863 else
11875 }
11876 else
11880 }
11884 else
11886 }
11895 {
11896 bfd_signed_vma offset;
11897 /* TLS stubs are arm mode. The original symbol is a
11898 data object, so branch_type is bogus. */
11900 enum elf32_arm_stub_type stub_type
11908 {
11910 = elf32_arm_get_stub_entry
11916 }
11917 else
11923 {
11933 }
11934 else
11935 {
11936 /* Thumb blx encodes the offset in a complicated
11937 fashion. */
11947 {
11949 }
11950 else
11951 {
11953 /* Round up the offset to a word boundary. */
11955 }
11967 }
11968 }
11969 /* These relocations needs special care, as besides the fact
11970 they point somewhere in .gotplt, the addend must be
11971 adjusted accordingly depending on the type of instruction
11972 we refer to. */
11974 {
11983 {
11990 /* bl/blx */
11993 /* add */
11995 else
11996 {
11997 _bfd_error_handler
11998 /* xgettext:c-format */
12000 "unexpected %s instruction '%#lx' "
12005 }
12006 }
12007 else
12008 {
12012 {
12023 _bfd_error_handler
12024 /* xgettext:c-format */
12026 "unexpected %s instruction '%#lx' "
12031 }
12032 }
12040 }
12041 else
12049 {
12050 /* For FDPIC relocations, resolve to the offset of the GOT
12051 entry from the start of GOT. */
12057 }
12058 else
12059 {
12063 }
12064 }
12068 {
12069 _bfd_error_handler
12070 /* xgettext:c-format */
12075 }
12076 else
12085 {
12088 /* Ensure that we have a BX instruction. */
12092 {
12093 /* Branch to veneer. */
12094 bfd_vma glue_addr;
12101 }
12102 else
12103 {
12104 /* Preserve Rm (lowest four bits) and the condition code
12105 (highest four bits). Other bits encode MOV PC,Rm. */
12107 }
12110 }
12117 /* Until we properly support segment-base-relative addressing then
12118 we assume the segment base to be zero, as for the group relocations.
12119 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12120 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12124 {
12128 {
12131 }
12153 }
12160 /* Until we properly support segment-base-relative addressing then
12161 we assume the segment base to be zero, as for the above relocations.
12162 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12163 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12164 as R_ARM_THM_MOVT_ABS. */
12168 {
12169 bfd_vma insn;
12175 {
12181 }
12207 }
12220 {
12224 /* sb is the origin of the *segment* containing the symbol. */
12226 bfd_vma residual;
12227 bfd_vma g_n;
12228 bfd_signed_vma signed_value;
12231 /* Determine which group of bits to select. */
12233 {
12255 }
12257 /* If REL, extract the addend from the insn. If RELA, it will
12258 have already been fetched for us. */
12260 {
12267 else
12268 {
12269 /* Compensate for the fact that in the instruction, the
12270 rotation is stored in multiples of 2 bits. */
12273 /* Rotate "constant" right by "rotation" bits. */
12276 }
12278 /* Determine if the instruction is an ADD or a SUB.
12279 (For REL, this determines the sign of the addend.) */
12282 {
12283 _bfd_error_handler
12284 /* xgettext:c-format */
12289 }
12292 }
12294 /* Compute the value (X) to go in the place. */
12300 /* PC relative. */
12302 else
12303 /* Section base relative. */
12306 /* If the target symbol is a Thumb function, then set the
12307 Thumb bit in the address. */
12311 /* Calculate the value of the relevant G_n, in encoded
12312 constant-with-rotation format. */
12316 /* Check for overflow if required. */
12323 {
12324 _bfd_error_handler
12325 /* xgettext:c-format */
12332 }
12334 /* Mask out the value and the ADD/SUB part of the opcode; take care
12335 not to destroy the S bit. */
12338 /* Set the opcode according to whether the value to go in the
12339 place is negative. */
12342 else
12345 /* Encode the offset. */
12349 }
12358 {
12362 /* sb is the origin of the *segment* containing the symbol. */
12364 bfd_vma residual;
12365 bfd_signed_vma signed_value;
12368 /* Determine which groups of bits to calculate. */
12370 {
12388 }
12390 /* If REL, extract the addend from the insn. If RELA, it will
12391 have already been fetched for us. */
12393 {
12396 }
12398 /* Compute the value (X) to go in the place. */
12402 /* PC relative. */
12404 else
12405 /* Section base relative. */
12408 /* Calculate the value of the relevant G_{n-1} to obtain
12409 the residual at that stage. */
12413 /* Check for overflow. */
12415 {
12416 _bfd_error_handler
12417 /* xgettext:c-format */
12424 }
12426 /* Mask out the value and U bit. */
12429 /* Set the U bit if the value to go in the place is non-negative. */
12433 /* Encode the offset. */
12437 }
12446 {
12450 /* sb is the origin of the *segment* containing the symbol. */
12452 bfd_vma residual;
12453 bfd_signed_vma signed_value;
12456 /* Determine which groups of bits to calculate. */
12458 {
12476 }
12478 /* If REL, extract the addend from the insn. If RELA, it will
12479 have already been fetched for us. */
12481 {
12484 }
12486 /* Compute the value (X) to go in the place. */
12490 /* PC relative. */
12492 else
12493 /* Section base relative. */
12496 /* Calculate the value of the relevant G_{n-1} to obtain
12497 the residual at that stage. */
12501 /* Check for overflow. */
12503 {
12504 _bfd_error_handler
12505 /* xgettext:c-format */
12512 }
12514 /* Mask out the value and U bit. */
12517 /* Set the U bit if the value to go in the place is non-negative. */
12521 /* Encode the offset. */
12525 }
12534 {
12538 /* sb is the origin of the *segment* containing the symbol. */
12540 bfd_vma residual;
12541 bfd_signed_vma signed_value;
12544 /* Determine which groups of bits to calculate. */
12546 {
12564 }
12566 /* If REL, extract the addend from the insn. If RELA, it will
12567 have already been fetched for us. */
12569 {
12572 }
12574 /* Compute the value (X) to go in the place. */
12578 /* PC relative. */
12580 else
12581 /* Section base relative. */
12584 /* Calculate the value of the relevant G_{n-1} to obtain
12585 the residual at that stage. */
12589 /* Check for overflow. (The absolute value to go in the place must be
12590 divisible by four and, after having been divided by four, must
12591 fit in eight bits.) */
12593 {
12594 _bfd_error_handler
12595 /* xgettext:c-format */
12602 }
12604 /* Mask out the value and U bit. */
12607 /* Set the U bit if the value to go in the place is non-negative. */
12611 /* Encode the offset. */
12615 }
12622 {
12628 /* Compute address. */
12634 /* Clean imm8 insn. */
12636 /* And update with correct part of address. */
12638 /* Update insn. */
12640 }
12646 {
12648 {
12658 /* Resolve relocation. */
12661 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12662 not done yet. */
12666 }
12667 else
12668 {
12671 bfd_vma addr;
12674 /* For static binaries, sym_sec can be null. */
12676 {
12679 }
12680 else
12681 {
12684 }
12689 /* This case cannot occur since funcdesc is allocated by
12690 the dynamic loader so we cannot resolve the relocation. */
12694 /* Resolve relocation. */
12697 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12701 }
12702 }
12707 {
12709 {
12710 Elf_Internal_Rela outrel;
12712 /* Resolve relocation. */
12716 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12718 {
12721 bfd_vma addr;
12724 /* For static binaries sym_sec can be null. */
12726 {
12729 }
12730 else
12731 {
12734 }
12736 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12740 }
12742 /* Add a dynamic relocation on GOT entry if not already done. */
12744 {
12746 {
12751 else
12755 sgot->contents
12757 }
12758 else
12759 {
12761 }
12769 else
12772 else
12775 }
12776 }
12777 else
12778 {
12779 /* Such relocation on static function should not have been
12780 emitted by the compiler. */
12782 }
12783 }
12788 {
12790 {
12792 Elf_Internal_Rela outrel;
12801 /* Replace static FUNCDESC relocation with a
12802 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12803 executable. */
12810 else
12816 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12820 }
12821 else
12822 {
12824 {
12827 bfd_vma addr;
12829 Elf_Internal_Rela outrel;
12831 /* For static binaries sym_sec can be null. */
12833 {
12836 }
12837 else
12838 {
12841 }
12846 /* Replace static FUNCDESC relocation with a
12847 R_ARM_RELATIVE dynamic relocation. */
12854 else
12860 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12864 }
12865 else
12866 {
12867 Elf_Internal_Rela outrel;
12869 /* Add a dynamic relocation. */
12875 }
12876 }
12877 }
12882 {
12883 bfd_vma relocation;
12888 {
12896 /* Sign extend. */
12898 }
12905 /* Put RELOCATION back into the insn. */
12906 {
12913 }
12915 /* Put the relocated value back in the object file: */
12920 }
12923 {
12924 bfd_vma relocation;
12929 {
12937 /* Sign extend. */
12940 }
12947 /* Put RELOCATION back into the insn. */
12948 {
12955 }
12957 /* Put the relocated value back in the object file: */
12962 }
12965 {
12966 bfd_vma relocation;
12971 {
12979 /* Sign extend. */
12982 }
12989 /* Put RELOCATION back into the insn. */
12990 {
12997 }
12999 /* Put the relocated value back in the object file: */
13004 }
13008 }
13009 }
13011 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13012 static void
13016 bfd_signed_vma increment)
13017 {
13018 bfd_signed_vma addend;
13022 {
13040 }
13041 else
13042 {
13043 bfd_vma contents;
13047 /* Get the (signed) value from the instruction. */
13050 {
13051 bfd_signed_vma mask;
13056 }
13058 /* Add in the increment, (which is a byte value). */
13060 {
13072 /* Should we check for overflow here ? */
13074 /* Drop any undesired bits. */
13077 }
13082 }
13083 }
13085 #define IS_ARM_TLS_RELOC(R_TYPE) \
13086 ((R_TYPE) == R_ARM_TLS_GD32 \
13087 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
13088 || (R_TYPE) == R_ARM_TLS_LDO32 \
13089 || (R_TYPE) == R_ARM_TLS_LDM32 \
13090 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
13091 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13092 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13093 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13094 || (R_TYPE) == R_ARM_TLS_LE32 \
13095 || (R_TYPE) == R_ARM_TLS_IE32 \
13096 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
13097 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13099 /* Specific set of relocations for the gnu tls dialect. */
13100 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13101 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13102 || (R_TYPE) == R_ARM_TLS_CALL \
13103 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13104 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13105 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
13107 /* Relocate an ARM ELF section. */
13109 static bfd_boolean
13118 {
13136 {
13143 bfd_vma relocation;
13144 bfd_reloc_status_type r;
13145 arelent bfd_reloc;
13168 {
13173 /* An object file might have a reference to a local
13174 undefined symbol. This is a daft object file, but we
13175 should at least do something about it. V4BX & NONE
13176 relocations do not use the symbol and are explicitly
13177 allowed to use the undefined symbol, so allow those.
13178 Likewise for relocations against STN_UNDEF. */
13191 {
13198 {
13203 {
13225 {
13226 _bfd_error_handler
13227 /* xgettext:c-format */
13233 }
13237 /* Get the (signed) value from the instruction. */
13240 {
13241 bfd_signed_vma mask;
13246 }
13248 }
13251 addend =
13256 /* Cases here must match those in the preceding
13257 switch statement. */
13259 {
13282 }
13283 }
13284 }
13285 else
13287 }
13288 else
13289 {
13298 }
13305 {
13306 /* This is a relocatable link. We don't have to change
13307 anything, unless the reloc is against a section symbol,
13308 in which case we have to adjust according to where the
13309 section symbol winds up in the output section. */
13311 {
13315 else
13317 }
13319 }
13323 else
13324 {
13325 name = (bfd_elf_string_from_elf_section
13329 }
13337 {
13338 _bfd_error_handler
13340 /* xgettext:c-format */
13342 /* xgettext:c-format */
13344 input_bfd,
13345 input_section,
13348 name);
13349 }
13351 /* We call elf32_arm_final_link_relocate unless we're completely
13352 done, i.e., the relaxation produced the final output we want,
13353 and we won't let anybody mess with it. Also, we have to do
13354 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13355 both in relaxed and non-relaxed cases. */
13361 {
13364 /* This may have been marked unresolved because it came from
13365 a shared library. But we've just dealt with that. */
13367 }
13368 else
13372 {
13383 }
13385 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13386 because such sections are not SEC_ALLOC and thus ld.so will
13387 not process them. */
13393 {
13394 _bfd_error_handler
13395 /* xgettext:c-format */
13398 input_bfd,
13399 input_section,
13404 }
13407 {
13409 {
13411 /* If the overflowing reloc was to an undefined symbol,
13412 we have already printed one error message and there
13413 is no point complaining again. */
13434 /* error_message should already be set. */
13439 /* Fall through. */
13441 common_error:
13446 }
13447 }
13448 }
13451 }
13453 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13454 adds the edit to the start of the list. (The list must be built in order of
13455 ascending TINDEX: the function's callers are primarily responsible for
13456 maintaining that condition). */
13458 static void
13461 arm_unwind_edit_type type,
13464 {
13473 {
13483 }
13484 else
13485 {
13492 }
13493 }
13497 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13498 static void
13500 {
13508 /* Adjust size of output section. */
13510 }
13512 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13513 static void
13515 {
13527 }
13529 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13530 made to those tables, such that:
13532 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13533 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13534 codes which have been inlined into the index).
13536 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13538 The edits are applied when the tables are written
13539 (in elf32_arm_write_section). */
13541 bfd_boolean
13545 bfd_boolean merge_exidx_entries)
13546 {
13553 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13554 text sections. */
13556 {
13560 {
13568 {
13569 Elf_Internal_Shdr *linked_hdr
13577 /* Link this .ARM.exidx section back from the text section it
13578 describes. */
13580 }
13581 }
13582 }
13584 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13585 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13586 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13589 {
13596 bfd_vma j;
13607 {
13608 /* Section has no unwind data. */
13612 /* Ignore zero sized sections. */
13619 }
13621 /* Skip /DISCARD/ sections. */
13638 /* An error? */
13642 {
13644 /* Add cantunwind if first unwind item does not match section
13645 start. */
13647 {
13650 }
13651 }
13654 {
13659 /* An EXIDX_CANTUNWIND entry. */
13661 {
13665 }
13666 /* Inlined unwinding data. Merge if equal to previous. */
13668 {
13674 }
13675 /* Normal table entry. In theory we could merge these too,
13676 but duplicate entries are likely to be much less common. */
13677 else
13681 {
13686 }
13689 }
13691 /* Free contents if we allocated it ourselves. */
13695 /* Record edits to be applied later (in elf32_arm_write_section). */
13704 }
13706 /* Add terminating CANTUNWIND entry. */
13712 }
13714 static bfd_boolean
13717 {
13733 }
13735 static bfd_boolean
13737 {
13744 /* Invoke the regular ELF backend linker to do all the work. */
13748 /* Process stub sections (eg BE8 encoding, ...). */
13752 {
13754 /* Only process it once, in its link_sec slot. */
13756 {
13762 }
13763 }
13765 /* Write out any glue sections now that we have created all the
13766 stubs. */
13768 {
13771 ARM2THUMB_GLUE_SECTION_NAME))
13776 THUMB2ARM_GLUE_SECTION_NAME))
13781 VFP11_ERRATUM_VENEER_SECTION_NAME))
13786 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13791 ARM_BX_GLUE_SECTION_NAME))
13793 }
13796 }
13798 /* Return a best guess for the machine number based on the attributes. */
13800 static unsigned int
13802 {
13806 {
13813 {
13820 {
13828 {
13834 {
13838 }
13839 }
13840 }
13843 }
13875 /* Force entry to be added for any new known Tag_CPU_arch value. */
13878 /* Unknown Tag_CPU_arch value. */
13880 }
13881 }
13883 /* Set the right machine number. */
13885 static bfd_boolean
13887 {
13893 {
13896 else
13898 }
13902 }
13904 /* Function to keep ARM specific flags in the ELF header. */
13906 static bfd_boolean
13908 {
13911 {
13913 {
13915 _bfd_error_handler
13916 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
13917 abfd);
13918 else
13919 _bfd_error_handler
13921 abfd);
13922 }
13923 }
13924 else
13925 {
13928 }
13931 }
13933 /* Copy backend specific data from one object module to another. */
13935 static bfd_boolean
13937 {
13938 flagword in_flags;
13939 flagword out_flags;
13950 {
13951 /* Cannot mix APCS26 and APCS32 code. */
13955 /* Cannot mix float APCS and non-float APCS code. */
13959 /* If the src and dest have different interworking flags
13960 then turn off the interworking bit. */
13962 {
13964 _bfd_error_handler
13965 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
13969 }
13971 /* Likewise for PIC, though don't warn for this case. */
13974 }
13980 }
13982 /* Values for Tag_ABI_PCS_R9_use. */
13983 enum
13984 {
13985 AEABI_R9_V6,
13986 AEABI_R9_SB,
13987 AEABI_R9_TLS,
13988 AEABI_R9_unused
13989 };
13991 /* Values for Tag_ABI_PCS_RW_data. */
13992 enum
13993 {
13994 AEABI_PCS_RW_data_absolute,
13995 AEABI_PCS_RW_data_PCrel,
13996 AEABI_PCS_RW_data_SBrel,
13997 AEABI_PCS_RW_data_unused
13998 };
14000 /* Values for Tag_ABI_enum_size. */
14001 enum
14002 {
14003 AEABI_enum_unused,
14004 AEABI_enum_short,
14005 AEABI_enum_wide,
14006 AEABI_enum_forced_wide
14007 };
14009 /* Determine whether an object attribute tag takes an integer, a
14010 string or both. */
14012 static int
14014 {
14023 else
14025 }
14027 /* The ABI defines that Tag_conformance should be emitted first, and that
14028 Tag_nodefaults should be second (if either is defined). This sets those
14029 two positions, and bumps up the position of all the remaining tags to
14030 compensate. */
14031 static int
14033 {
14043 }
14045 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
14046 static bfd_boolean
14048 {
14050 {
14051 _bfd_error_handler
14056 }
14057 else
14058 {
14059 _bfd_error_handler
14063 }
14064 }
14066 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
14067 Returns -1 if no architecture could be read. */
14069 static int
14071 {
14075 /* Note: the tag and its argument below are uleb128 values, though
14076 currently-defined values fit in one byte for each. */
14083 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14085 }
14087 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14088 The tag is removed if ARCH is -1. */
14090 static void
14092 {
14097 {
14100 }
14102 /* Note: the tag and its argument below are uleb128 values, though
14103 currently-defined values fit in one byte for each. */
14109 }
14111 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14112 into account. */
14114 static int
14117 {
14118 #define T(X) TAG_CPU_ARCH_##X
14121 {
14131 };
14133 {
14144 };
14146 {
14158 };
14160 {
14173 };
14175 {
14189 };
14191 {
14206 };
14208 {
14224 };
14226 {
14243 };
14245 {
14263 };
14265 {
14284 };
14286 {
14309 };
14311 {
14335 };
14337 {
14338 v6t2,
14339 v6k,
14340 v7,
14341 v6_m,
14342 v6s_m,
14343 v7e_m,
14344 v8,
14345 v8r,
14346 v8m_baseline,
14347 v8m_mainline,
14348 NULL,
14349 NULL,
14350 NULL,
14351 v8_1m_mainline,
14352 /* Pseudo-architecture. */
14353 v4t_plus_v6_m
14354 };
14356 /* Check we've not got a higher architecture than we know about. */
14359 {
14362 }
14364 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14370 /* And override the new tag if we have a Tag_also_compatible_with on the
14371 input. */
14380 /* Architectures before V6KZ add features monotonically. */
14386 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14387 as the canonical version. */
14389 {
14392 }
14393 else
14397 {
14401 }
14404 #undef T
14405 }
14407 /* Query attributes object to see if integer divide instructions may be
14408 present in an object. */
14409 static bfd_boolean
14411 {
14416 {
14418 /* Integer divide allowed if instruction contained in archetecture. */
14423 else
14427 /* Integer divide explicitly prohibited. */
14431 /* Unrecognised case - treat as allowing divide everywhere. */
14433 /* Integer divide allowed in ARM state. */
14435 }
14436 }
14438 /* Query attributes object to see if integer divide instructions are
14439 forbidden to be in the object. This is not the inverse of
14440 elf32_arm_attributes_accept_div. */
14441 static bfd_boolean
14443 {
14445 }
14447 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14448 are conflicting attributes. */
14450 static bfd_boolean
14452 {
14456 /* Some tags have 0 = don't care, 1 = strong requirement,
14457 2 = weak requirement. */
14463 /* Skip the linker stubs file. This preserves previous behavior
14464 of accepting unknown attributes in the first input file - but
14465 is that a bug? */
14469 /* Skip any input that hasn't attribute section.
14470 This enables to link object files without attribute section with
14471 any others. */
14476 {
14477 /* This is the first object. Copy the attributes. */
14482 /* Use the Tag_null value to indicate the attributes have been
14483 initialized. */
14486 /* We do not output objects with Tag_MPextension_use_legacy - we move
14487 the attribute's value to Tag_MPextension_use. */
14489 {
14493 {
14494 _bfd_error_handler
14498 }
14504 }
14507 }
14511 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14513 {
14514 /* Ignore mismatches if the object doesn't use floating point or is
14515 floating point ABI independent. */
14522 {
14523 _bfd_error_handler
14528 }
14529 }
14532 {
14533 /* Merge this attribute with existing attributes. */
14535 {
14538 /* These are merged after Tag_CPU_arch. */
14543 /* Use the first value seen. */
14547 {
14552 {
14553 /* These aren't real CPU names, but we can't guess
14554 that from the architecture version alone. */
14572 };
14574 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14580 secondary_compat);
14582 /* Return with error if failed to merge. */
14590 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14594 {
14595 /* The output architecture has been changed to match the
14596 input architecture. Use the input names. */
14603 }
14604 else
14605 {
14608 }
14610 /* If we still don't have a value for Tag_CPU_name,
14611 make one up now. Tag_CPU_raw_name remains blank. */
14616 }
14623 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14633 /* Use the largest value specified. */
14640 /* Use the smallest value specified. */
14649 {
14650 /* This error message should be enabled once all non-conformant
14651 binaries in the toolchain have had the attributes set
14652 properly.
14653 _bfd_error_handler
14654 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14655 obfd, ibfd);
14656 result = FALSE; */
14657 }
14658 /* Fall through. */
14661 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14662 value if greater than 2 (for future-proofing). */
14670 /* The virtualization tag effectively stores two bits of
14671 information: the intended use of TrustZone (in bit 0), and the
14672 intended use of Virtualization (in bit 1). */
14677 {
14680 else
14681 {
14682 _bfd_error_handler
14687 }
14688 }
14693 {
14694 /* 0 will merge with anything.
14695 'A' and 'S' merge to 'A'.
14696 'R' and 'S' merge to 'R'.
14697 'M' and 'A|R|S' is an error. */
14706 else
14707 {
14708 _bfd_error_handler
14710 ibfd,
14714 }
14715 }
14719 /* No need to change output value if any of:
14720 - pre (<=) ARMv5T input architecture (do not have DSP)
14721 - M input profile not ARMv7E-M and do not have DSP. */
14727 /* Output value should be 0 if DSP part of architecture, ie.
14728 - post (>=) ARMv5te architecture output
14729 - A, R or S profile output or ARMv7E-M output architecture. */
14736 /* Otherwise, DSP instructions are added and not part of output
14737 architecture. */
14738 else
14743 {
14744 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14745 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14746 when it's 0. It might mean absence of FP hardware if
14747 Tag_FP_arch is zero. */
14749 #define VFP_VERSION_COUNT 9
14750 static const struct
14751 {
14755 {
14765 };
14770 /* If the output has no requirement about FP hardware,
14771 follow the requirement of the input. */
14773 {
14774 /* This assert is still reasonable, we shouldn't
14775 produce the suspicious build attribute
14776 combination (See below for in_attr). */
14782 }
14783 /* If the input has no requirement about FP hardware, do
14784 nothing. */
14786 {
14787 /* We used to assert that Tag_ABI_HardFP_use was
14788 zero here, but we should never assert when
14789 consuming an object file that has suspicious
14790 build attributes. The single precision variant
14791 of 'no FP architecture' is still 'no FP
14792 architecture', so we just ignore the tag in this
14793 case. */
14795 }
14797 /* Both the input and the output have nonzero Tag_FP_arch.
14798 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14800 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14801 do nothing. */
14804 ;
14805 /* If the input and the output have different Tag_ABI_HardFP_use,
14806 the combination of them is 0 (implied by Tag_FP_arch). */
14811 /* Now we can handle Tag_FP_arch. */
14813 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14814 pick the biggest. */
14817 {
14820 }
14821 /* The output uses the superset of input features
14822 (ISA version) and registers. */
14829 /* This assumes all possible supersets are also a valid
14830 options. */
14832 {
14836 }
14838 }
14844 {
14845 /* It's sometimes ok to mix different configs, so this is only
14846 a warning. */
14847 _bfd_error_handler
14849 }
14855 {
14856 _bfd_error_handler
14859 }
14867 {
14868 _bfd_error_handler
14870 ibfd);
14872 }
14873 /* Use the smallest value specified. */
14880 {
14881 _bfd_error_handler
14882 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
14884 }
14890 {
14893 {
14894 /* The existing object is compatible with anything.
14895 Use whatever requirements the new object has. */
14897 }
14901 {
14912 _bfd_error_handler
14913 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
14915 }
14916 }
14919 /* Aready done. */
14923 {
14924 _bfd_error_handler
14928 }
14931 /* Merged in target-independent code. */
14934 /* This is handled along with Tag_FP_arch. */
14938 {
14940 {
14941 _bfd_error_handler
14945 }
14946 }
14952 /* A value of zero on input means that the divide instruction may
14953 be used if available in the base architecture as specified via
14954 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14955 the user did not want divide instructions. A value of 2
14956 explicitly means that divide instructions were allowed in ARM
14957 and Thumb state. */
14971 /* We don't output objects with Tag_MPextension_use_legacy - we
14972 move the value to Tag_MPextension_use. */
14974 {
14976 {
14977 _bfd_error_handler
14980 ibfd);
14982 }
14983 }
14991 /* This tag is set if it exists, but the value is unused (and is
14992 typically zero). We don't actually need to do anything here -
14993 the merge happens automatically when the type flags are merged
14994 below. */
14997 /* Already done in Tag_CPU_arch. */
15000 /* Keep the attribute if it matches. Throw it away otherwise.
15001 No attribute means no claim to conform. */
15008 result
15010 }
15012 /* If out_attr was copied from in_attr then it won't have a type yet. */
15015 }
15017 /* Merge Tag_compatibility attributes and any common GNU ones. */
15021 /* Check for any attributes not known on ARM. */
15025 }
15028 /* Return TRUE if the two EABI versions are incompatible. */
15030 static bfd_boolean
15032 {
15033 /* v4 and v5 are the same spec before and after it was released,
15034 so allow mixing them. */
15040 }
15042 /* Merge backend specific data from an object file to the output
15043 object file when linking. */
15045 static bfd_boolean
15048 /* Display the flags field. */
15050 static bfd_boolean
15052 {
15058 /* Print normal ELF private data. */
15062 /* Ignore init flag - it may not be set, despite the flags field
15063 containing valid data. */
15068 {
15070 /* The following flag bits are GNU extensions and not part of the
15071 official ARM ELF extended ABI. Hence they are only decoded if
15072 the EABI version is not set. */
15078 else
15085 else
15114 else
15125 else
15157 eabi:
15170 }
15191 }
15193 static int
15195 {
15197 {
15202 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15203 This allows us to distinguish between data used by Thumb instructions
15204 and non-data (which is probably code) inside Thumb regions of an
15205 executable. */
15212 }
15215 }
15223 {
15226 {
15230 }
15233 }
15235 /* Look through the relocs for a section during the first phase. */
15237 static bfd_boolean
15240 {
15248 bfd_boolean call_reloc_p;
15249 bfd_boolean may_become_dynamic_p;
15250 bfd_boolean may_need_local_target_p;
15264 /* Create dynamic sections for relocatable executables so that we can
15265 copy relocations. */
15268 {
15271 }
15286 {
15298 /* PR 9934: It is possible to have relocations that do not
15299 refer to symbols, thus it is also possible to have an
15300 object file containing relocations but no symbol table. */
15302 {
15304 r_symndx);
15306 }
15311 {
15313 {
15314 /* A local symbol. */
15319 }
15320 else
15321 {
15326 }
15327 }
15335 /* Could be done earlier, if h were already available. */
15338 {
15340 {
15342 {
15347 }
15348 else
15349 {
15351 }
15352 }
15356 {
15358 {
15359 /* Such a relocation is not supposed to be generated
15360 by gcc on a static function. */
15361 /* Anyway if needed it could be handled. */
15363 }
15364 else
15365 {
15367 }
15368 }
15372 {
15374 {
15379 }
15380 else
15381 {
15383 }
15384 }
15398 /* This symbol requires a global offset table entry. */
15399 {
15403 {
15416 }
15422 {
15425 }
15426 else
15427 {
15428 /* This is a global offset table entry for a local symbol. */
15433 }
15435 /* If a variable is accessed with both tls methods, two
15436 slots may be created. */
15441 /* We will already have issued an error message if there
15442 is a TLS/non-TLS mismatch, based on the symbol
15443 type. So just combine any TLS types needed. */
15448 /* If the symbol is accessed in both IE and GDESC
15449 method, we're able to relax. Turn off the GDESC flag,
15450 without messing up with any other kind of tls types
15451 that may be involved. */
15456 {
15459 else
15461 }
15462 }
15463 /* Fall through. */
15469 /* Fall through. */
15491 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15492 ldr __GOTT_INDEX__ offsets. */
15494 {
15497 }
15500 /* Fall through. */
15507 {
15508 _bfd_error_handler
15509 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15514 }
15516 /* Fall through. */
15519 jump_over:
15521 {
15523 }
15524 /* Fall through. */
15532 /* Should the interworking branches be listed here? */
15536 {
15539 {
15540 /* In shared libraries and relocatable executables,
15541 we treat local relative references as calls;
15542 see the related SYMBOL_CALLS_LOCAL code in
15543 allocate_dynrelocs. */
15546 }
15547 else
15548 /* We are creating a shared library or relocatable
15549 executable, and this is a reloc against a global symbol,
15550 or a non-PC-relative reloc against a local symbol.
15551 We may need to copy the reloc into the output. */
15553 }
15554 else
15558 /* This relocation describes the C++ object vtable hierarchy.
15559 Reconstruct it for later use during GC. */
15565 /* This relocation describes which C++ vtable entries are actually
15566 used. Record for later use during GC. */
15571 }
15574 {
15576 /* We may need a .plt entry if the function this reloc
15577 refers to is in a different object, regardless of the
15578 symbol's type. We can't tell for sure yet, because
15579 something later might force the symbol local. */
15582 /* If this reloc is in a read-only section, we might
15583 need a copy reloc. We can't check reliably at this
15584 stage whether the section is read-only, as input
15585 sections have not yet been mapped to output sections.
15586 Tentatively set the flag for now, and correct in
15587 adjust_dynamic_symbol. */
15589 }
15593 {
15599 {
15602 }
15603 else
15604 {
15610 }
15612 /* If the symbol is a function that doesn't bind locally,
15613 this relocation will need a PLT entry. */
15620 /* It's too early to use htab->use_blx here, so we have to
15621 record possible blx references separately from
15622 relocs that definitely need a thumb stub. */
15630 }
15633 {
15636 /* Create a reloc section in dynobj. */
15638 {
15639 sreloc = _bfd_elf_make_dynamic_reloc_section
15645 /* BPABI objects never have dynamic relocations mapped. */
15647 {
15648 flagword flags;
15653 }
15654 }
15656 /* If this is a global symbol, count the number of
15657 relocations we need for this symbol. */
15660 else
15661 {
15665 }
15669 {
15680 }
15687 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15688 that will become rofixup. */
15689 /* This is due to the fact that we suppose all will become rofixup. */
15690 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15691 _bfd_error_handler
15696 }
15697 }
15698 }
15701 }
15703 static void
15706 {
15728 {
15731 }
15733 {
15736 }
15737 else
15749 {
15752 {
15755 irela++;
15756 count++;
15757 }
15759 {
15763 bfd_size_type j;
15764 bfd_vma offset;
15780 else
15784 {
15786 {
15788 bfd_vma bias;
15789 bfd_vma reloc_index;
15799 {
15800 bias++;
15802 }
15806 {
15808 irela++;
15809 count++;
15810 }
15813 }
15816 {
15817 /* New relocation entity. */
15826 irela++;
15827 count++;
15828 }
15829 }
15830 else
15831 {
15833 {
15836 irela++;
15837 }
15840 }
15841 }
15842 }
15850 {
15853 irela++;
15854 count--;
15855 }
15859 /* Hashes are no longer valid. */
15862 }
15864 /* Unwinding tables are not referenced directly. This pass marks them as
15865 required if the corresponding code section is marked. Similarly, ARMv8-M
15866 secure entry functions can only be referenced by SG veneers which are
15867 created after the GC process. They need to be marked in case they reside in
15868 their own section (as would be the case if code was compiled with
15869 -ffunction-sections). */
15871 static bfd_boolean
15873 elf_gc_mark_hook_fn gc_mark_hook)
15874 {
15894 /* Marking EH data may cause additional code sections to be marked,
15895 requiring multiple passes. */
15898 {
15901 {
15909 {
15918 {
15922 }
15923 }
15925 /* Mark section holding ARMv8-M secure entry functions. We mark all
15926 of them so no need for a second browsing. */
15928 {
15935 /* Scan symbols. */
15937 {
15940 /* Assume it is a special symbol. If not, cmse_scan will
15941 warn about it and user can do something about it. */
15943 CMSE_PREFIX))
15944 {
15949 /* The debug sections related to these secure entry
15950 functions are marked on enabling below flag. */
15952 }
15953 }
15956 {
15957 /* Looping over all the sections of the object file containing
15958 Armv8-M secure entry functions and marking all the debug
15959 sections. */
15961 {
15962 /* If not a debug sections, skip it. */
15965 }
15967 }
15968 }
15969 }
15971 }
15974 }
15976 /* Treat mapping symbols as special target symbols. */
15978 static bfd_boolean
15980 {
15982 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
15983 }
15985 /* If the ELF symbol SYM might be a function in SEC, return the
15986 function size and set *CODE_OFF to the function's entry point,
15987 otherwise return zero. */
15989 static bfd_size_type
15992 {
15993 bfd_size_type size;
16002 {
16009 }
16013 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16023 }
16025 static bfd_boolean
16030 {
16031 bfd_boolean found;
16036 }
16038 /* Adjust a symbol defined by a dynamic object and referenced by a
16039 regular object. The current definition is in some section of the
16040 dynamic object, but we're not including those sections. We have to
16041 change the definition to something the rest of the link can
16042 understand. */
16044 static bfd_boolean
16047 {
16059 /* Make sure we know what is going on here. */
16070 /* If this is a function, put it in the procedure linkage table. We
16071 will fill in the contents of the procedure linkage table later,
16072 when we know the address of the .got section. */
16074 {
16075 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16076 symbol binds locally. */
16082 {
16083 /* This case can occur if we saw a PLT32 reloc in an input
16084 file, but the symbol was never referred to by a dynamic
16085 object, or if all references were garbage collected. In
16086 such a case, we don't actually need to build a procedure
16087 linkage table, and we can just do a PC24 reloc instead. */
16093 }
16096 }
16097 else
16098 {
16099 /* It's possible that we incorrectly decided a .plt reloc was
16100 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16101 in check_relocs. We can't decide accurately between function
16102 and non-function syms in check-relocs; Objects loaded later in
16103 the link may change h->type. So fix it now. */
16108 }
16110 /* If this is a weak symbol, and there is a real definition, the
16111 processor independent code will have arranged for us to see the
16112 real definition first, and we can just use the same value. */
16114 {
16120 }
16122 /* If there are no non-GOT references, we do not need a copy
16123 relocation. */
16127 /* This is a reference to a symbol defined by a dynamic object which
16128 is not a function. */
16130 /* If we are creating a shared library, we must presume that the
16131 only references to the symbol are via the global offset table.
16132 For such cases we need not do anything here; the relocations will
16133 be handled correctly by relocate_section. Relocatable executables
16134 can reference data in shared objects directly, so we don't need to
16135 do anything here. */
16139 /* We must allocate the symbol in our .dynbss section, which will
16140 become part of the .bss section of the executable. There will be
16141 an entry for this symbol in the .dynsym section. The dynamic
16142 object will contain position independent code, so all references
16143 from the dynamic object to this symbol will go through the global
16144 offset table. The dynamic linker will use the .dynsym entry to
16145 determine the address it must put in the global offset table, so
16146 both the dynamic object and the regular object will refer to the
16147 same memory location for the variable. */
16148 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16149 linker to copy the initial value out of the dynamic object and into
16150 the runtime process image. We need to remember the offset into the
16151 .rel(a).bss section we are going to use. */
16153 {
16156 }
16157 else
16158 {
16161 }
16165 {
16168 }
16171 }
16173 /* Allocate space in .plt, .got and associated reloc sections for
16174 dynamic relocs. */
16176 static bfd_boolean
16178 {
16196 {
16197 /* Make sure this symbol is output as a dynamic symbol.
16198 Undefined weak syms won't yet be marked as dynamic. */
16201 {
16204 }
16206 /* If the call in the PLT entry binds locally, the associated
16207 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16208 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16209 than the .plt section. */
16211 {
16215 /* All non-call references can be resolved directly.
16216 This means that they can (and in some cases, must)
16217 resolve directly to the run-time target, rather than
16218 to the PLT. That in turns means that any .got entry
16219 would be equal to the .igot.plt entry, so there's
16220 no point having both. */
16222 }
16227 {
16230 /* If this symbol is not defined in a regular file, and we are
16231 not generating a shared library, then set the symbol to this
16232 location in the .plt. This is required to make function
16233 pointers compare as equal between the normal executable and
16234 the shared library. */
16237 {
16241 /* Make sure the function is not marked as Thumb, in case
16242 it is the target of an ABS32 relocation, which will
16243 point to the PLT entry. */
16245 }
16247 /* VxWorks executables have a second set of relocations for
16248 each PLT entry. They go in a separate relocation section,
16249 which is processed by the kernel loader. */
16251 {
16252 /* There is a relocation for the initial PLT entry:
16253 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16257 /* There are two extra relocations for each subsequent
16258 PLT entry: an R_ARM_32 relocation for the GOT entry,
16259 and an R_ARM_32 relocation for the PLT entry. */
16261 }
16262 }
16263 else
16264 {
16267 }
16268 }
16269 else
16270 {
16273 }
16279 {
16281 bfd_boolean dyn;
16285 /* Make sure this symbol is output as a dynamic symbol.
16286 Undefined weak syms won't yet be marked as dynamic. */
16289 {
16292 }
16295 {
16303 /* Non-TLS symbols need one GOT slot. */
16305 else
16306 {
16308 {
16309 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16310 eh->tlsdesc_got
16315 /* plt.got_offset needs to know there's a TLS_DESC
16316 reloc in the middle of .got.plt. */
16318 }
16321 {
16322 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16323 consecutive GOT slots. If the symbol is both GD
16324 and GDESC, got.offset may have been
16325 overwritten. */
16328 }
16331 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16332 slot. */
16334 }
16341 h)
16350 {
16358 {
16360 /* GDESC needs a trampoline to jump to. */
16362 }
16364 /* Only GD needs it. GDESC just emits one relocation per
16365 2 entries. */
16368 }
16371 {
16373 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16375 }
16378 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16379 they all resolve dynamically instead. Reserve room for the
16380 GOT entry's R_ARM_IRELATIVE relocation. */
16384 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16387 /* Reserve room for rofixup for FDPIC executable. */
16388 /* TLS relocs do not need space since they are completely
16389 resolved. */
16391 }
16392 }
16393 else
16396 /* FDPIC support. */
16398 {
16399 /* Symbol musn't be exported. */
16403 /* We only allocate one function descriptor with its associated relocation. */
16405 {
16410 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16413 else
16415 }
16416 }
16419 {
16428 {
16429 /* We only allocate one function descriptor with its associated relocation. q */
16431 {
16435 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16438 else
16440 }
16441 }
16443 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16444 R_ARM_RELATIVE/rofixup relocation on it. */
16449 else
16451 }
16454 {
16461 {
16462 /* We only allocate one function descriptor with its associated relocation. */
16464 {
16469 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16472 else
16474 }
16475 }
16477 {
16478 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16480 }
16481 else
16482 {
16483 /* Will need one dynamic reloc per reference. will be either
16484 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16487 }
16488 }
16490 /* Allocate stubs for exported Thumb functions on v4t. */
16495 {
16502 /* Create a new symbol to regist the real location of the function. */
16516 /* Point the symbol at the stub. */
16521 }
16526 /* In the shared -Bsymbolic case, discard space allocated for
16527 dynamic pc-relative relocs against symbols which turn out to be
16528 defined in regular objects. For the normal shared case, discard
16529 space for pc-relative relocs that have become local due to symbol
16530 visibility changes. */
16533 {
16534 /* Relocs that use pc_count are PC-relative forms, which will appear
16535 on something like ".long foo - ." or "movw REG, foo - .". We want
16536 calls to protected symbols to resolve directly to the function
16537 rather than going via the plt. If people want function pointer
16538 comparisons to work as expected then they should avoid writing
16539 assembly like ".long foo - .". */
16541 {
16545 {
16550 else
16552 }
16553 }
16556 {
16560 {
16563 else
16565 }
16566 }
16568 /* Also discard relocs on undefined weak syms with non-default
16569 visibility. */
16572 {
16577 /* Make sure undefined weak symbols are output as a dynamic
16578 symbol in PIEs. */
16581 {
16584 }
16585 }
16589 {
16590 /* Output absolute symbols so that we can create relocations
16591 against them. For normal symbols we output a relocation
16592 against the section that contains them. */
16595 }
16597 }
16598 else
16599 {
16600 /* For the non-shared case, discard space for relocs against
16601 symbols which turn out to need copy relocs or are not
16602 dynamic. */
16610 {
16611 /* Make sure this symbol is output as a dynamic symbol.
16612 Undefined weak syms won't yet be marked as dynamic. */
16615 {
16618 }
16620 /* If that succeeded, we know we'll be keeping all the
16621 relocs. */
16624 }
16628 keep: ;
16629 }
16631 /* Finally, allocate space. */
16633 {
16644 else
16646 }
16649 }
16651 void
16654 {
16662 }
16664 /* Set the sizes of the dynamic sections. */
16666 static bfd_boolean
16669 {
16672 bfd_boolean relocs;
16685 {
16686 /* Set the contents of the .interp section to the interpreter. */
16688 {
16693 }
16694 }
16696 /* Set up .got offsets for local syms, and space for local dynamic
16697 relocs. */
16699 {
16705 bfd_size_type locsymcount;
16715 {
16720 {
16723 {
16724 /* Input section has been discarded, either because
16725 it is a copy of a linkonce section or due to
16726 linker script /DISCARD/, so we'll be discarding
16727 the relocs too. */
16728 }
16732 {
16733 /* Relocations in vxworks .tls_vars sections are
16734 handled specially by the loader. */
16735 }
16737 {
16741 else
16745 }
16746 }
16747 }
16766 {
16770 /* FDPIC support. */
16772 {
16774 {
16778 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16781 else
16783 }
16784 }
16787 {
16789 {
16793 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16796 else
16798 }
16800 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16803 else
16805 }
16808 {
16812 {
16817 /* All references to the PLT are calls, so all
16818 non-call references can resolve directly to the
16819 run-time target. This means that the .got entry
16820 would be the same as the .igot.plt entry, so there's
16821 no point creating both. */
16823 }
16824 else
16825 {
16828 }
16831 {
16837 else
16839 }
16840 }
16842 {
16847 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16850 {
16855 /* plt.got_offset needs to know there's a TLS_DESC
16856 reloc in the middle of .got.plt. */
16858 }
16863 {
16864 /* If the symbol is both GD and GDESC, *local_got
16865 may have been overwritten. */
16868 }
16871 symndx);
16875 /* If all references to an STT_GNU_IFUNC PLT are calls,
16876 then all non-call references, including this GOT entry,
16877 resolve directly to the run-time target. */
16883 {
16891 {
16895 }
16896 }
16897 }
16898 else
16900 }
16901 }
16904 {
16905 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16906 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
16911 }
16912 else
16915 /* At the very end of the .rofixup section is a pointer to the GOT,
16916 reserve space for it. */
16920 /* Allocate global sym .plt and .got entries, and space for global
16921 sym dynamic relocs. */
16924 /* Here we rummage through the found bfds to collect glue information. */
16926 {
16930 /* Initialise mapping tables for code/data. */
16937 }
16939 /* Allocate space for the glue sections now that we've sized them. */
16942 /* For every jump slot reserved in the sgotplt, reloc_count is
16943 incremented. However, when we reserve space for TLS descriptors,
16944 it's not incremented, so in order to compute the space reserved
16945 for them, it suffices to multiply the reloc count by the jump
16946 slot size. */
16951 {
16958 /* If we're not using lazy TLS relocations, don't generate the
16959 PLT and GOT entries they require. */
16962 else
16963 {
16969 }
16970 }
16972 /* The check_relocs and adjust_dynamic_symbol entry points have
16973 determined the sizes of the various dynamic sections. Allocate
16974 memory for them. */
16977 {
16983 /* It's OK to base decisions on the section name, because none
16984 of the dynobj section names depend upon the input files. */
16988 {
16989 /* Remember whether there is a PLT. */
16990 ;
16991 }
16993 {
16995 {
16996 /* Remember whether there are any reloc sections other
16997 than .rel(a).plt and .rela.plt.unloaded. */
17001 /* We use the reloc_count field as a counter if we need
17002 to copy relocs into the output file. */
17004 }
17005 }
17013 {
17014 /* It's not one of our sections, so don't allocate space. */
17016 }
17019 {
17020 /* If we don't need this section, strip it from the
17021 output file. This is mostly to handle .rel(a).bss and
17022 .rel(a).plt. We must create both sections in
17023 create_dynamic_sections, because they must be created
17024 before the linker maps input sections to output
17025 sections. The linker does that before
17026 adjust_dynamic_symbol is called, and it is that
17027 function which decides whether anything needs to go
17028 into these sections. */
17031 }
17036 /* Allocate memory for the section contents. */
17040 }
17043 relocs);
17044 }
17046 /* Size sections even though they're not dynamic. We use it to setup
17047 _TLS_MODULE_BASE_, if needed. */
17049 static bfd_boolean
17052 {
17064 {
17067 tlsbase = elf_link_hash_lookup
17071 {
17087 }
17088 }
17096 }
17098 /* Finish up dynamic symbol handling. We set the contents of various
17099 dynamic sections here. */
17101 static bfd_boolean
17106 {
17117 {
17119 {
17124 }
17127 {
17128 /* Mark the symbol as undefined, rather than as defined in
17129 the .plt section. */
17131 /* If the symbol is weak we need to clear the value.
17132 Otherwise, the PLT entry would provide a definition for
17133 the symbol even if the symbol wasn't defined anywhere,
17134 and so the symbol would never be NULL. Leave the value if
17135 there were any relocations where pointer equality matters
17136 (this is a clue for the dynamic linker, to make function
17137 pointer comparisons work between an application and shared
17138 library). */
17141 }
17143 {
17144 /* At least one non-call relocation references this .iplt entry,
17145 so the .iplt entry is the function's canonical address. */
17153 }
17154 }
17157 {
17159 Elf_Internal_Rela rel;
17161 /* This symbol needs a copy reloc. Set it up. */
17173 else
17176 }
17178 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17179 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17180 it is relative to the ".got" section. */
17188 }
17190 static void
17194 {
17198 {
17201 /* Emit mov pc,rx if bx is not permitted. */
17205 }
17206 }
17208 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17209 other variants, NaCl needs this entry in a static executable's
17210 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17211 zero. For .iplt really only the last bundle is useful, and .iplt
17212 could have a shorter first entry, with each individual PLT entry's
17213 relative branch calculated differently so it targets the last
17214 bundle instead of the instruction before it (labelled .Lplt_tail
17215 above). But it's simpler to keep the size and layout of PLT0
17216 consistent with the dynamic case, at the cost of some dead code at
17217 the start of .iplt and the one dead store to the stack at the start
17218 of .Lplt_tail. */
17219 static void
17222 {
17238 }
17240 /* Finish up the dynamic sections. */
17242 static bfd_boolean
17244 {
17257 /* A broken linker script might have discarded the dynamic sections.
17258 Catch this here so that we do not seg-fault later on. */
17264 {
17276 {
17277 Elf_Internal_Dyn dyn;
17284 {
17318 get_vma:
17321 {
17322 _bfd_error_handler
17326 }
17329 else
17330 /* In the BPABI, tags in the PT_DYNAMIC section point
17331 at the file offset, not the memory address, for the
17332 convenience of the post linker. */
17337 get_vma_if_bpabi:
17353 /* In the BPABI, the DT_REL tag must point at the file
17354 offset, not the VMA, of the first relocation
17355 section. So, we use code similar to that in
17356 elflink.c, but do not check for SHF_ALLOC on the
17357 relocation section, since relocation sections are
17358 never allocated under the BPABI. PLT relocs are also
17359 included. */
17361 {
17367 {
17368 Elf_Internal_Shdr *hdr
17371 {
17378 }
17379 }
17381 }
17398 /* Set the bottom bit of DT_INIT/FINI if the
17399 corresponding function is Thumb. */
17405 get_sym:
17406 /* If it wasn't set by elf_bfd_final_link
17407 then there is nothing to adjust. */
17409 {
17417 {
17420 }
17421 }
17423 }
17424 }
17426 /* Fill in the first entry in the procedure linkage table. */
17428 {
17432 /* Calculate the addresses of the GOT and PLT. */
17437 {
17438 /* The VxWorks GOT is relocated by the dynamic linker.
17439 Therefore, we must emit relocations rather than simply
17440 computing the values now. */
17441 Elf_Internal_Rela rel;
17452 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17458 }
17463 {
17475 }
17476 else
17477 {
17490 #ifdef FOUR_WORD_PLT
17491 /* The displacement value goes in the otherwise-unused
17492 last word of the second entry. */
17494 #else
17496 #endif
17497 }
17498 }
17500 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17501 really seem like the right value. */
17506 {
17507 bfd_vma got_address
17511 bfd_vma plt_address
17527 }
17530 {
17534 #ifdef FOUR_WORD_PLT
17537 #endif
17538 }
17543 {
17544 /* Correct the .rel(a).plt.unloaded relocations. They will have
17545 incorrect symbol indexes. */
17554 {
17555 Elf_Internal_Rela rel;
17566 }
17567 }
17568 }
17573 /* NaCl uses a special first entry in .iplt too. */
17576 /* Fill in the first three entries in the global offset table. */
17578 {
17580 {
17583 else
17589 }
17592 }
17594 /* At the very end of the .rofixup section is a pointer to the GOT. */
17596 {
17605 /* Make sure we allocated and generated the same number of fixups. */
17607 }
17610 }
17612 static bfd_boolean
17614 {
17629 {
17636 }
17640 {
17644 else
17646 }
17648 /* Scan segment to set p_flags attribute if it contains only sections with
17649 SHF_ARM_PURECODE flag. */
17651 {
17657 {
17660 }
17662 {
17665 }
17666 }
17668 }
17670 static enum elf_reloc_type_class
17674 {
17676 {
17687 }
17688 }
17690 static void
17692 {
17694 }
17696 static bfd_boolean
17698 {
17701 }
17703 /* Return TRUE if this is an unwinding table entry. */
17705 static bfd_boolean
17707 {
17710 }
17713 /* Set the type and flags for an ARM section. We do this by
17714 the section name, which is a hack, but ought to work. */
17716 static bfd_boolean
17718 {
17724 {
17727 }
17733 }
17735 /* Handle an ARM specific section when reading an object file. This is
17736 called when bfd_section_from_shdr finds a section with an unknown
17737 type. */
17739 static bfd_boolean
17744 {
17745 /* There ought to be a place to keep ELF backend specific flags, but
17746 at the moment there isn't one. We just keep track of the
17747 sections by their name, instead. Fortunately, the ABI gives
17748 names for all the ARM specific sections, so we will probably get
17749 away with this. */
17751 {
17759 }
17765 }
17769 {
17772 else
17774 }
17777 {
17786 enum map_symbol_type
17787 {
17788 ARM_MAP_ARM,
17789 ARM_MAP_THUMB,
17790 ARM_MAP_DATA
17791 };
17794 /* Output a single mapping symbol. */
17796 static bfd_boolean
17799 bfd_vma offset)
17800 {
17802 Elf_Internal_Sym sym;
17814 }
17816 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17817 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
17819 static bfd_boolean
17821 bfd_boolean is_iplt_entry_p,
17824 {
17836 {
17839 }
17840 else
17841 {
17844 }
17850 {
17855 }
17857 {
17866 }
17868 {
17871 }
17873 {
17875 ? ARM_MAP_THUMB
17888 }
17890 {
17893 }
17894 else
17895 {
17896 bfd_boolean thumb_stub_p;
17900 {
17903 }
17904 #ifdef FOUR_WORD_PLT
17909 #else
17910 /* A three-word PLT with no Thumb thunk contains only Arm code,
17911 so only need to output a mapping symbol for the first PLT entry and
17912 entries with thumb thunks. */
17914 {
17917 }
17918 #endif
17919 }
17922 }
17924 /* Output mapping symbols for PLT entries associated with H. */
17926 static bfd_boolean
17928 {
17936 /* When warning symbols are created, they **replace** the "real"
17937 entry in the hash table, thus we never get to see the real
17938 symbol in a hash traversal. So look at it now. */
17944 }
17946 /* Bind a veneered symbol to its veneer identified by its hash entry
17947 STUB_ENTRY. The veneered location thus loose its symbol. */
17949 static void
17951 {
17958 }
17960 /* Output a single local symbol for a generated stub. */
17962 static bfd_boolean
17965 {
17966 Elf_Internal_Sym sym;
17977 }
17979 static bfd_boolean
17982 {
17985 bfd_vma addr;
17994 /* Massage our args to the form they really have. */
18000 /* Ensure this stub is attached to the current section being
18001 processed. */
18010 else
18011 {
18014 {
18029 }
18030 }
18035 {
18037 {
18054 }
18057 {
18061 }
18064 {
18081 }
18082 }
18085 }
18087 /* Output mapping symbols for linker generated sections,
18088 and for those data-only sections that do not have a
18089 $d. */
18091 static bfd_boolean
18096 Elf_Internal_Sym *,
18097 asection *,
18099 {
18100 output_arch_syminfo osi;
18102 bfd_vma offset;
18103 bfd_size_type size;
18116 /* Add a $d mapping symbol to data-only sections that
18117 don't have any mapping symbol. This may result in (harmless) redundant
18118 mapping symbols. */
18122 {
18127 {
18132 == SEC_HAS_CONTENTS
18137 {
18142 }
18143 }
18144 }
18146 /* ARM->Thumb glue. */
18148 {
18150 ARM2THUMB_GLUE_SECTION_NAME);
18159 else
18163 {
18166 }
18167 }
18169 /* Thumb->ARM glue. */
18171 {
18173 THUMB2ARM_GLUE_SECTION_NAME);
18180 {
18183 }
18184 }
18186 /* ARMv4 BX veneers. */
18188 {
18190 ARM_BX_GLUE_SECTION_NAME);
18196 }
18198 /* Long calls stubs. */
18200 {
18206 {
18207 /* Ignore non-stub sections. */
18217 }
18218 }
18220 /* Finally, output mapping symbols for the PLT. */
18222 {
18227 /* Output mapping symbols for the plt header. SymbianOS does not have a
18228 plt header. */
18230 {
18231 /* VxWorks shared libraries have no PLT header. */
18233 {
18238 }
18239 }
18241 {
18244 }
18246 {
18253 }
18255 {
18258 #ifndef FOUR_WORD_PLT
18261 #endif
18262 }
18263 }
18267 {
18268 /* NaCl uses a special first entry in .iplt too. */
18274 }
18277 {
18282 {
18288 {
18296 }
18297 }
18298 }
18300 {
18301 /* Mapping symbols for the lazy tls trampoline. */
18309 }
18311 {
18312 /* Mapping symbols for the tls trampoline. */
18315 #ifdef FOUR_WORD_PLT
18319 #endif
18320 }
18323 }
18325 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18326 the import library. All SYMCOUNT symbols of ABFD can be examined
18327 from their pointers in SYMS. Pointers of symbols to keep should be
18328 stored continuously at the beginning of that array.
18330 Returns the number of symbols to keep. */
18332 static unsigned int
18336 {
18351 {
18354 flagword flags;
18369 {
18373 }
18385 }
18391 }
18393 /* Filter symbols of ABFD to include in the import library. All
18394 SYMCOUNT symbols of ABFD can be examined from their pointers in
18395 SYMS. Pointers of symbols to keep should be stored continuously at
18396 the beginning of that array.
18398 Returns the number of symbols to keep. */
18400 static unsigned int
18404 {
18407 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18408 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18409 library to be a relocatable object file. */
18413 else
18415 }
18417 /* Allocate target specific section data. */
18419 static bfd_boolean
18421 {
18423 {
18431 }
18434 }
18437 /* Used to order a list of mapping symbols by address. */
18439 static int
18441 {
18450 /* Ensure results do not depend on the host qsort for objects with
18451 multiple mapping symbols at the same address by sorting on type
18452 after vma. */
18456 else
18458 }
18460 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18462 static unsigned long
18464 {
18466 }
18468 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18469 relocations. */
18471 static void
18473 {
18477 /* High bit of first word is supposed to be zero. */
18481 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18482 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18488 }
18490 /* Data for make_branch_to_a8_stub(). */
18492 struct a8_branch_to_stub_data
18493 {
18496 };
18499 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18500 places for a particular section. */
18502 static bfd_boolean
18505 {
18511 bfd_signed_vma branch_offset;
18524 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18525 generated when both source and target are in the same section. */
18542 /* We attempt to avoid this condition by setting stubs_always_after_branch
18543 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18544 This check is just to be on the safe side... */
18546 {
18550 }
18553 {
18564 {
18569 jump24:
18571 {
18572 /* There's not much we can do apart from complain if this
18573 happens. */
18577 }
18579 /* i1 = not(j1 eor s), so:
18580 not i1 = j1 eor s
18581 j1 = (not i1) eor s. */
18593 }
18599 }
18605 }
18607 /* Beginning of stm32l4xx work-around. */
18609 /* Functions encoding instructions necessary for the emission of the
18610 fix-stm32l4xx-629360.
18611 Encoding is extracted from the
18612 ARM (C) Architecture Reference Manual
18613 ARMv7-A and ARMv7-R edition
18614 ARM DDI 0406C.b (ID072512). */
18618 {
18619 /* A8.8.18 B (A8-334)
18620 B target_address (Encoding T4). */
18621 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18622 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18623 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18640 }
18644 {
18645 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18646 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18653 }
18657 {
18658 /* A8.8.60 LDMDB/LDMEA (A8-402)
18659 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18666 }
18670 {
18671 /* A8.8.103 MOV (register) (A8-486)
18672 MOV Rd, Rm (Encoding T1). */
18679 }
18683 {
18684 /* A8.8.221 SUB (immediate) (A8-708)
18685 SUB Rd, Rn, #value (Encoding T3). */
18695 }
18700 {
18701 /* A8.8.332 VLDM (A8-922)
18702 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18711 }
18716 {
18717 /* A8.8.332 VLDM (A8-922)
18718 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18726 }
18730 {
18731 /* A8.8.247 UDF (A8-758)
18732 Undefined (Encoding T2). */
18738 }
18742 {
18743 /* A8.8.247 UDF (A8-758)
18744 Undefined (Encoding T1). */
18749 }
18751 /* Functions writing an instruction in memory, returning the next
18752 memory position to write to. */
18757 {
18760 }
18765 {
18768 }
18770 /* Function filling up a region in memory with T1 and T2 UDFs taking
18771 care of alignment. */
18779 {
18782 /* Fill the remaining of the stub with deterministic contents : UDF
18783 instructions.
18784 Check if realignment is needed on modulo 4 frontier using T1, to
18785 further use T2. */
18789 current_stub_contents =
18794 current_stub_contents =
18799 }
18801 /* Functions writing the stream of instructions equivalent to the
18802 derived sequence for ldmia, ldmdb, vldm respectively. */
18804 static void
18810 {
18823 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18824 smaller than 8 registers load sequences that do not cause the
18825 hardware issue. */
18827 {
18828 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18829 current_stub_contents =
18831 initial_insn);
18833 /* B initial_insn_addr+4. */
18835 current_stub_contents =
18837 create_instruction_branch_absolute
18840 /* Fill the remaining of the stub with deterministic contents. */
18841 current_stub_contents =
18844 base_stub_contents +
18845 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18848 }
18850 /* - reg_list[13] == 0. */
18853 /* - reg_list[14] & reg_list[15] != 1. */
18856 /* - if (wback==1) reg_list[rn] == 0. */
18859 /* - nb_registers > 8. */
18862 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18864 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18865 - One with the 7 lowest registers (register mask 0x007F)
18866 This LDM will finally contain between 2 and 7 registers
18867 - One with the 7 highest registers (register mask 0xDF80)
18868 This ldm will finally contain between 2 and 7 registers. */
18872 /* A spare register may be needed during this veneer to temporarily
18873 handle the base register. This register will be restored with the
18874 last LDM operation.
18875 The usable register may be any general purpose register (that
18876 excludes PC, SP, LR : register mask is 0x1FFF). */
18879 /* Generate the stub function. */
18881 {
18882 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18883 current_stub_contents =
18885 create_instruction_ldmia
18888 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18889 current_stub_contents =
18891 create_instruction_ldmia
18894 {
18895 /* B initial_insn_addr+4. */
18896 current_stub_contents =
18898 create_instruction_branch_absolute
18900 }
18901 }
18903 {
18906 /* If Rn is not part of the high-register-list, move it there. */
18908 {
18909 /* Choose a Ri in the high-register-list that will be restored. */
18912 /* MOV Ri, Rn. */
18913 current_stub_contents =
18916 }
18918 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18919 current_stub_contents =
18921 create_instruction_ldmia
18924 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18925 current_stub_contents =
18927 create_instruction_ldmia
18931 {
18932 /* B initial_insn_addr+4. */
18933 current_stub_contents =
18935 create_instruction_branch_absolute
18937 }
18938 }
18940 /* Fill the remaining of the stub with deterministic contents. */
18941 current_stub_contents =
18944 base_stub_contents +
18945 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18946 }
18948 static void
18954 {
18967 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18968 smaller than 8 registers load sequences that do not cause the
18969 hardware issue. */
18971 {
18972 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18973 current_stub_contents =
18975 initial_insn);
18977 /* B initial_insn_addr+4. */
18978 current_stub_contents =
18980 create_instruction_branch_absolute
18983 /* Fill the remaining of the stub with deterministic contents. */
18984 current_stub_contents =
18987 base_stub_contents +
18988 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18991 }
18993 /* - reg_list[13] == 0. */
18996 /* - reg_list[14] & reg_list[15] != 1. */
18999 /* - if (wback==1) reg_list[rn] == 0. */
19002 /* - nb_registers > 8. */
19005 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19007 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19008 - One with the 7 lowest registers (register mask 0x007F)
19009 This LDM will finally contain between 2 and 7 registers
19010 - One with the 7 highest registers (register mask 0xDF80)
19011 This ldm will finally contain between 2 and 7 registers. */
19015 /* A spare register may be needed during this veneer to temporarily
19016 handle the base register. This register will be restored with
19017 the last LDM operation.
19018 The usable register may be any general purpose register (that excludes
19019 PC, SP, LR : register mask is 0x1FFF). */
19022 /* Generate the stub function. */
19024 {
19025 /* Choose a Ri in the low-register-list that will be restored. */
19028 /* MOV Ri, Rn. */
19029 current_stub_contents =
19033 /* LDMDB Ri!, {R-high-register-list}. */
19034 current_stub_contents =
19036 create_instruction_ldmdb
19039 /* LDMDB Ri, {R-low-register-list}. */
19040 current_stub_contents =
19042 create_instruction_ldmdb
19045 /* B initial_insn_addr+4. */
19046 current_stub_contents =
19048 create_instruction_branch_absolute
19050 }
19052 {
19053 /* LDMDB Rn!, {R-high-register-list}. */
19054 current_stub_contents =
19056 create_instruction_ldmdb
19059 /* LDMDB Rn!, {R-low-register-list}. */
19060 current_stub_contents =
19062 create_instruction_ldmdb
19065 /* B initial_insn_addr+4. */
19066 current_stub_contents =
19068 create_instruction_branch_absolute
19070 }
19072 {
19073 /* Choose a Ri in the high-register-list that will be restored. */
19076 /* SUB Ri, Rn, #(4*nb_registers). */
19077 current_stub_contents =
19081 /* LDMIA Ri!, {R-low-register-list}. */
19082 current_stub_contents =
19084 create_instruction_ldmia
19087 /* LDMIA Ri, {R-high-register-list}. */
19088 current_stub_contents =
19090 create_instruction_ldmia
19092 }
19094 {
19095 /* Choose a Ri in the high-register-list that will be restored. */
19098 /* SUB Rn, Rn, #(4*nb_registers) */
19099 current_stub_contents =
19103 /* MOV Ri, Rn. */
19104 current_stub_contents =
19108 /* LDMIA Ri!, {R-low-register-list}. */
19109 current_stub_contents =
19111 create_instruction_ldmia
19114 /* LDMIA Ri, {R-high-register-list}. */
19115 current_stub_contents =
19117 create_instruction_ldmia
19119 }
19121 {
19124 {
19125 /* Choose a Ri in the low-register-list that will be restored. */
19128 /* MOV Ri, Rn. */
19129 current_stub_contents =
19132 }
19134 /* LDMDB Ri!, {R-high-register-list}. */
19135 current_stub_contents =
19137 create_instruction_ldmdb
19140 /* LDMDB Ri, {R-low-register-list}. */
19141 current_stub_contents =
19143 create_instruction_ldmdb
19146 /* B initial_insn_addr+4. */
19147 current_stub_contents =
19149 create_instruction_branch_absolute
19151 }
19153 {
19156 {
19157 /* Choose a Ri in the high-register-list that will be restored. */
19159 }
19161 /* SUB Ri, Rn, #(4*nb_registers). */
19162 current_stub_contents =
19166 /* LDMIA Ri!, {R-low-register-list}. */
19167 current_stub_contents =
19169 create_instruction_ldmia
19172 /* LDMIA Ri, {R-high-register-list}. */
19173 current_stub_contents =
19175 create_instruction_ldmia
19177 }
19179 {
19180 /* The assembler should not have accepted to encode this. */
19183 }
19185 /* Fill the remaining of the stub with deterministic contents. */
19186 current_stub_contents =
19189 base_stub_contents +
19190 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19192 }
19194 static void
19200 {
19206 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19207 smaller than 8 words load sequences that do not cause the
19208 hardware issue. */
19210 {
19211 /* Untouched instruction. */
19212 current_stub_contents =
19214 initial_insn);
19216 /* B initial_insn_addr+4. */
19217 current_stub_contents =
19219 create_instruction_branch_absolute
19221 }
19222 else
19223 {
19233 /* d = UInt (Vd:D);. */
19237 /* Compute the number of 8-words chunks needed to split. */
19241 /* The test coverage has been done assuming the following
19242 hypothesis that exactly one of the previous is_ predicates is
19243 true. */
19247 /* We treat the cutting of the words in one pass for all
19248 cases, then we emit the adjustments:
19250 vldm rx, {...}
19251 -> vldm rx!, {8_words_or_less} for each needed 8_word
19252 -> sub rx, rx, #size (list)
19254 vldm rx!, {...}
19255 -> vldm rx!, {8_words_or_less} for each needed 8_word
19256 This also handles vpop instruction (when rx is sp)
19258 vldmd rx!, {...}
19259 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19261 {
19265 {
19266 new_insn = create_instruction_vldmia
19268 is_dp,
19273 }
19275 {
19276 new_insn = create_instruction_vldmdb
19278 is_dp,
19282 }
19285 current_stub_contents =
19287 new_insn);
19288 }
19290 /* Only this case requires the base register compensation
19291 subtract. */
19293 {
19294 current_stub_contents =
19296 create_instruction_sub
19298 }
19300 /* B initial_insn_addr+4. */
19301 current_stub_contents =
19303 create_instruction_branch_absolute
19305 }
19307 /* Fill the remaining of the stub with deterministic contents. */
19308 current_stub_contents =
19311 base_stub_contents +
19312 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19313 }
19315 static void
19321 {
19325 stub_contents);
19329 stub_contents);
19333 stub_contents);
19334 }
19336 /* End of stm32l4xx work-around. */
19339 /* Do code byteswapping. Return FALSE afterwards so that the section is
19340 written out as normal. */
19342 static bfd_boolean
19347 {
19354 bfd_vma ptr;
19355 bfd_vma end;
19357 bfd_byte tmp;
19363 /* If this section has not been allocated an _arm_elf_section_data
19364 structure then we cannot record anything. */
19374 {
19379 {
19383 {
19385 {
19386 bfd_vma branch_to_veneer;
19387 /* Original condition code of instruction, plus bit mask for
19388 ARM B instruction. */
19392 /* The instruction is before the label. */
19395 /* Above offset included in -4 below. */
19409 }
19413 {
19414 bfd_vma branch_from_veneer;
19417 /* Take size of veneer into account. */
19426 /* Original instruction. */
19433 /* Branch back to insn after original insn. */
19439 }
19444 }
19445 }
19446 }
19449 {
19453 {
19457 {
19459 {
19461 bfd_vma branch_to_veneer =
19466 {
19467 bfd_vma out_of_range =
19473 _bfd_error_handler
19475 "cannot create STM32L4XX veneer; "
19478 output_bfd,
19482 }
19484 insn = create_instruction_branch_absolute
19487 /* The instruction is before the label. */
19492 }
19496 {
19502 veneer_r = veneer
19507 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19508 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19509 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19512 {
19516 }
19518 /* Original instruction. */
19521 stm32l4xx_create_replacing_stub
19523 }
19528 }
19529 }
19530 }
19533 {
19534 arm_unwind_table_edit *edit_node
19536 /* Now, sec->size is the size of the section we will write. The original
19537 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19538 markers) was sec->rawsize. (This isn't the case if we perform no
19539 edits, then rawsize will be zero and we should use size). */
19548 {
19550 {
19554 {
19557 out_index++;
19558 in_index++;
19559 }
19563 {
19565 {
19567 in_index++;
19572 {
19580 /* Note: this is meant to be equivalent to an
19581 R_ARM_PREL31 relocation. These synthetic
19582 EXIDX_CANTUNWIND markers are not relocated by the
19583 usual BFD method. */
19587 {
19588 /* Here relocation for new EXIDX_CANTUNWIND is
19589 created, so there is no need to
19590 adjust offset by hand. */
19593 }
19595 /* First address we can't unwind. */
19599 /* Code for EXIDX_CANTUNWIND. */
19603 out_index++;
19605 }
19607 }
19610 }
19611 }
19612 else
19613 {
19614 /* No more edits, copy remaining entries verbatim. */
19617 out_index++;
19618 in_index++;
19619 }
19620 }
19624 edited_contents,
19628 }
19630 /* Fix code to point to Cortex-A8 erratum stubs. */
19632 {
19640 }
19646 {
19651 {
19654 else
19658 {
19660 /* Byte swap code words. */
19662 {
19670 }
19674 /* Byte swap code halfwords. */
19676 {
19681 }
19685 /* Leave data alone. */
19687 }
19689 }
19690 }
19698 }
19700 /* Mangle thumb function symbols as we read them in. */
19702 static bfd_boolean
19707 {
19712 /* New EABI objects mark thumb function symbols by setting the low bit of
19713 the address. */
19716 {
19718 {
19721 ST_BRANCH_TO_THUMB);
19722 }
19723 else
19725 }
19727 {
19730 }
19733 else
19737 }
19740 /* Mangle thumb function symbols as we write them out. */
19742 static void
19747 {
19748 Elf_Internal_Sym newsym;
19750 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19751 of the address set, as per the new EABI. We do this unconditionally
19752 because objcopy does not set the elf header flags until after
19753 it writes out the symbol table. */
19755 {
19760 {
19761 /* Do this only for defined symbols. At link type, the static
19762 linker will simulate the work of dynamic linker of resolving
19763 symbols and will carry over the thumbness of found symbols to
19764 the output symbol table. It's not clear how it happens, but
19765 the thumbness of undefined symbols can well be different at
19766 runtime, and writing '1' for them will be confusing for users
19767 and possibly for dynamic linker itself.
19768 */
19770 }
19773 }
19775 }
19777 /* Add the PT_ARM_EXIDX program header. */
19779 static bfd_boolean
19782 {
19788 {
19789 /* If there is already a PT_ARM_EXIDX header, then we do not
19790 want to add another one. This situation arises when running
19791 "strip"; the input binary already has the header. */
19796 {
19807 }
19808 }
19811 }
19813 /* We may add a PT_ARM_EXIDX program header. */
19815 static int
19818 {
19824 else
19826 }
19828 /* Hook called by the linker routine which adds symbols from an object
19829 file. */
19831 static bfd_boolean
19835 {
19845 }
19847 /* We use this to override swap_symbol_in and swap_symbol_out. */
19849 {
19862 bfd_elf32_write_out_phdrs,
19863 bfd_elf32_write_shdrs_and_ehdr,
19864 bfd_elf32_checksum_contents,
19865 bfd_elf32_write_relocs,
19866 elf32_arm_swap_symbol_in,
19867 elf32_arm_swap_symbol_out,
19868 bfd_elf32_slurp_reloc_table,
19869 bfd_elf32_slurp_symbol_table,
19870 bfd_elf32_swap_dyn_in,
19871 bfd_elf32_swap_dyn_out,
19872 bfd_elf32_swap_reloc_in,
19873 bfd_elf32_swap_reloc_out,
19874 bfd_elf32_swap_reloca_in,
19875 bfd_elf32_swap_reloca_out
19876 };
19878 static bfd_vma
19880 {
19881 /* V7 BE8 code is always little endian. */
19886 }
19888 static bfd_vma
19890 {
19891 /* V7 BE8 code is always little endian. */
19896 }
19898 /* Return size of plt0 entry starting at ADDR
19899 or (bfd_vma) -1 if size can not be determined. */
19901 static bfd_vma
19903 {
19904 bfd_vma first_word;
19905 bfd_vma plt0_size;
19913 else
19914 /* We don't yet handle this PLT format. */
19918 }
19920 /* Return size of plt entry starting at offset OFFSET
19921 of plt section located at address START
19922 or (bfd_vma) -1 if size can not be determined. */
19924 static bfd_vma
19926 {
19927 bfd_vma first_insn;
19931 /* PLT entry size if fixed on Thumb-only platforms. */
19935 /* Respect Thumb stub if necessary. */
19937 {
19939 }
19941 /* Strip immediate from first add. */
19944 #ifdef FOUR_WORD_PLT
19947 #else
19952 #endif
19953 else
19954 /* We don't yet handle this PLT format. */
19958 }
19960 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19962 static long
19969 {
19978 bfd_vma offset;
20007 {
20011 }
20017 {
20021 }
20035 {
20043 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20044 we are defining a symbol, ensure one of them is set. */
20056 {
20063 ;
20067 }
20072 }
20075 }
20077 static bfd_boolean
20079 {
20083 }
20085 static flagword
20087 {
20092 }
20094 static unsigned int
20096 {
20101 }
20103 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20104 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20105 FALSE otherwise. ISECTION is the best guess matching section from the
20106 input bfd IBFD, but it might be NULL. */
20108 static bfd_boolean
20113 {
20115 {
20117 {
20125 /* The sh_link field must be set to the text section associated with
20126 this index section. Unfortunately the ARM EHABI does not specify
20127 exactly how to determine this association. Our caller does try
20128 to match up OSECTION with its corresponding input section however
20129 so that is a good first guess. */
20140 )
20141 {
20146 }
20149 {
20150 /* Failing that we have to find a matching section ourselves. If
20151 we had the output section name available we could compare that
20152 with input section names. Unfortunately we don't. So instead
20153 we use a simple heuristic and look for the nearest executable
20154 section before this one. */
20166 }
20169 {
20171 /* If the text section was part of a group
20172 then the index section should be too. */
20176 }
20177 }
20189 }
20192 }
20194 /* Returns TRUE if NAME is an ARM mapping symbol.
20195 Traditionally the symbols $a, $d and $t have been used.
20196 The ARM ELF standard also defines $x (for A64 code). It also allows a
20197 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20198 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20199 not support them here. $t.x indicates the start of ThumbEE instructions. */
20201 static bfd_boolean
20203 {
20206 the mapping symbols could have acquired a prefix.
20207 We do not support this here, since such symbols no
20208 longer conform to the ARM ELF ABI. */
20211 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20212 any characters that follow the period are legal characters for the body
20213 of a symbol's name. For now we just assume that this is the case. */
20214 }
20216 /* Make sure that mapping symbols in object files are not removed via the
20217 "strip --strip-unneeded" tool. These symbols are needed in order to
20218 correctly generate interworking veneers, and for byte swapping code
20219 regions. Once an object file has been linked, it is safe to remove the
20220 symbols as they will no longer be needed. */
20222 static void
20224 {
20229 }
20231 #undef elf_backend_copy_special_section_fields
20232 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20234 #define ELF_ARCH bfd_arch_arm
20235 #define ELF_TARGET_ID ARM_ELF_DATA
20236 #define ELF_MACHINE_CODE EM_ARM
20237 #ifdef __QNXTARGET__
20238 #define ELF_MAXPAGESIZE 0x1000
20239 #else
20240 #define ELF_MAXPAGESIZE 0x10000
20241 #endif
20242 #define ELF_MINPAGESIZE 0x1000
20243 #define ELF_COMMONPAGESIZE 0x1000
20245 #define bfd_elf32_mkobject elf32_arm_mkobject
20247 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20248 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20249 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20250 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20251 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20252 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20253 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20254 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20255 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20256 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20257 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20258 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20260 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20261 #define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
20262 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20263 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20264 #define elf_backend_check_relocs elf32_arm_check_relocs
20265 #define elf_backend_update_relocs elf32_arm_update_relocs
20266 #define elf_backend_relocate_section elf32_arm_relocate_section
20267 #define elf_backend_write_section elf32_arm_write_section
20268 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20269 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20270 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20271 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20272 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
20273 #define elf_backend_always_size_sections elf32_arm_always_size_sections
20274 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20275 #define elf_backend_init_file_header elf32_arm_init_file_header
20276 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20277 #define elf_backend_object_p elf32_arm_object_p
20278 #define elf_backend_fake_sections elf32_arm_fake_sections
20279 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20280 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20281 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20282 #define elf_backend_size_info elf32_arm_size_info
20283 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20284 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20285 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20286 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20287 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20288 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20289 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20290 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20292 #define elf_backend_can_refcount 1
20293 #define elf_backend_can_gc_sections 1
20294 #define elf_backend_plt_readonly 1
20295 #define elf_backend_want_got_plt 1
20296 #define elf_backend_want_plt_sym 0
20297 #define elf_backend_want_dynrelro 1
20298 #define elf_backend_may_use_rel_p 1
20299 #define elf_backend_may_use_rela_p 0
20300 #define elf_backend_default_use_rela_p 0
20301 #define elf_backend_dtrel_excludes_plt 1
20303 #define elf_backend_got_header_size 12
20304 #define elf_backend_extern_protected_data 1
20306 #undef elf_backend_obj_attrs_vendor
20308 #undef elf_backend_obj_attrs_section
20310 #undef elf_backend_obj_attrs_arg_type
20311 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20312 #undef elf_backend_obj_attrs_section_type
20313 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20314 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20315 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20317 #undef elf_backend_section_flags
20318 #define elf_backend_section_flags elf32_arm_section_flags
20319 #undef elf_backend_lookup_section_flags_hook
20320 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20322 #define elf_backend_linux_prpsinfo32_ugid16 TRUE
20326 /* Native Client targets. */
20328 #undef TARGET_LITTLE_SYM
20329 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20330 #undef TARGET_LITTLE_NAME
20332 #undef TARGET_BIG_SYM
20333 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20334 #undef TARGET_BIG_NAME
20337 /* Like elf32_arm_link_hash_table_create -- but overrides
20338 appropriately for NaCl. */
20342 {
20347 {
20353 }
20355 }
20357 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20358 really need to use elf32_arm_modify_segment_map. But we do it
20359 anyway just to reduce gratuitous differences with the stock ARM backend. */
20361 static bfd_boolean
20363 {
20366 }
20368 static bfd_boolean
20370 {
20373 }
20375 static bfd_vma
20378 {
20382 }
20384 #undef elf32_bed
20385 #define elf32_bed elf32_arm_nacl_bed
20386 #undef bfd_elf32_bfd_link_hash_table_create
20387 #define bfd_elf32_bfd_link_hash_table_create \
20388 elf32_arm_nacl_link_hash_table_create
20389 #undef elf_backend_plt_alignment
20390 #define elf_backend_plt_alignment 4
20391 #undef elf_backend_modify_segment_map
20392 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20393 #undef elf_backend_modify_headers
20394 #define elf_backend_modify_headers nacl_modify_headers
20395 #undef elf_backend_final_write_processing
20396 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20397 #undef bfd_elf32_get_synthetic_symtab
20398 #undef elf_backend_plt_sym_val
20399 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20400 #undef elf_backend_copy_special_section_fields
20402 #undef ELF_MINPAGESIZE
20403 #undef ELF_COMMONPAGESIZE
20405 #undef ELF_TARGET_OS
20406 #define ELF_TARGET_OS is_nacl
20410 /* Reset to defaults. */
20411 #undef elf_backend_plt_alignment
20412 #undef elf_backend_modify_segment_map
20413 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20414 #undef elf_backend_modify_headers
20415 #undef elf_backend_final_write_processing
20416 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20417 #undef ELF_MINPAGESIZE
20418 #define ELF_MINPAGESIZE 0x1000
20419 #undef ELF_COMMONPAGESIZE
20420 #define ELF_COMMONPAGESIZE 0x1000
20423 /* FDPIC Targets. */
20425 #undef TARGET_LITTLE_SYM
20426 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20427 #undef TARGET_LITTLE_NAME
20429 #undef TARGET_BIG_SYM
20430 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20431 #undef TARGET_BIG_NAME
20433 #undef elf_match_priority
20434 #define elf_match_priority 128
20435 #undef ELF_OSABI
20436 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20438 /* Like elf32_arm_link_hash_table_create -- but overrides
20439 appropriately for FDPIC. */
20443 {
20448 {
20452 }
20454 }
20456 /* We need dynamic symbols for every section, since segments can
20457 relocate independently. */
20458 static bfd_boolean
20461 ATTRIBUTE_UNUSED,
20463 {
20465 {
20468 /* If sh_type is yet undecided, assume it could be
20469 SHT_PROGBITS/SHT_NOBITS. */
20473 /* There shouldn't be section relative relocations
20474 against any other section. */
20477 }
20478 }
20480 #undef elf32_bed
20481 #define elf32_bed elf32_arm_fdpic_bed
20483 #undef bfd_elf32_bfd_link_hash_table_create
20484 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20486 #undef elf_backend_omit_section_dynsym
20487 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20489 #undef ELF_TARGET_OS
20493 #undef elf_match_priority
20494 #undef ELF_OSABI
20495 #undef elf_backend_omit_section_dynsym
20497 /* VxWorks Targets. */
20499 #undef TARGET_LITTLE_SYM
20500 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20501 #undef TARGET_LITTLE_NAME
20503 #undef TARGET_BIG_SYM
20504 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20505 #undef TARGET_BIG_NAME
20508 /* Like elf32_arm_link_hash_table_create -- but overrides
20509 appropriately for VxWorks. */
20513 {
20518 {
20522 }
20524 }
20526 static bfd_boolean
20528 {
20531 }
20533 #undef elf32_bed
20534 #define elf32_bed elf32_arm_vxworks_bed
20536 #undef bfd_elf32_bfd_link_hash_table_create
20537 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20538 #undef elf_backend_final_write_processing
20539 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20540 #undef elf_backend_emit_relocs
20541 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20543 #undef elf_backend_may_use_rel_p
20544 #define elf_backend_may_use_rel_p 0
20545 #undef elf_backend_may_use_rela_p
20546 #define elf_backend_may_use_rela_p 1
20547 #undef elf_backend_default_use_rela_p
20548 #define elf_backend_default_use_rela_p 1
20549 #undef elf_backend_want_plt_sym
20550 #define elf_backend_want_plt_sym 1
20551 #undef ELF_MAXPAGESIZE
20552 #define ELF_MAXPAGESIZE 0x1000
20553 #undef ELF_TARGET_OS
20554 #define ELF_TARGET_OS is_vxworks
20559 /* Merge backend specific data from an object file to the output
20560 object file when linking. */
20562 static bfd_boolean
20564 {
20566 flagword out_flags;
20567 flagword in_flags;
20571 /* Check if we have the same endianness. */
20581 /* The input BFD must have had its flags initialised. */
20582 /* The following seems bogus to me -- The flags are initialized in
20583 the assembler but I don't think an elf_flags_init field is
20584 written into the object. */
20585 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20590 /* In theory there is no reason why we couldn't handle this. However
20591 in practice it isn't even close to working and there is no real
20592 reason to want it. */
20596 {
20598 ibfd);
20600 }
20603 {
20604 /* If the input is the default architecture and had the default
20605 flags then do not bother setting the flags for the output
20606 architecture, instead allow future merges to do this. If no
20607 future merges ever set these flags then they will retain their
20608 uninitialised values, which surprise surprise, correspond
20609 to the default values. */
20622 }
20624 /* Determine what should happen if the input ARM architecture
20625 does not match the output ARM architecture. */
20629 /* Identical flags must be compatible. */
20633 /* Check to see if the input BFD actually contains any sections. If
20634 not, its flags may not have been initialised either, but it
20635 cannot actually cause any incompatiblity. Do not short-circuit
20636 dynamic objects; their section list may be emptied by
20637 elf_link_add_object_symbols.
20639 Also check to see if there are no code sections in the input.
20640 In this case there is no need to check for code specific flags.
20641 XXX - do we need to worry about floating-point format compatability
20642 in data sections ? */
20644 {
20649 {
20650 /* Ignore synthetic glue sections. */
20653 {
20661 }
20662 }
20666 }
20668 /* Complain about various flag mismatches. */
20671 {
20672 _bfd_error_handler
20677 }
20679 /* Not sure what needs to be checked for EABI versions >= 1. */
20680 /* VxWorks libraries do not use these flags. */
20684 {
20686 {
20687 _bfd_error_handler
20692 }
20695 {
20697 _bfd_error_handler
20698 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20700 else
20701 _bfd_error_handler
20702 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20706 }
20709 {
20711 _bfd_error_handler
20714 else
20715 _bfd_error_handler
20720 }
20723 {
20725 _bfd_error_handler
20728 else
20729 _bfd_error_handler
20734 }
20736 #ifdef EF_ARM_SOFT_FLOAT
20738 {
20739 /* We can allow interworking between code that is VFP format
20740 layout, and uses either soft float or integer regs for
20741 passing floating point arguments and results. We already
20742 know that the APCS_FLOAT flags match; similarly for VFP
20743 flags. */
20746 {
20748 _bfd_error_handler
20751 else
20752 _bfd_error_handler
20757 }
20758 }
20759 #endif
20761 /* Interworking mismatch is only a warning. */
20763 {
20765 {
20766 _bfd_error_handler
20769 }
20770 else
20771 {
20772 _bfd_error_handler
20775 }
20776 }
20777 }
20780 }
20783 /* Symbian OS Targets. */
20785 #undef TARGET_LITTLE_SYM
20786 #define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20787 #undef TARGET_LITTLE_NAME
20789 #undef TARGET_BIG_SYM
20790 #define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20791 #undef TARGET_BIG_NAME
20794 /* Like elf32_arm_link_hash_table_create -- but overrides
20795 appropriately for Symbian OS. */
20799 {
20804 {
20807 /* There is no PLT header for Symbian OS. */
20809 /* The PLT entries are each one instruction and one word. */
20811 /* Symbian uses armv5t or above, so use_blx is always true. */
20814 }
20816 }
20818 static const struct bfd_elf_special_section
20819 elf32_arm_symbian_special_sections[] =
20820 {
20821 /* In a BPABI executable, the dynamic linking sections do not go in
20822 the loadable read-only segment. The post-linker may wish to
20823 refer to these sections, but they are not part of the final
20824 program image. */
20830 /* These sections do not need to be writable as the SymbianOS
20831 postlinker will arrange things so that no dynamic relocation is
20832 required. */
20837 };
20839 static void
20842 {
20843 /* BPABI objects are never loaded directly by an OS kernel; they are
20844 processed by a postlinker first, into an OS-specific format. If
20845 the D_PAGED bit is set on the file, BFD will align segments on
20846 page boundaries, so that an OS can directly map the file. With
20847 BPABI objects, that just results in wasted space. In addition,
20848 because we clear the D_PAGED bit, map_sections_to_segments will
20849 recognize that the program headers should not be mapped into any
20850 loadable segment. */
20853 }
20855 static bfd_boolean
20858 {
20862 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20863 segment. However, because the .dynamic section is not marked
20864 with SEC_LOAD, the generic ELF code will not create such a
20865 segment. */
20868 {
20874 {
20878 }
20879 }
20881 /* Also call the generic arm routine. */
20883 }
20885 /* Return address for Ith PLT stub in section PLT, for relocation REL
20886 or (bfd_vma) -1 if it should not be included. */
20888 static bfd_vma
20891 {
20893 }
20895 #undef elf32_bed
20896 #define elf32_bed elf32_arm_symbian_bed
20898 /* The dynamic sections are not allocated on SymbianOS; the postlinker
20899 will process them and then discard them. */
20900 #undef ELF_DYNAMIC_SEC_FLAGS
20901 #define ELF_DYNAMIC_SEC_FLAGS \
20902 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20904 #undef elf_backend_emit_relocs
20906 #undef bfd_elf32_bfd_link_hash_table_create
20907 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20908 #undef elf_backend_special_sections
20909 #define elf_backend_special_sections elf32_arm_symbian_special_sections
20910 #undef elf_backend_begin_write_processing
20911 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20912 #undef elf_backend_final_write_processing
20913 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20915 #undef elf_backend_modify_segment_map
20916 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20918 /* There is no .got section for BPABI objects, and hence no header. */
20919 #undef elf_backend_got_header_size
20920 #define elf_backend_got_header_size 0
20922 /* Similarly, there is no .got.plt section. */
20923 #undef elf_backend_want_got_plt
20924 #define elf_backend_want_got_plt 0
20926 #undef elf_backend_plt_sym_val
20927 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20929 #undef elf_backend_may_use_rel_p
20930 #define elf_backend_may_use_rel_p 1
20931 #undef elf_backend_may_use_rela_p
20932 #define elf_backend_may_use_rela_p 0
20933 #undef elf_backend_default_use_rela_p
20934 #define elf_backend_default_use_rela_p 0
20935 #undef elf_backend_want_plt_sym
20936 #define elf_backend_want_plt_sym 0
20937 #undef elf_backend_dtrel_excludes_plt
20938 #define elf_backend_dtrel_excludes_plt 0
20939 #undef ELF_MAXPAGESIZE
20940 #define ELF_MAXPAGESIZE 0x8000
20941 #undef ELF_TARGET_OS
20942 #define ELF_TARGET_OS is_symbian