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RISC-V: Don't report warnings when linking different privileged spec objects.
[binutils-gdb.git] / opcodes / i386-dis.c
blobea3a8e2f8605e69dc2de25d3da8f35707e9b2150
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2024 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 typedef struct instr_info instr_info;
43
44 static bool dofloat (instr_info *, int);
45 static int putop (instr_info *, const char *, int);
46 static void oappend_with_style (instr_info *, const char *,
47 enum disassembler_style);
48
49 static bool OP_E (instr_info *, int, int);
50 static bool OP_E_memory (instr_info *, int, int);
51 static bool OP_indirE (instr_info *, int, int);
52 static bool OP_G (instr_info *, int, int);
53 static bool OP_ST (instr_info *, int, int);
54 static bool OP_STi (instr_info *, int, int);
55 static bool OP_Skip_MODRM (instr_info *, int, int);
56 static bool OP_REG (instr_info *, int, int);
57 static bool OP_IMREG (instr_info *, int, int);
58 static bool OP_I (instr_info *, int, int);
59 static bool OP_I64 (instr_info *, int, int);
60 static bool OP_sI (instr_info *, int, int);
61 static bool OP_J (instr_info *, int, int);
62 static bool OP_SEG (instr_info *, int, int);
63 static bool OP_DIR (instr_info *, int, int);
64 static bool OP_OFF (instr_info *, int, int);
65 static bool OP_OFF64 (instr_info *, int, int);
66 static bool OP_ESreg (instr_info *, int, int);
67 static bool OP_DSreg (instr_info *, int, int);
68 static bool OP_C (instr_info *, int, int);
69 static bool OP_D (instr_info *, int, int);
70 static bool OP_T (instr_info *, int, int);
71 static bool OP_MMX (instr_info *, int, int);
72 static bool OP_XMM (instr_info *, int, int);
73 static bool OP_EM (instr_info *, int, int);
74 static bool OP_EX (instr_info *, int, int);
75 static bool OP_EMC (instr_info *, int,int);
76 static bool OP_MXC (instr_info *, int,int);
77 static bool OP_R (instr_info *, int, int);
78 static bool OP_M (instr_info *, int, int);
79 static bool OP_VEX (instr_info *, int, int);
80 static bool OP_VexR (instr_info *, int, int);
81 static bool OP_VexW (instr_info *, int, int);
82 static bool OP_Rounding (instr_info *, int, int);
83 static bool OP_REG_VexI4 (instr_info *, int, int);
84 static bool OP_VexI4 (instr_info *, int, int);
85 static bool OP_0f07 (instr_info *, int, int);
86 static bool OP_Monitor (instr_info *, int, int);
87 static bool OP_Mwait (instr_info *, int, int);
88
89 static bool PCLMUL_Fixup (instr_info *, int, int);
90 static bool VPCMP_Fixup (instr_info *, int, int);
91 static bool VPCOM_Fixup (instr_info *, int, int);
92 static bool NOP_Fixup (instr_info *, int, int);
93 static bool MONTMUL_Fixup (instr_info *, int, int);
94 static bool OP_3DNowSuffix (instr_info *, int, int);
95 static bool CMP_Fixup (instr_info *, int, int);
96 static bool REP_Fixup (instr_info *, int, int);
97 static bool SEP_Fixup (instr_info *, int, int);
98 static bool BND_Fixup (instr_info *, int, int);
99 static bool NOTRACK_Fixup (instr_info *, int, int);
100 static bool HLE_Fixup1 (instr_info *, int, int);
101 static bool HLE_Fixup2 (instr_info *, int, int);
102 static bool HLE_Fixup3 (instr_info *, int, int);
103 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
104 static bool XMM_Fixup (instr_info *, int, int);
105 static bool FXSAVE_Fixup (instr_info *, int, int);
106 static bool MOVSXD_Fixup (instr_info *, int, int);
107 static bool DistinctDest_Fixup (instr_info *, int, int);
108 static bool PREFETCHI_Fixup (instr_info *, int, int);
109 static bool PUSH2_POP2_Fixup (instr_info *, int, int);
110 static bool JMPABS_Fixup (instr_info *, int, int);
111 static bool CFCMOV_Fixup (instr_info *, int, int);
112
113 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
114 enum disassembler_style,
115 const char *, ...);
116
117 /* This character is used to encode style information within the output
118 buffers. See oappend_insert_style for more details. */
119 #define STYLE_MARKER_CHAR '\002'
120
121 /* The maximum operand buffer size. */
122 #define MAX_OPERAND_BUFFER_SIZE 128
123
124 enum address_mode
125 {
126 mode_16bit,
127 mode_32bit,
128 mode_64bit
129 };
130
131 static const char *prefix_name (enum address_mode, uint8_t, int);
132
133 enum x86_64_isa
134 {
135 amd64 = 1,
136 intel64
137 };
138
139 enum evex_type
140 {
141 evex_default = 0,
142 evex_from_legacy,
143 evex_from_vex,
144 };
145
146 struct instr_info
147 {
148 enum address_mode address_mode;
149
150 /* Flags for the prefixes for the current instruction. See below. */
151 int prefixes;
152
153 /* REX prefix the current instruction. See below. */
154 uint8_t rex;
155 /* Bits of REX we've already used. */
156 uint8_t rex_used;
157
158 /* Record W R4 X4 B4 bits for rex2. */
159 unsigned char rex2;
160 /* Bits of rex2 we've already used. */
161 unsigned char rex2_used;
162 unsigned char rex2_payload;
163
164 bool need_modrm;
165 unsigned char condition_code;
166 unsigned char need_vex;
167 bool has_sib;
168
169 /* Flags for ins->prefixes which we somehow handled when printing the
170 current instruction. */
171 int used_prefixes;
172
173 /* Flags for EVEX bits which we somehow handled when printing the
174 current instruction. */
175 int evex_used;
176
177 char obuf[MAX_OPERAND_BUFFER_SIZE];
178 char *obufp;
179 char *mnemonicendp;
180 const uint8_t *start_codep;
181 uint8_t *codep;
182 const uint8_t *end_codep;
183 unsigned char nr_prefixes;
184 signed char last_lock_prefix;
185 signed char last_repz_prefix;
186 signed char last_repnz_prefix;
187 signed char last_data_prefix;
188 signed char last_addr_prefix;
189 signed char last_rex_prefix;
190 signed char last_rex2_prefix;
191 signed char last_seg_prefix;
192 signed char fwait_prefix;
193 /* The active segment register prefix. */
194 unsigned char active_seg_prefix;
195
196 #define MAX_CODE_LENGTH 15
197 /* We can up to 14 ins->prefixes since the maximum instruction length is
198 15bytes. */
199 uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
200 disassemble_info *info;
201
202 struct
203 {
204 int mod;
205 int reg;
206 int rm;
207 }
208 modrm;
209
210 struct
211 {
212 int scale;
213 int index;
214 int base;
215 }
216 sib;
217
218 struct
219 {
220 int register_specifier;
221 int length;
222 int prefix;
223 int mask_register_specifier;
224 int scc;
225 int ll;
226 bool w;
227 bool evex;
228 bool v;
229 bool zeroing;
230 bool b;
231 bool no_broadcast;
232 bool nf;
233 bool u;
234 }
235 vex;
236
237 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */
238 #define nd b
239
240 enum evex_type evex_type;
241
242 /* Remember if the current op is a jump instruction. */
243 bool op_is_jump;
244
245 bool two_source_ops;
246
247 /* Record whether EVEX masking is used incorrectly. */
248 bool illegal_masking;
249
250 /* Record whether the modrm byte has been skipped. */
251 bool has_skipped_modrm;
252
253 unsigned char op_ad;
254 signed char op_index[MAX_OPERANDS];
255 bool op_riprel[MAX_OPERANDS];
256 char *op_out[MAX_OPERANDS];
257 bfd_vma op_address[MAX_OPERANDS];
258 bfd_vma start_pc;
259
260 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
261 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
262 * section of the "Virtual 8086 Mode" chapter.)
263 * 'pc' should be the address of this instruction, it will
264 * be used to print the target address if this is a relative jump or call
265 * The function returns the length of this instruction in bytes.
266 */
267 char intel_syntax;
268 bool intel_mnemonic;
269 char open_char;
270 char close_char;
271 char separator_char;
272 char scale_char;
273
274 enum x86_64_isa isa64;
275 };
276
277 struct dis_private {
278 bfd_vma insn_start;
279 int orig_sizeflag;
280
281 /* Indexes first byte not fetched. */
282 unsigned int fetched;
283 uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
284 };
285
286 /* Mark parts used in the REX prefix. When we are testing for
287 empty prefix (for 8bit register REX extension), just mask it
288 out. Otherwise test for REX bit is excuse for existence of REX
289 only in case value is nonzero. */
290 #define USED_REX(value) \
291 { \
292 if (value) \
293 { \
294 if (ins->rex & value) \
295 ins->rex_used |= (value) | REX_OPCODE; \
296 if (ins->rex2 & value) \
297 { \
298 ins->rex2_used |= (value); \
299 ins->rex_used |= REX_OPCODE; \
300 } \
301 } \
302 else \
303 ins->rex_used |= REX_OPCODE; \
304 }
305
306
307 #define EVEX_b_used 1
308 #define EVEX_len_used 2
309
310
311 /* {rex2} is not printed when the REX2_SPECIAL is set. */
312 #define REX2_SPECIAL 16
313
314 /* Flags stored in PREFIXES. */
315 #define PREFIX_REPZ 1
316 #define PREFIX_REPNZ 2
317 #define PREFIX_CS 4
318 #define PREFIX_SS 8
319 #define PREFIX_DS 0x10
320 #define PREFIX_ES 0x20
321 #define PREFIX_FS 0x40
322 #define PREFIX_GS 0x80
323 #define PREFIX_LOCK 0x100
324 #define PREFIX_DATA 0x200
325 #define PREFIX_ADDR 0x400
326 #define PREFIX_FWAIT 0x800
327 #define PREFIX_REX2 0x1000
328 #define PREFIX_NP_OR_DATA 0x2000
329 #define NO_PREFIX 0x4000
330
331 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
332 to ADDR (exclusive) are valid. Returns true for success, false
333 on error. */
334 static bool
335 fetch_code (struct disassemble_info *info, const uint8_t *until)
336 {
337 int status = -1;
338 struct dis_private *priv = info->private_data;
339 bfd_vma start = priv->insn_start + priv->fetched;
340 uint8_t *fetch_end = priv->the_buffer + priv->fetched;
341 ptrdiff_t needed = until - fetch_end;
342
343 if (needed <= 0)
344 return true;
345
346 if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
347 status = (*info->read_memory_func) (start, fetch_end, needed, info);
348 if (status != 0)
349 {
350 /* If we did manage to read at least one byte, then
351 print_insn_i386 will do something sensible. Otherwise, print
352 an error. We do that here because this is where we know
353 STATUS. */
354 if (!priv->fetched)
355 (*info->memory_error_func) (status, start, info);
356 return false;
357 }
358
359 priv->fetched += needed;
360 return true;
361 }
362
363 static bool
364 fetch_modrm (instr_info *ins)
365 {
366 if (!fetch_code (ins->info, ins->codep + 1))
367 return false;
368
369 ins->modrm.mod = (*ins->codep >> 6) & 3;
370 ins->modrm.reg = (*ins->codep >> 3) & 7;
371 ins->modrm.rm = *ins->codep & 7;
372
373 return true;
374 }
375
376 static int
377 fetch_error (const instr_info *ins)
378 {
379 /* Getting here means we tried for data but didn't get it. That
380 means we have an incomplete instruction of some sort. Just
381 print the first byte as a prefix or a .byte pseudo-op. */
382 const struct dis_private *priv = ins->info->private_data;
383 const char *name = NULL;
384
385 if (ins->codep <= priv->the_buffer)
386 return -1;
387
388 if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
389 name = prefix_name (ins->address_mode, priv->the_buffer[0],
390 priv->orig_sizeflag);
391 if (name != NULL)
392 i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
393 else
394 {
395 /* Just print the first byte as a .byte instruction. */
396 i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
397 i386_dis_printf (ins->info, dis_style_immediate, "%#x",
398 (unsigned int) priv->the_buffer[0]);
399 }
400
401 return 1;
402 }
403
404 /* Possible values for prefix requirement. */
405 #define PREFIX_IGNORED_SHIFT 16
406 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
407 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
408 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
409 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
410 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
411 #define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
412
413 /* Opcode prefixes. */
414 #define PREFIX_OPCODE (PREFIX_REPZ \
415 | PREFIX_REPNZ \
416 | PREFIX_DATA)
417
418 /* Prefixes ignored. */
419 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
420 | PREFIX_IGNORED_REPNZ \
421 | PREFIX_IGNORED_DATA)
422
423 #define XX { NULL, 0 }
424 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
425
426 #define Eb { OP_E, b_mode }
427 #define Ebnd { OP_E, bnd_mode }
428 #define EbS { OP_E, b_swap_mode }
429 #define EbndS { OP_E, bnd_swap_mode }
430 #define Ev { OP_E, v_mode }
431 #define Eva { OP_E, va_mode }
432 #define Ev_bnd { OP_E, v_bnd_mode }
433 #define EvS { OP_E, v_swap_mode }
434 #define Ed { OP_E, d_mode }
435 #define Edq { OP_E, dq_mode }
436 #define Edb { OP_E, db_mode }
437 #define Edw { OP_E, dw_mode }
438 #define Eq { OP_E, q_mode }
439 #define indirEv { OP_indirE, indir_v_mode }
440 #define indirEp { OP_indirE, f_mode }
441 #define stackEv { OP_E, stack_v_mode }
442 #define Em { OP_E, m_mode }
443 #define Ew { OP_E, w_mode }
444 #define M { OP_M, 0 } /* lea, lgdt, etc. */
445 #define Ma { OP_M, a_mode }
446 #define Mb { OP_M, b_mode }
447 #define Md { OP_M, d_mode }
448 #define Mdq { OP_M, dq_mode }
449 #define Mo { OP_M, o_mode }
450 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
451 #define Mq { OP_M, q_mode }
452 #define Mv { OP_M, v_mode }
453 #define Mv_bnd { OP_M, v_bndmk_mode }
454 #define Mw { OP_M, w_mode }
455 #define Mx { OP_M, x_mode }
456 #define Mxmm { OP_M, xmm_mode }
457 #define Mymm { OP_M, ymm_mode }
458 #define Gb { OP_G, b_mode }
459 #define Gbnd { OP_G, bnd_mode }
460 #define Gv { OP_G, v_mode }
461 #define Gd { OP_G, d_mode }
462 #define Gdq { OP_G, dq_mode }
463 #define Gq { OP_G, q_mode }
464 #define Gm { OP_G, m_mode }
465 #define Gva { OP_G, va_mode }
466 #define Gw { OP_G, w_mode }
467 #define Ib { OP_I, b_mode }
468 #define sIb { OP_sI, b_mode } /* sign extened byte */
469 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
470 #define Iv { OP_I, v_mode }
471 #define sIv { OP_sI, v_mode }
472 #define Iv64 { OP_I64, v_mode }
473 #define Id { OP_I, d_mode }
474 #define Iw { OP_I, w_mode }
475 #define I1 { OP_I, const_1_mode }
476 #define Jb { OP_J, b_mode }
477 #define Jv { OP_J, v_mode }
478 #define Jdqw { OP_J, dqw_mode }
479 #define Cm { OP_C, m_mode }
480 #define Dm { OP_D, m_mode }
481 #define Td { OP_T, d_mode }
482 #define Skip_MODRM { OP_Skip_MODRM, 0 }
483
484 #define RMeAX { OP_REG, eAX_reg }
485 #define RMeBX { OP_REG, eBX_reg }
486 #define RMeCX { OP_REG, eCX_reg }
487 #define RMeDX { OP_REG, eDX_reg }
488 #define RMeSP { OP_REG, eSP_reg }
489 #define RMeBP { OP_REG, eBP_reg }
490 #define RMeSI { OP_REG, eSI_reg }
491 #define RMeDI { OP_REG, eDI_reg }
492 #define RMrAX { OP_REG, rAX_reg }
493 #define RMrBX { OP_REG, rBX_reg }
494 #define RMrCX { OP_REG, rCX_reg }
495 #define RMrDX { OP_REG, rDX_reg }
496 #define RMrSP { OP_REG, rSP_reg }
497 #define RMrBP { OP_REG, rBP_reg }
498 #define RMrSI { OP_REG, rSI_reg }
499 #define RMrDI { OP_REG, rDI_reg }
500 #define RMAL { OP_REG, al_reg }
501 #define RMCL { OP_REG, cl_reg }
502 #define RMDL { OP_REG, dl_reg }
503 #define RMBL { OP_REG, bl_reg }
504 #define RMAH { OP_REG, ah_reg }
505 #define RMCH { OP_REG, ch_reg }
506 #define RMDH { OP_REG, dh_reg }
507 #define RMBH { OP_REG, bh_reg }
508 #define RMAX { OP_REG, ax_reg }
509 #define RMDX { OP_REG, dx_reg }
510
511 #define eAX { OP_IMREG, eAX_reg }
512 #define AL { OP_IMREG, al_reg }
513 #define CL { OP_IMREG, cl_reg }
514 #define zAX { OP_IMREG, z_mode_ax_reg }
515 #define indirDX { OP_IMREG, indir_dx_reg }
516
517 #define Sw { OP_SEG, w_mode }
518 #define Sv { OP_SEG, v_mode }
519 #define Ap { OP_DIR, 0 }
520 #define Ob { OP_OFF64, b_mode }
521 #define Ov { OP_OFF64, v_mode }
522 #define Xb { OP_DSreg, eSI_reg }
523 #define Xv { OP_DSreg, eSI_reg }
524 #define Xz { OP_DSreg, eSI_reg }
525 #define Yb { OP_ESreg, eDI_reg }
526 #define Yv { OP_ESreg, eDI_reg }
527 #define DSBX { OP_DSreg, eBX_reg }
528
529 #define es { OP_REG, es_reg }
530 #define ss { OP_REG, ss_reg }
531 #define cs { OP_REG, cs_reg }
532 #define ds { OP_REG, ds_reg }
533 #define fs { OP_REG, fs_reg }
534 #define gs { OP_REG, gs_reg }
535
536 #define MX { OP_MMX, 0 }
537 #define XM { OP_XMM, 0 }
538 #define XMScalar { OP_XMM, scalar_mode }
539 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
540 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
541 #define XMM { OP_XMM, xmm_mode }
542 #define TMM { OP_XMM, tmm_mode }
543 #define XMxmmq { OP_XMM, xmmq_mode }
544 #define EM { OP_EM, v_mode }
545 #define EMS { OP_EM, v_swap_mode }
546 #define EMd { OP_EM, d_mode }
547 #define EMx { OP_EM, x_mode }
548 #define EXbwUnit { OP_EX, bw_unit_mode }
549 #define EXb { OP_EX, b_mode }
550 #define EXw { OP_EX, w_mode }
551 #define EXd { OP_EX, d_mode }
552 #define EXdS { OP_EX, d_swap_mode }
553 #define EXwS { OP_EX, w_swap_mode }
554 #define EXq { OP_EX, q_mode }
555 #define EXqS { OP_EX, q_swap_mode }
556 #define EXdq { OP_EX, dq_mode }
557 #define EXx { OP_EX, x_mode }
558 #define EXxh { OP_EX, xh_mode }
559 #define EXxS { OP_EX, x_swap_mode }
560 #define EXxmm { OP_EX, xmm_mode }
561 #define EXymm { OP_EX, ymm_mode }
562 #define EXxmmq { OP_EX, xmmq_mode }
563 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
564 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
565 #define EXxmmdw { OP_EX, xmmdw_mode }
566 #define EXxmmqd { OP_EX, xmmqd_mode }
567 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
568 #define EXymmq { OP_EX, ymmq_mode }
569 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
570 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
571 #define Rd { OP_R, d_mode }
572 #define Rdq { OP_R, dq_mode }
573 #define Rq { OP_R, q_mode }
574 #define Nq { OP_R, q_mm_mode }
575 #define Ux { OP_R, x_mode }
576 #define Uxmm { OP_R, xmm_mode }
577 #define Rxmmq { OP_R, xmmq_mode }
578 #define Rymm { OP_R, ymm_mode }
579 #define Rtmm { OP_R, tmm_mode }
580 #define EMCq { OP_EMC, q_mode }
581 #define MXC { OP_MXC, 0 }
582 #define OPSUF { OP_3DNowSuffix, 0 }
583 #define SEP { SEP_Fixup, 0 }
584 #define CMP { CMP_Fixup, 0 }
585 #define XMM0 { XMM_Fixup, 0 }
586 #define FXSAVE { FXSAVE_Fixup, 0 }
587
588 #define Vex { OP_VEX, x_mode }
589 #define VexW { OP_VexW, x_mode }
590 #define VexScalar { OP_VEX, scalar_mode }
591 #define VexScalarR { OP_VexR, scalar_mode }
592 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
593 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
594 #define VexGdq { OP_VEX, dq_mode }
595 #define VexGb { OP_VEX, b_mode }
596 #define VexGv { OP_VEX, v_mode }
597 #define VexTmm { OP_VEX, tmm_mode }
598 #define XMVexI4 { OP_REG_VexI4, x_mode }
599 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
600 #define VexI4 { OP_VexI4, 0 }
601 #define PCLMUL { PCLMUL_Fixup, 0 }
602 #define VPCMP { VPCMP_Fixup, 0 }
603 #define VPCOM { VPCOM_Fixup, 0 }
604
605 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
606 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
607 #define EXxEVexS { OP_Rounding, evex_sae_mode }
608
609 #define MaskG { OP_G, mask_mode }
610 #define MaskE { OP_E, mask_mode }
611 #define MaskR { OP_R, mask_mode }
612 #define MaskBDE { OP_E, mask_bd_mode }
613 #define MaskVex { OP_VEX, mask_mode }
614
615 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
616 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
617
618 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
619
620 /* Used handle "rep" prefix for string instructions. */
621 #define Xbr { REP_Fixup, eSI_reg }
622 #define Xvr { REP_Fixup, eSI_reg }
623 #define Ybr { REP_Fixup, eDI_reg }
624 #define Yvr { REP_Fixup, eDI_reg }
625 #define Yzr { REP_Fixup, eDI_reg }
626 #define indirDXr { REP_Fixup, indir_dx_reg }
627 #define ALr { REP_Fixup, al_reg }
628 #define eAXr { REP_Fixup, eAX_reg }
629
630 /* Used handle HLE prefix for lockable instructions. */
631 #define Ebh1 { HLE_Fixup1, b_mode }
632 #define Evh1 { HLE_Fixup1, v_mode }
633 #define Ebh2 { HLE_Fixup2, b_mode }
634 #define Evh2 { HLE_Fixup2, v_mode }
635 #define Ebh3 { HLE_Fixup3, b_mode }
636 #define Evh3 { HLE_Fixup3, v_mode }
637
638 #define BND { BND_Fixup, 0 }
639 #define NOTRACK { NOTRACK_Fixup, 0 }
640
641 #define cond_jump_flag { NULL, cond_jump_mode }
642 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
643
644 /* bits in sizeflag */
645 #define SUFFIX_ALWAYS 4
646 #define AFLAG 2
647 #define DFLAG 1
648
649 enum
650 {
651 /* byte operand */
652 b_mode = 1,
653 /* byte operand with operand swapped */
654 b_swap_mode,
655 /* byte operand, sign extend like 'T' suffix */
656 b_T_mode,
657 /* operand size depends on prefixes */
658 v_mode,
659 /* operand size depends on prefixes with operand swapped */
660 v_swap_mode,
661 /* operand size depends on address prefix */
662 va_mode,
663 /* word operand */
664 w_mode,
665 /* double word operand */
666 d_mode,
667 /* word operand with operand swapped */
668 w_swap_mode,
669 /* double word operand with operand swapped */
670 d_swap_mode,
671 /* quad word operand */
672 q_mode,
673 /* 8-byte MM operand */
674 q_mm_mode,
675 /* quad word operand with operand swapped */
676 q_swap_mode,
677 /* ten-byte operand */
678 t_mode,
679 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
680 broadcast enabled. */
681 x_mode,
682 /* Similar to x_mode, but with different EVEX mem shifts. */
683 evex_x_gscat_mode,
684 /* Similar to x_mode, but with yet different EVEX mem shifts. */
685 bw_unit_mode,
686 /* Similar to x_mode, but with disabled broadcast. */
687 evex_x_nobcst_mode,
688 /* Similar to x_mode, but with operands swapped and disabled broadcast
689 in EVEX. */
690 x_swap_mode,
691 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
692 broadcast of 16bit enabled. */
693 xh_mode,
694 /* 16-byte XMM operand */
695 xmm_mode,
696 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
697 memory operand (depending on vector length). Broadcast isn't
698 allowed. */
699 xmmq_mode,
700 /* Same as xmmq_mode, but broadcast is allowed. */
701 evex_half_bcst_xmmq_mode,
702 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
703 memory operand (depending on vector length). 16bit broadcast. */
704 evex_half_bcst_xmmqh_mode,
705 /* 16-byte XMM, word, double word or quad word operand. */
706 xmmdw_mode,
707 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
708 xmmqd_mode,
709 /* 16-byte XMM, double word, quad word operand or xmm word operand.
710 16bit broadcast. */
711 evex_half_bcst_xmmqdh_mode,
712 /* 32-byte YMM operand */
713 ymm_mode,
714 /* quad word, ymmword or zmmword memory operand. */
715 ymmq_mode,
716 /* TMM operand */
717 tmm_mode,
718 /* d_mode in 32bit, q_mode in 64bit mode. */
719 m_mode,
720 /* pair of v_mode operands */
721 a_mode,
722 cond_jump_mode,
723 loop_jcxz_mode,
724 movsxd_mode,
725 v_bnd_mode,
726 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
727 v_bndmk_mode,
728 /* operand size depends on REX.W / VEX.W. */
729 dq_mode,
730 /* Displacements like v_mode without considering Intel64 ISA. */
731 dqw_mode,
732 /* bounds operand */
733 bnd_mode,
734 /* bounds operand with operand swapped */
735 bnd_swap_mode,
736 /* 4- or 6-byte pointer operand */
737 f_mode,
738 const_1_mode,
739 /* v_mode for indirect branch opcodes. */
740 indir_v_mode,
741 /* v_mode for stack-related opcodes. */
742 stack_v_mode,
743 /* non-quad operand size depends on prefixes */
744 z_mode,
745 /* 16-byte operand */
746 o_mode,
747 /* registers like d_mode, memory like b_mode. */
748 db_mode,
749 /* registers like d_mode, memory like w_mode. */
750 dw_mode,
751
752 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
753 vex_vsib_d_w_dq_mode,
754 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
755 vex_vsib_q_w_dq_mode,
756 /* mandatory non-vector SIB. */
757 vex_sibmem_mode,
758
759 /* scalar, ignore vector length. */
760 scalar_mode,
761
762 /* Static rounding. */
763 evex_rounding_mode,
764 /* Static rounding, 64-bit mode only. */
765 evex_rounding_64_mode,
766 /* Supress all exceptions. */
767 evex_sae_mode,
768
769 /* Mask register operand. */
770 mask_mode,
771 /* Mask register operand. */
772 mask_bd_mode,
773
774 es_reg,
775 cs_reg,
776 ss_reg,
777 ds_reg,
778 fs_reg,
779 gs_reg,
780
781 eAX_reg,
782 eCX_reg,
783 eDX_reg,
784 eBX_reg,
785 eSP_reg,
786 eBP_reg,
787 eSI_reg,
788 eDI_reg,
789
790 al_reg,
791 cl_reg,
792 dl_reg,
793 bl_reg,
794 ah_reg,
795 ch_reg,
796 dh_reg,
797 bh_reg,
798
799 ax_reg,
800 cx_reg,
801 dx_reg,
802 bx_reg,
803 sp_reg,
804 bp_reg,
805 si_reg,
806 di_reg,
807
808 rAX_reg,
809 rCX_reg,
810 rDX_reg,
811 rBX_reg,
812 rSP_reg,
813 rBP_reg,
814 rSI_reg,
815 rDI_reg,
816
817 z_mode_ax_reg,
818 indir_dx_reg
819 };
820
821 enum
822 {
823 FLOATCODE = 1,
824 USE_REG_TABLE,
825 USE_MOD_TABLE,
826 USE_RM_TABLE,
827 USE_PREFIX_TABLE,
828 USE_X86_64_TABLE,
829 USE_X86_64_EVEX_FROM_VEX_TABLE,
830 USE_X86_64_EVEX_PFX_TABLE,
831 USE_X86_64_EVEX_W_TABLE,
832 USE_X86_64_EVEX_MEM_W_TABLE,
833 USE_3BYTE_TABLE,
834 USE_XOP_8F_TABLE,
835 USE_VEX_C4_TABLE,
836 USE_VEX_C5_TABLE,
837 USE_VEX_LEN_TABLE,
838 USE_VEX_W_TABLE,
839 USE_EVEX_TABLE,
840 USE_EVEX_LEN_TABLE
841 };
842
843 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
844
845 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
846 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
847 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
848 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
849 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
850 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
851 #define X86_64_EVEX_FROM_VEX_TABLE(I) \
852 DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
853 #define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I))
854 #define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I))
855 #define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I))
856 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
857 #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0)
858 #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0)
859 #define VEX_C5_TABLE() DIS386 (USE_VEX_C5_TABLE, 0)
860 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
861 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
862 #define EVEX_TABLE() DIS386 (USE_EVEX_TABLE, 0)
863 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
864
865 enum
866 {
867 REG_80 = 0,
868 REG_81,
869 REG_83,
870 REG_8F,
871 REG_C0,
872 REG_C1,
873 REG_C6,
874 REG_C7,
875 REG_D0,
876 REG_D1,
877 REG_D2,
878 REG_D3,
879 REG_F6,
880 REG_F7,
881 REG_FE,
882 REG_FF,
883 REG_0F00,
884 REG_0F01,
885 REG_0F0D,
886 REG_0F18,
887 REG_0F1C_P_0_MOD_0,
888 REG_0F1E_P_1_MOD_3,
889 REG_0F38D8_PREFIX_1,
890 REG_0F3A0F_P_1,
891 REG_0F71,
892 REG_0F72,
893 REG_0F73,
894 REG_0FA6,
895 REG_0FA7,
896 REG_0FAE,
897 REG_0FBA,
898 REG_0FC7,
899 REG_VEX_0F71,
900 REG_VEX_0F72,
901 REG_VEX_0F73,
902 REG_VEX_0FAE,
903 REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
904 REG_VEX_0F38F3_L_0_P_0,
905 REG_VEX_MAP7_F6_L_0_W_0,
906 REG_VEX_MAP7_F8_L_0_W_0,
907
908 REG_XOP_09_01_L_0,
909 REG_XOP_09_02_L_0,
910 REG_XOP_09_12_L_0,
911 REG_XOP_0A_12_L_0,
912
913 REG_EVEX_0F71,
914 REG_EVEX_0F72,
915 REG_EVEX_0F73,
916 REG_EVEX_0F38C6_L_2,
917 REG_EVEX_0F38C7_L_2,
918 REG_EVEX_MAP4_80,
919 REG_EVEX_MAP4_81,
920 REG_EVEX_MAP4_83,
921 REG_EVEX_MAP4_8F,
922 REG_EVEX_MAP4_F6,
923 REG_EVEX_MAP4_F7,
924 REG_EVEX_MAP4_FE,
925 REG_EVEX_MAP4_FF,
926 };
927
928 enum
929 {
930 MOD_62_32BIT = 0,
931 MOD_C4_32BIT,
932 MOD_C5_32BIT,
933 MOD_0F01_REG_0,
934 MOD_0F01_REG_1,
935 MOD_0F01_REG_2,
936 MOD_0F01_REG_3,
937 MOD_0F01_REG_5,
938 MOD_0F01_REG_7,
939 MOD_0F12_PREFIX_0,
940 MOD_0F16_PREFIX_0,
941 MOD_0F18_REG_0,
942 MOD_0F18_REG_1,
943 MOD_0F18_REG_2,
944 MOD_0F18_REG_3,
945 MOD_0F18_REG_6,
946 MOD_0F18_REG_7,
947 MOD_0F1A_PREFIX_0,
948 MOD_0F1B_PREFIX_0,
949 MOD_0F1B_PREFIX_1,
950 MOD_0F1C_PREFIX_0,
951 MOD_0F1E_PREFIX_1,
952 MOD_0FAE_REG_0,
953 MOD_0FAE_REG_1,
954 MOD_0FAE_REG_2,
955 MOD_0FAE_REG_3,
956 MOD_0FAE_REG_4,
957 MOD_0FAE_REG_5,
958 MOD_0FAE_REG_6,
959 MOD_0FAE_REG_7,
960 MOD_0FC7_REG_6,
961 MOD_0FC7_REG_7,
962 MOD_0F38DC_PREFIX_1,
963 MOD_0F38F8,
964
965 MOD_VEX_0F3849_X86_64_L_0_W_0,
966
967 MOD_EVEX_MAP4_60,
968 MOD_EVEX_MAP4_61,
969 MOD_EVEX_MAP4_F8_P_1,
970 MOD_EVEX_MAP4_F8_P_3,
971 };
972
973 enum
974 {
975 RM_C6_REG_7 = 0,
976 RM_C7_REG_7,
977 RM_0F01_REG_0,
978 RM_0F01_REG_1,
979 RM_0F01_REG_2,
980 RM_0F01_REG_3,
981 RM_0F01_REG_5_MOD_3,
982 RM_0F01_REG_7_MOD_3,
983 RM_0F1E_P_1_MOD_3_REG_7,
984 RM_0FAE_REG_6_MOD_3_P_0,
985 RM_0FAE_REG_7_MOD_3,
986 RM_0F3A0F_P_1_R_0,
987
988 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
989 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
990 };
991
992 enum
993 {
994 PREFIX_90 = 0,
995 PREFIX_0F00_REG_6_X86_64,
996 PREFIX_0F01_REG_0_MOD_3_RM_6,
997 PREFIX_0F01_REG_0_MOD_3_RM_7,
998 PREFIX_0F01_REG_1_RM_2,
999 PREFIX_0F01_REG_1_RM_4,
1000 PREFIX_0F01_REG_1_RM_5,
1001 PREFIX_0F01_REG_1_RM_6,
1002 PREFIX_0F01_REG_1_RM_7,
1003 PREFIX_0F01_REG_3_RM_1,
1004 PREFIX_0F01_REG_5_MOD_0,
1005 PREFIX_0F01_REG_5_MOD_3_RM_0,
1006 PREFIX_0F01_REG_5_MOD_3_RM_1,
1007 PREFIX_0F01_REG_5_MOD_3_RM_2,
1008 PREFIX_0F01_REG_5_MOD_3_RM_4,
1009 PREFIX_0F01_REG_5_MOD_3_RM_5,
1010 PREFIX_0F01_REG_5_MOD_3_RM_6,
1011 PREFIX_0F01_REG_5_MOD_3_RM_7,
1012 PREFIX_0F01_REG_7_MOD_3_RM_2,
1013 PREFIX_0F01_REG_7_MOD_3_RM_5,
1014 PREFIX_0F01_REG_7_MOD_3_RM_6,
1015 PREFIX_0F01_REG_7_MOD_3_RM_7,
1016 PREFIX_0F09,
1017 PREFIX_0F10,
1018 PREFIX_0F11,
1019 PREFIX_0F12,
1020 PREFIX_0F16,
1021 PREFIX_0F18_REG_6_MOD_0_X86_64,
1022 PREFIX_0F18_REG_7_MOD_0_X86_64,
1023 PREFIX_0F1A,
1024 PREFIX_0F1B,
1025 PREFIX_0F1C,
1026 PREFIX_0F1E,
1027 PREFIX_0F2A,
1028 PREFIX_0F2B,
1029 PREFIX_0F2C,
1030 PREFIX_0F2D,
1031 PREFIX_0F2E,
1032 PREFIX_0F2F,
1033 PREFIX_0F51,
1034 PREFIX_0F52,
1035 PREFIX_0F53,
1036 PREFIX_0F58,
1037 PREFIX_0F59,
1038 PREFIX_0F5A,
1039 PREFIX_0F5B,
1040 PREFIX_0F5C,
1041 PREFIX_0F5D,
1042 PREFIX_0F5E,
1043 PREFIX_0F5F,
1044 PREFIX_0F60,
1045 PREFIX_0F61,
1046 PREFIX_0F62,
1047 PREFIX_0F6F,
1048 PREFIX_0F70,
1049 PREFIX_0F78,
1050 PREFIX_0F79,
1051 PREFIX_0F7C,
1052 PREFIX_0F7D,
1053 PREFIX_0F7E,
1054 PREFIX_0F7F,
1055 PREFIX_0FA6_REG_0,
1056 PREFIX_0FA6_REG_5,
1057 PREFIX_0FA7_REG_6,
1058 PREFIX_0FAE_REG_0_MOD_3,
1059 PREFIX_0FAE_REG_1_MOD_3,
1060 PREFIX_0FAE_REG_2_MOD_3,
1061 PREFIX_0FAE_REG_3_MOD_3,
1062 PREFIX_0FAE_REG_4_MOD_0,
1063 PREFIX_0FAE_REG_4_MOD_3,
1064 PREFIX_0FAE_REG_5_MOD_3,
1065 PREFIX_0FAE_REG_6_MOD_0,
1066 PREFIX_0FAE_REG_6_MOD_3,
1067 PREFIX_0FAE_REG_7_MOD_0,
1068 PREFIX_0FB8,
1069 PREFIX_0FBC,
1070 PREFIX_0FBD,
1071 PREFIX_0FC2,
1072 PREFIX_0FC7_REG_6_MOD_0,
1073 PREFIX_0FC7_REG_6_MOD_3,
1074 PREFIX_0FC7_REG_7_MOD_3,
1075 PREFIX_0FD0,
1076 PREFIX_0FD6,
1077 PREFIX_0FE6,
1078 PREFIX_0FE7,
1079 PREFIX_0FF0,
1080 PREFIX_0FF7,
1081 PREFIX_0F38D8,
1082 PREFIX_0F38DC,
1083 PREFIX_0F38DD,
1084 PREFIX_0F38DE,
1085 PREFIX_0F38DF,
1086 PREFIX_0F38F0,
1087 PREFIX_0F38F1,
1088 PREFIX_0F38F6,
1089 PREFIX_0F38F8_M_0,
1090 PREFIX_0F38F8_M_1_X86_64,
1091 PREFIX_0F38FA,
1092 PREFIX_0F38FB,
1093 PREFIX_0F38FC,
1094 PREFIX_0F3A0F,
1095 PREFIX_VEX_0F12,
1096 PREFIX_VEX_0F16,
1097 PREFIX_VEX_0F2A,
1098 PREFIX_VEX_0F2C,
1099 PREFIX_VEX_0F2D,
1100 PREFIX_VEX_0F41_L_1_W_0,
1101 PREFIX_VEX_0F41_L_1_W_1,
1102 PREFIX_VEX_0F42_L_1_W_0,
1103 PREFIX_VEX_0F42_L_1_W_1,
1104 PREFIX_VEX_0F44_L_0_W_0,
1105 PREFIX_VEX_0F44_L_0_W_1,
1106 PREFIX_VEX_0F45_L_1_W_0,
1107 PREFIX_VEX_0F45_L_1_W_1,
1108 PREFIX_VEX_0F46_L_1_W_0,
1109 PREFIX_VEX_0F46_L_1_W_1,
1110 PREFIX_VEX_0F47_L_1_W_0,
1111 PREFIX_VEX_0F47_L_1_W_1,
1112 PREFIX_VEX_0F4A_L_1_W_0,
1113 PREFIX_VEX_0F4A_L_1_W_1,
1114 PREFIX_VEX_0F4B_L_1_W_0,
1115 PREFIX_VEX_0F4B_L_1_W_1,
1116 PREFIX_VEX_0F6F,
1117 PREFIX_VEX_0F70,
1118 PREFIX_VEX_0F7E,
1119 PREFIX_VEX_0F7F,
1120 PREFIX_VEX_0F90_L_0_W_0,
1121 PREFIX_VEX_0F90_L_0_W_1,
1122 PREFIX_VEX_0F91_L_0_W_0,
1123 PREFIX_VEX_0F91_L_0_W_1,
1124 PREFIX_VEX_0F92_L_0_W_0,
1125 PREFIX_VEX_0F92_L_0_W_1,
1126 PREFIX_VEX_0F93_L_0_W_0,
1127 PREFIX_VEX_0F93_L_0_W_1,
1128 PREFIX_VEX_0F98_L_0_W_0,
1129 PREFIX_VEX_0F98_L_0_W_1,
1130 PREFIX_VEX_0F99_L_0_W_0,
1131 PREFIX_VEX_0F99_L_0_W_1,
1132 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1133 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1134 PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1135 PREFIX_VEX_0F3850_W_0,
1136 PREFIX_VEX_0F3851_W_0,
1137 PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1138 PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1139 PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1140 PREFIX_VEX_0F3872,
1141 PREFIX_VEX_0F38B0_W_0,
1142 PREFIX_VEX_0F38B1_W_0,
1143 PREFIX_VEX_0F38D2_W_0,
1144 PREFIX_VEX_0F38D3_W_0,
1145 PREFIX_VEX_0F38CB,
1146 PREFIX_VEX_0F38CC,
1147 PREFIX_VEX_0F38CD,
1148 PREFIX_VEX_0F38DA_W_0,
1149 PREFIX_VEX_0F38F2_L_0,
1150 PREFIX_VEX_0F38F3_L_0,
1151 PREFIX_VEX_0F38F5_L_0,
1152 PREFIX_VEX_0F38F6_L_0,
1153 PREFIX_VEX_0F38F7_L_0,
1154 PREFIX_VEX_0F3AF0_L_0,
1155 PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64,
1156 PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1157
1158 PREFIX_EVEX_0F5B,
1159 PREFIX_EVEX_0F6F,
1160 PREFIX_EVEX_0F70,
1161 PREFIX_EVEX_0F78,
1162 PREFIX_EVEX_0F79,
1163 PREFIX_EVEX_0F7A,
1164 PREFIX_EVEX_0F7B,
1165 PREFIX_EVEX_0F7E,
1166 PREFIX_EVEX_0F7F,
1167 PREFIX_EVEX_0FC2,
1168 PREFIX_EVEX_0FE6,
1169 PREFIX_EVEX_0F3810,
1170 PREFIX_EVEX_0F3811,
1171 PREFIX_EVEX_0F3812,
1172 PREFIX_EVEX_0F3813,
1173 PREFIX_EVEX_0F3814,
1174 PREFIX_EVEX_0F3815,
1175 PREFIX_EVEX_0F3820,
1176 PREFIX_EVEX_0F3821,
1177 PREFIX_EVEX_0F3822,
1178 PREFIX_EVEX_0F3823,
1179 PREFIX_EVEX_0F3824,
1180 PREFIX_EVEX_0F3825,
1181 PREFIX_EVEX_0F3826,
1182 PREFIX_EVEX_0F3827,
1183 PREFIX_EVEX_0F3828,
1184 PREFIX_EVEX_0F3829,
1185 PREFIX_EVEX_0F382A,
1186 PREFIX_EVEX_0F3830,
1187 PREFIX_EVEX_0F3831,
1188 PREFIX_EVEX_0F3832,
1189 PREFIX_EVEX_0F3833,
1190 PREFIX_EVEX_0F3834,
1191 PREFIX_EVEX_0F3835,
1192 PREFIX_EVEX_0F3838,
1193 PREFIX_EVEX_0F3839,
1194 PREFIX_EVEX_0F383A,
1195 PREFIX_EVEX_0F3852,
1196 PREFIX_EVEX_0F3853,
1197 PREFIX_EVEX_0F3868,
1198 PREFIX_EVEX_0F3872,
1199 PREFIX_EVEX_0F3874,
1200 PREFIX_EVEX_0F389A,
1201 PREFIX_EVEX_0F389B,
1202 PREFIX_EVEX_0F38AA,
1203 PREFIX_EVEX_0F38AB,
1204
1205 PREFIX_EVEX_0F3A08,
1206 PREFIX_EVEX_0F3A0A,
1207 PREFIX_EVEX_0F3A26,
1208 PREFIX_EVEX_0F3A27,
1209 PREFIX_EVEX_0F3A42_W_0,
1210 PREFIX_EVEX_0F3A56,
1211 PREFIX_EVEX_0F3A57,
1212 PREFIX_EVEX_0F3A66,
1213 PREFIX_EVEX_0F3A67,
1214 PREFIX_EVEX_0F3AC2,
1215
1216 PREFIX_EVEX_MAP4_4x,
1217 PREFIX_EVEX_MAP4_F0,
1218 PREFIX_EVEX_MAP4_F1,
1219 PREFIX_EVEX_MAP4_F2,
1220 PREFIX_EVEX_MAP4_F8,
1221
1222 PREFIX_EVEX_MAP5_10,
1223 PREFIX_EVEX_MAP5_11,
1224 PREFIX_EVEX_MAP5_18,
1225 PREFIX_EVEX_MAP5_1B,
1226 PREFIX_EVEX_MAP5_1D,
1227 PREFIX_EVEX_MAP5_1E,
1228 PREFIX_EVEX_MAP5_2A,
1229 PREFIX_EVEX_MAP5_2C,
1230 PREFIX_EVEX_MAP5_2D,
1231 PREFIX_EVEX_MAP5_2E,
1232 PREFIX_EVEX_MAP5_2F,
1233 PREFIX_EVEX_MAP5_51,
1234 PREFIX_EVEX_MAP5_58,
1235 PREFIX_EVEX_MAP5_59,
1236 PREFIX_EVEX_MAP5_5A,
1237 PREFIX_EVEX_MAP5_5B,
1238 PREFIX_EVEX_MAP5_5C,
1239 PREFIX_EVEX_MAP5_5D,
1240 PREFIX_EVEX_MAP5_5E,
1241 PREFIX_EVEX_MAP5_5F,
1242 PREFIX_EVEX_MAP5_74,
1243 PREFIX_EVEX_MAP5_78,
1244 PREFIX_EVEX_MAP5_79,
1245 PREFIX_EVEX_MAP5_7A,
1246 PREFIX_EVEX_MAP5_7B,
1247 PREFIX_EVEX_MAP5_7C,
1248 PREFIX_EVEX_MAP5_7D,
1249
1250 PREFIX_EVEX_MAP6_13,
1251 PREFIX_EVEX_MAP6_56,
1252 PREFIX_EVEX_MAP6_57,
1253 PREFIX_EVEX_MAP6_D6,
1254 PREFIX_EVEX_MAP6_D7,
1255 };
1256
1257 enum
1258 {
1259 X86_64_06 = 0,
1260 X86_64_07,
1261 X86_64_0E,
1262 X86_64_16,
1263 X86_64_17,
1264 X86_64_1E,
1265 X86_64_1F,
1266 X86_64_27,
1267 X86_64_2F,
1268 X86_64_37,
1269 X86_64_3F,
1270 X86_64_60,
1271 X86_64_61,
1272 X86_64_62,
1273 X86_64_63,
1274 X86_64_6D,
1275 X86_64_6F,
1276 X86_64_82,
1277 X86_64_9A,
1278 X86_64_C2,
1279 X86_64_C3,
1280 X86_64_C4,
1281 X86_64_C5,
1282 X86_64_CE,
1283 X86_64_D4,
1284 X86_64_D5,
1285 X86_64_E8,
1286 X86_64_E9,
1287 X86_64_EA,
1288 X86_64_0F00_REG_6,
1289 X86_64_0F01_REG_0,
1290 X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1291 X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1292 X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1293 X86_64_0F01_REG_1,
1294 X86_64_0F01_REG_1_RM_2_PREFIX_1,
1295 X86_64_0F01_REG_1_RM_2_PREFIX_3,
1296 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1297 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1298 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1299 X86_64_0F01_REG_2,
1300 X86_64_0F01_REG_3,
1301 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1302 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1303 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1304 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1305 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1306 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1307 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1308 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1309 X86_64_0F18_REG_6_MOD_0,
1310 X86_64_0F18_REG_7_MOD_0,
1311 X86_64_0F24,
1312 X86_64_0F26,
1313 X86_64_0F38F8_M_1,
1314 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1315
1316 X86_64_VEX_0F3849,
1317 X86_64_VEX_0F384B,
1318 X86_64_VEX_0F385C,
1319 X86_64_VEX_0F385E,
1320 X86_64_VEX_0F386C,
1321 X86_64_VEX_0F38Ex,
1322
1323 X86_64_VEX_MAP7_F6_L_0_W_0_R_0,
1324 X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1325 };
1326
1327 enum
1328 {
1329 THREE_BYTE_0F38 = 0,
1330 THREE_BYTE_0F3A
1331 };
1332
1333 enum
1334 {
1335 XOP_08 = 0,
1336 XOP_09,
1337 XOP_0A
1338 };
1339
1340 enum
1341 {
1342 VEX_0F = 0,
1343 VEX_0F38,
1344 VEX_0F3A,
1345 VEX_MAP7,
1346 };
1347
1348 enum
1349 {
1350 EVEX_0F = 0,
1351 EVEX_0F38,
1352 EVEX_0F3A,
1353 EVEX_MAP4,
1354 EVEX_MAP5,
1355 EVEX_MAP6,
1356 EVEX_MAP7,
1357 };
1358
1359 enum
1360 {
1361 VEX_LEN_0F12_P_0 = 0,
1362 VEX_LEN_0F12_P_2,
1363 VEX_LEN_0F13,
1364 VEX_LEN_0F16_P_0,
1365 VEX_LEN_0F16_P_2,
1366 VEX_LEN_0F17,
1367 VEX_LEN_0F41,
1368 VEX_LEN_0F42,
1369 VEX_LEN_0F44,
1370 VEX_LEN_0F45,
1371 VEX_LEN_0F46,
1372 VEX_LEN_0F47,
1373 VEX_LEN_0F4A,
1374 VEX_LEN_0F4B,
1375 VEX_LEN_0F6E,
1376 VEX_LEN_0F77,
1377 VEX_LEN_0F7E_P_1,
1378 VEX_LEN_0F7E_P_2,
1379 VEX_LEN_0F90,
1380 VEX_LEN_0F91,
1381 VEX_LEN_0F92,
1382 VEX_LEN_0F93,
1383 VEX_LEN_0F98,
1384 VEX_LEN_0F99,
1385 VEX_LEN_0FAE_R_2,
1386 VEX_LEN_0FAE_R_3,
1387 VEX_LEN_0FC4,
1388 VEX_LEN_0FD6,
1389 VEX_LEN_0F3816,
1390 VEX_LEN_0F3819,
1391 VEX_LEN_0F381A,
1392 VEX_LEN_0F3836,
1393 VEX_LEN_0F3841,
1394 VEX_LEN_0F3849_X86_64,
1395 VEX_LEN_0F384B_X86_64,
1396 VEX_LEN_0F385A,
1397 VEX_LEN_0F385C_X86_64,
1398 VEX_LEN_0F385E_X86_64,
1399 VEX_LEN_0F386C_X86_64,
1400 VEX_LEN_0F38CB_P_3_W_0,
1401 VEX_LEN_0F38CC_P_3_W_0,
1402 VEX_LEN_0F38CD_P_3_W_0,
1403 VEX_LEN_0F38DA_W_0_P_0,
1404 VEX_LEN_0F38DA_W_0_P_2,
1405 VEX_LEN_0F38DB,
1406 VEX_LEN_0F38F2,
1407 VEX_LEN_0F38F3,
1408 VEX_LEN_0F38F5,
1409 VEX_LEN_0F38F6,
1410 VEX_LEN_0F38F7,
1411 VEX_LEN_0F3A00,
1412 VEX_LEN_0F3A01,
1413 VEX_LEN_0F3A06,
1414 VEX_LEN_0F3A14,
1415 VEX_LEN_0F3A15,
1416 VEX_LEN_0F3A16,
1417 VEX_LEN_0F3A17,
1418 VEX_LEN_0F3A18,
1419 VEX_LEN_0F3A19,
1420 VEX_LEN_0F3A20,
1421 VEX_LEN_0F3A21,
1422 VEX_LEN_0F3A22,
1423 VEX_LEN_0F3A30,
1424 VEX_LEN_0F3A31,
1425 VEX_LEN_0F3A32,
1426 VEX_LEN_0F3A33,
1427 VEX_LEN_0F3A38,
1428 VEX_LEN_0F3A39,
1429 VEX_LEN_0F3A41,
1430 VEX_LEN_0F3A46,
1431 VEX_LEN_0F3A60,
1432 VEX_LEN_0F3A61,
1433 VEX_LEN_0F3A62,
1434 VEX_LEN_0F3A63,
1435 VEX_LEN_0F3ADE_W_0,
1436 VEX_LEN_0F3ADF,
1437 VEX_LEN_0F3AF0,
1438 VEX_LEN_MAP7_F6,
1439 VEX_LEN_MAP7_F8,
1440 VEX_LEN_XOP_08_85,
1441 VEX_LEN_XOP_08_86,
1442 VEX_LEN_XOP_08_87,
1443 VEX_LEN_XOP_08_8E,
1444 VEX_LEN_XOP_08_8F,
1445 VEX_LEN_XOP_08_95,
1446 VEX_LEN_XOP_08_96,
1447 VEX_LEN_XOP_08_97,
1448 VEX_LEN_XOP_08_9E,
1449 VEX_LEN_XOP_08_9F,
1450 VEX_LEN_XOP_08_A3,
1451 VEX_LEN_XOP_08_A6,
1452 VEX_LEN_XOP_08_B6,
1453 VEX_LEN_XOP_08_C0,
1454 VEX_LEN_XOP_08_C1,
1455 VEX_LEN_XOP_08_C2,
1456 VEX_LEN_XOP_08_C3,
1457 VEX_LEN_XOP_08_CC,
1458 VEX_LEN_XOP_08_CD,
1459 VEX_LEN_XOP_08_CE,
1460 VEX_LEN_XOP_08_CF,
1461 VEX_LEN_XOP_08_EC,
1462 VEX_LEN_XOP_08_ED,
1463 VEX_LEN_XOP_08_EE,
1464 VEX_LEN_XOP_08_EF,
1465 VEX_LEN_XOP_09_01,
1466 VEX_LEN_XOP_09_02,
1467 VEX_LEN_XOP_09_12,
1468 VEX_LEN_XOP_09_82_W_0,
1469 VEX_LEN_XOP_09_83_W_0,
1470 VEX_LEN_XOP_09_90,
1471 VEX_LEN_XOP_09_91,
1472 VEX_LEN_XOP_09_92,
1473 VEX_LEN_XOP_09_93,
1474 VEX_LEN_XOP_09_94,
1475 VEX_LEN_XOP_09_95,
1476 VEX_LEN_XOP_09_96,
1477 VEX_LEN_XOP_09_97,
1478 VEX_LEN_XOP_09_98,
1479 VEX_LEN_XOP_09_99,
1480 VEX_LEN_XOP_09_9A,
1481 VEX_LEN_XOP_09_9B,
1482 VEX_LEN_XOP_09_C1,
1483 VEX_LEN_XOP_09_C2,
1484 VEX_LEN_XOP_09_C3,
1485 VEX_LEN_XOP_09_C6,
1486 VEX_LEN_XOP_09_C7,
1487 VEX_LEN_XOP_09_CB,
1488 VEX_LEN_XOP_09_D1,
1489 VEX_LEN_XOP_09_D2,
1490 VEX_LEN_XOP_09_D3,
1491 VEX_LEN_XOP_09_D6,
1492 VEX_LEN_XOP_09_D7,
1493 VEX_LEN_XOP_09_DB,
1494 VEX_LEN_XOP_09_E1,
1495 VEX_LEN_XOP_09_E2,
1496 VEX_LEN_XOP_09_E3,
1497 VEX_LEN_XOP_0A_12,
1498 };
1499
1500 enum
1501 {
1502 EVEX_LEN_0F3816 = 0,
1503 EVEX_LEN_0F3819,
1504 EVEX_LEN_0F381A,
1505 EVEX_LEN_0F381B,
1506 EVEX_LEN_0F3836,
1507 EVEX_LEN_0F385A,
1508 EVEX_LEN_0F385B,
1509 EVEX_LEN_0F38C6,
1510 EVEX_LEN_0F38C7,
1511 EVEX_LEN_0F3A00,
1512 EVEX_LEN_0F3A01,
1513 EVEX_LEN_0F3A18,
1514 EVEX_LEN_0F3A19,
1515 EVEX_LEN_0F3A1A,
1516 EVEX_LEN_0F3A1B,
1517 EVEX_LEN_0F3A23,
1518 EVEX_LEN_0F3A38,
1519 EVEX_LEN_0F3A39,
1520 EVEX_LEN_0F3A3A,
1521 EVEX_LEN_0F3A3B,
1522 EVEX_LEN_0F3A43
1523 };
1524
1525 enum
1526 {
1527 VEX_W_0F41_L_1 = 0,
1528 VEX_W_0F42_L_1,
1529 VEX_W_0F44_L_0,
1530 VEX_W_0F45_L_1,
1531 VEX_W_0F46_L_1,
1532 VEX_W_0F47_L_1,
1533 VEX_W_0F4A_L_1,
1534 VEX_W_0F4B_L_1,
1535 VEX_W_0F90_L_0,
1536 VEX_W_0F91_L_0,
1537 VEX_W_0F92_L_0,
1538 VEX_W_0F93_L_0,
1539 VEX_W_0F98_L_0,
1540 VEX_W_0F99_L_0,
1541 VEX_W_0F380C,
1542 VEX_W_0F380D,
1543 VEX_W_0F380E,
1544 VEX_W_0F380F,
1545 VEX_W_0F3813,
1546 VEX_W_0F3816_L_1,
1547 VEX_W_0F3818,
1548 VEX_W_0F3819_L_1,
1549 VEX_W_0F381A_L_1,
1550 VEX_W_0F382C,
1551 VEX_W_0F382D,
1552 VEX_W_0F382E,
1553 VEX_W_0F382F,
1554 VEX_W_0F3836,
1555 VEX_W_0F3846,
1556 VEX_W_0F3849_X86_64_L_0,
1557 VEX_W_0F384B_X86_64_L_0,
1558 VEX_W_0F3850,
1559 VEX_W_0F3851,
1560 VEX_W_0F3852,
1561 VEX_W_0F3853,
1562 VEX_W_0F3858,
1563 VEX_W_0F3859,
1564 VEX_W_0F385A_L_0,
1565 VEX_W_0F385C_X86_64_L_0,
1566 VEX_W_0F385E_X86_64_L_0,
1567 VEX_W_0F386C_X86_64_L_0,
1568 VEX_W_0F3872_P_1,
1569 VEX_W_0F3878,
1570 VEX_W_0F3879,
1571 VEX_W_0F38B0,
1572 VEX_W_0F38B1,
1573 VEX_W_0F38B4,
1574 VEX_W_0F38B5,
1575 VEX_W_0F38CB_P_3,
1576 VEX_W_0F38CC_P_3,
1577 VEX_W_0F38CD_P_3,
1578 VEX_W_0F38CF,
1579 VEX_W_0F38D2,
1580 VEX_W_0F38D3,
1581 VEX_W_0F38DA,
1582 VEX_W_0F3A00_L_1,
1583 VEX_W_0F3A01_L_1,
1584 VEX_W_0F3A02,
1585 VEX_W_0F3A04,
1586 VEX_W_0F3A05,
1587 VEX_W_0F3A06_L_1,
1588 VEX_W_0F3A18_L_1,
1589 VEX_W_0F3A19_L_1,
1590 VEX_W_0F3A1D,
1591 VEX_W_0F3A38_L_1,
1592 VEX_W_0F3A39_L_1,
1593 VEX_W_0F3A46_L_1,
1594 VEX_W_0F3A4A,
1595 VEX_W_0F3A4B,
1596 VEX_W_0F3A4C,
1597 VEX_W_0F3ACE,
1598 VEX_W_0F3ACF,
1599 VEX_W_0F3ADE,
1600 VEX_W_MAP7_F6_L_0,
1601 VEX_W_MAP7_F8_L_0,
1602
1603 VEX_W_XOP_08_85_L_0,
1604 VEX_W_XOP_08_86_L_0,
1605 VEX_W_XOP_08_87_L_0,
1606 VEX_W_XOP_08_8E_L_0,
1607 VEX_W_XOP_08_8F_L_0,
1608 VEX_W_XOP_08_95_L_0,
1609 VEX_W_XOP_08_96_L_0,
1610 VEX_W_XOP_08_97_L_0,
1611 VEX_W_XOP_08_9E_L_0,
1612 VEX_W_XOP_08_9F_L_0,
1613 VEX_W_XOP_08_A6_L_0,
1614 VEX_W_XOP_08_B6_L_0,
1615 VEX_W_XOP_08_C0_L_0,
1616 VEX_W_XOP_08_C1_L_0,
1617 VEX_W_XOP_08_C2_L_0,
1618 VEX_W_XOP_08_C3_L_0,
1619 VEX_W_XOP_08_CC_L_0,
1620 VEX_W_XOP_08_CD_L_0,
1621 VEX_W_XOP_08_CE_L_0,
1622 VEX_W_XOP_08_CF_L_0,
1623 VEX_W_XOP_08_EC_L_0,
1624 VEX_W_XOP_08_ED_L_0,
1625 VEX_W_XOP_08_EE_L_0,
1626 VEX_W_XOP_08_EF_L_0,
1627
1628 VEX_W_XOP_09_80,
1629 VEX_W_XOP_09_81,
1630 VEX_W_XOP_09_82,
1631 VEX_W_XOP_09_83,
1632 VEX_W_XOP_09_C1_L_0,
1633 VEX_W_XOP_09_C2_L_0,
1634 VEX_W_XOP_09_C3_L_0,
1635 VEX_W_XOP_09_C6_L_0,
1636 VEX_W_XOP_09_C7_L_0,
1637 VEX_W_XOP_09_CB_L_0,
1638 VEX_W_XOP_09_D1_L_0,
1639 VEX_W_XOP_09_D2_L_0,
1640 VEX_W_XOP_09_D3_L_0,
1641 VEX_W_XOP_09_D6_L_0,
1642 VEX_W_XOP_09_D7_L_0,
1643 VEX_W_XOP_09_DB_L_0,
1644 VEX_W_XOP_09_E1_L_0,
1645 VEX_W_XOP_09_E2_L_0,
1646 VEX_W_XOP_09_E3_L_0,
1647
1648 EVEX_W_0F5B_P_0,
1649 EVEX_W_0F62,
1650 EVEX_W_0F66,
1651 EVEX_W_0F6A,
1652 EVEX_W_0F6B,
1653 EVEX_W_0F6C,
1654 EVEX_W_0F6D,
1655 EVEX_W_0F6F_P_1,
1656 EVEX_W_0F6F_P_2,
1657 EVEX_W_0F6F_P_3,
1658 EVEX_W_0F70_P_2,
1659 EVEX_W_0F72_R_2,
1660 EVEX_W_0F72_R_6,
1661 EVEX_W_0F73_R_2,
1662 EVEX_W_0F73_R_6,
1663 EVEX_W_0F76,
1664 EVEX_W_0F78_P_0,
1665 EVEX_W_0F78_P_2,
1666 EVEX_W_0F79_P_0,
1667 EVEX_W_0F79_P_2,
1668 EVEX_W_0F7A_P_1,
1669 EVEX_W_0F7A_P_2,
1670 EVEX_W_0F7A_P_3,
1671 EVEX_W_0F7B_P_2,
1672 EVEX_W_0F7E_P_1,
1673 EVEX_W_0F7F_P_1,
1674 EVEX_W_0F7F_P_2,
1675 EVEX_W_0F7F_P_3,
1676 EVEX_W_0FD2,
1677 EVEX_W_0FD3,
1678 EVEX_W_0FD4,
1679 EVEX_W_0FD6,
1680 EVEX_W_0FE6_P_1,
1681 EVEX_W_0FE7,
1682 EVEX_W_0FF2,
1683 EVEX_W_0FF3,
1684 EVEX_W_0FF4,
1685 EVEX_W_0FFA,
1686 EVEX_W_0FFB,
1687 EVEX_W_0FFE,
1688
1689 EVEX_W_0F3810_P_1,
1690 EVEX_W_0F3810_P_2,
1691 EVEX_W_0F3811_P_1,
1692 EVEX_W_0F3811_P_2,
1693 EVEX_W_0F3812_P_1,
1694 EVEX_W_0F3812_P_2,
1695 EVEX_W_0F3813_P_1,
1696 EVEX_W_0F3814_P_1,
1697 EVEX_W_0F3815_P_1,
1698 EVEX_W_0F3819_L_n,
1699 EVEX_W_0F381A_L_n,
1700 EVEX_W_0F381B_L_2,
1701 EVEX_W_0F381E,
1702 EVEX_W_0F381F,
1703 EVEX_W_0F3820_P_1,
1704 EVEX_W_0F3821_P_1,
1705 EVEX_W_0F3822_P_1,
1706 EVEX_W_0F3823_P_1,
1707 EVEX_W_0F3824_P_1,
1708 EVEX_W_0F3825_P_1,
1709 EVEX_W_0F3825_P_2,
1710 EVEX_W_0F3828_P_2,
1711 EVEX_W_0F3829_P_2,
1712 EVEX_W_0F382A_P_1,
1713 EVEX_W_0F382A_P_2,
1714 EVEX_W_0F382B,
1715 EVEX_W_0F3830_P_1,
1716 EVEX_W_0F3831_P_1,
1717 EVEX_W_0F3832_P_1,
1718 EVEX_W_0F3833_P_1,
1719 EVEX_W_0F3834_P_1,
1720 EVEX_W_0F3835_P_1,
1721 EVEX_W_0F3835_P_2,
1722 EVEX_W_0F3837,
1723 EVEX_W_0F383A_P_1,
1724 EVEX_W_0F3859,
1725 EVEX_W_0F385A_L_n,
1726 EVEX_W_0F385B_L_2,
1727 EVEX_W_0F3870,
1728 EVEX_W_0F3872_P_2,
1729 EVEX_W_0F387A,
1730 EVEX_W_0F387B,
1731 EVEX_W_0F3883,
1732
1733 EVEX_W_0F3A18_L_n,
1734 EVEX_W_0F3A19_L_n,
1735 EVEX_W_0F3A1A_L_2,
1736 EVEX_W_0F3A1B_L_2,
1737 EVEX_W_0F3A21,
1738 EVEX_W_0F3A23_L_n,
1739 EVEX_W_0F3A38_L_n,
1740 EVEX_W_0F3A39_L_n,
1741 EVEX_W_0F3A3A_L_2,
1742 EVEX_W_0F3A3B_L_2,
1743 EVEX_W_0F3A42,
1744 EVEX_W_0F3A43_L_n,
1745 EVEX_W_0F3A70,
1746 EVEX_W_0F3A72,
1747
1748 EVEX_W_MAP4_8F_R_0,
1749 EVEX_W_MAP4_F8_P1_M_1,
1750 EVEX_W_MAP4_F8_P3_M_1,
1751 EVEX_W_MAP4_FF_R_6,
1752
1753 EVEX_W_MAP5_5B_P_0,
1754 EVEX_W_MAP5_7A_P_3,
1755 };
1756
1757 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1758
1759 struct dis386 {
1760 const char *name;
1761 struct
1762 {
1763 op_rtn rtn;
1764 int bytemode;
1765 } op[MAX_OPERANDS];
1766 unsigned int prefix_requirement;
1767 };
1768
1769 /* Upper case letters in the instruction names here are macros.
1770 'A' => print 'b' if no (suitable) register operand or suffix_always is true
1771 'B' => print 'b' if suffix_always is true
1772 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1773 size prefix
1774 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1775 suffix_always is true
1776 'E' => print 'e' if 32-bit form of jcxz
1777 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1778 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1779 'H' => print ",pt" or ",pn" branch hint
1780 'I' unused.
1781 'J' unused.
1782 'K' => print 'd' or 'q' if rex prefix is present.
1783 'L' => print 'l' or 'q' if suffix_always is true
1784 'M' => print 'r' if intel_mnemonic is false.
1785 'N' => print 'n' if instruction has no wait "prefix"
1786 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1787 'P' => behave as 'T' except with register operand outside of suffix_always
1788 mode
1789 'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1790 suffix_always is true
1791 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1792 'S' => print 'w', 'l' or 'q' if suffix_always is true
1793 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1794 prefix or if suffix_always is true.
1795 'U' unused.
1796 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1797 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1798 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1799 'Y' => no output, mark EVEX.aaa != 0 as bad.
1800 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1801 '!' => change condition from true to false or from false to true.
1802 '%' => add 1 upper case letter to the macro.
1803 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1804 prefix or suffix_always is true (lcall/ljmp).
1805 '@' => in 64bit mode for Intel64 ISA or if instruction
1806 has no operand sizing prefix, print 'q' if suffix_always is true or
1807 nothing otherwise; behave as 'P' in all other cases
1808
1809 2 upper case letter macros:
1810 "CC" => print condition code
1811 "XY" => print 'x' or 'y' if suffix_always is true or no register
1812 operands and no broadcast.
1813 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1814 register operands and no broadcast.
1815 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1816 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1817 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1818 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1819 "XV" => print "{vex} " pseudo prefix
1820 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1821 is used by an EVEX-encoded (AVX512VL) instruction.
1822 "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
1823 pseudo prefix when instructions without NF, EGPR and VVVV,
1824 "NE" => don't print "{evex} " pseudo prefix for some special instructions
1825 in MAP4.
1826 "ZU" => print 'zu' if EVEX.ZU=1.
1827 "SC" => print suffix SCC for SCC insns
1828 "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1829 "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1830 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1831 being false, or no operand at all in 64bit mode, or if suffix_always
1832 is true.
1833 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1834 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1835 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1836 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1837 "DF" => print default flag value for SCC insns
1838 "BW" => print 'b' or 'w' depending on the VEX.W bit
1839 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1840 an operand size prefix, or suffix_always is true. print
1841 'q' if rex prefix is present.
1842
1843 Many of the above letters print nothing in Intel mode. See "putop"
1844 for the details.
1845
1846 Braces '{' and '}', and vertical bars '|', indicate alternative
1847 mnemonic strings for AT&T and Intel. */
1848
1849 static const struct dis386 dis386[] = {
1850 /* 00 */
1851 { "addB", { Ebh1, Gb }, 0 },
1852 { "addS", { Evh1, Gv }, 0 },
1853 { "addB", { Gb, EbS }, 0 },
1854 { "addS", { Gv, EvS }, 0 },
1855 { "addB", { AL, Ib }, 0 },
1856 { "addS", { eAX, Iv }, 0 },
1857 { X86_64_TABLE (X86_64_06) },
1858 { X86_64_TABLE (X86_64_07) },
1859 /* 08 */
1860 { "orB", { Ebh1, Gb }, 0 },
1861 { "orS", { Evh1, Gv }, 0 },
1862 { "orB", { Gb, EbS }, 0 },
1863 { "orS", { Gv, EvS }, 0 },
1864 { "orB", { AL, Ib }, 0 },
1865 { "orS", { eAX, Iv }, 0 },
1866 { X86_64_TABLE (X86_64_0E) },
1867 { Bad_Opcode }, /* 0x0f extended opcode escape */
1868 /* 10 */
1869 { "adcB", { Ebh1, Gb }, 0 },
1870 { "adcS", { Evh1, Gv }, 0 },
1871 { "adcB", { Gb, EbS }, 0 },
1872 { "adcS", { Gv, EvS }, 0 },
1873 { "adcB", { AL, Ib }, 0 },
1874 { "adcS", { eAX, Iv }, 0 },
1875 { X86_64_TABLE (X86_64_16) },
1876 { X86_64_TABLE (X86_64_17) },
1877 /* 18 */
1878 { "sbbB", { Ebh1, Gb }, 0 },
1879 { "sbbS", { Evh1, Gv }, 0 },
1880 { "sbbB", { Gb, EbS }, 0 },
1881 { "sbbS", { Gv, EvS }, 0 },
1882 { "sbbB", { AL, Ib }, 0 },
1883 { "sbbS", { eAX, Iv }, 0 },
1884 { X86_64_TABLE (X86_64_1E) },
1885 { X86_64_TABLE (X86_64_1F) },
1886 /* 20 */
1887 { "andB", { Ebh1, Gb }, 0 },
1888 { "andS", { Evh1, Gv }, 0 },
1889 { "andB", { Gb, EbS }, 0 },
1890 { "andS", { Gv, EvS }, 0 },
1891 { "andB", { AL, Ib }, 0 },
1892 { "andS", { eAX, Iv }, 0 },
1893 { Bad_Opcode }, /* SEG ES prefix */
1894 { X86_64_TABLE (X86_64_27) },
1895 /* 28 */
1896 { "subB", { Ebh1, Gb }, 0 },
1897 { "subS", { Evh1, Gv }, 0 },
1898 { "subB", { Gb, EbS }, 0 },
1899 { "subS", { Gv, EvS }, 0 },
1900 { "subB", { AL, Ib }, 0 },
1901 { "subS", { eAX, Iv }, 0 },
1902 { Bad_Opcode }, /* SEG CS prefix */
1903 { X86_64_TABLE (X86_64_2F) },
1904 /* 30 */
1905 { "xorB", { Ebh1, Gb }, 0 },
1906 { "xorS", { Evh1, Gv }, 0 },
1907 { "xorB", { Gb, EbS }, 0 },
1908 { "xorS", { Gv, EvS }, 0 },
1909 { "xorB", { AL, Ib }, 0 },
1910 { "xorS", { eAX, Iv }, 0 },
1911 { Bad_Opcode }, /* SEG SS prefix */
1912 { X86_64_TABLE (X86_64_37) },
1913 /* 38 */
1914 { "cmpB", { Eb, Gb }, 0 },
1915 { "cmpS", { Ev, Gv }, 0 },
1916 { "cmpB", { Gb, EbS }, 0 },
1917 { "cmpS", { Gv, EvS }, 0 },
1918 { "cmpB", { AL, Ib }, 0 },
1919 { "cmpS", { eAX, Iv }, 0 },
1920 { Bad_Opcode }, /* SEG DS prefix */
1921 { X86_64_TABLE (X86_64_3F) },
1922 /* 40 */
1923 { "inc{S|}", { RMeAX }, 0 },
1924 { "inc{S|}", { RMeCX }, 0 },
1925 { "inc{S|}", { RMeDX }, 0 },
1926 { "inc{S|}", { RMeBX }, 0 },
1927 { "inc{S|}", { RMeSP }, 0 },
1928 { "inc{S|}", { RMeBP }, 0 },
1929 { "inc{S|}", { RMeSI }, 0 },
1930 { "inc{S|}", { RMeDI }, 0 },
1931 /* 48 */
1932 { "dec{S|}", { RMeAX }, 0 },
1933 { "dec{S|}", { RMeCX }, 0 },
1934 { "dec{S|}", { RMeDX }, 0 },
1935 { "dec{S|}", { RMeBX }, 0 },
1936 { "dec{S|}", { RMeSP }, 0 },
1937 { "dec{S|}", { RMeBP }, 0 },
1938 { "dec{S|}", { RMeSI }, 0 },
1939 { "dec{S|}", { RMeDI }, 0 },
1940 /* 50 */
1941 { "push!P", { RMrAX }, 0 },
1942 { "push!P", { RMrCX }, 0 },
1943 { "push!P", { RMrDX }, 0 },
1944 { "push!P", { RMrBX }, 0 },
1945 { "push!P", { RMrSP }, 0 },
1946 { "push!P", { RMrBP }, 0 },
1947 { "push!P", { RMrSI }, 0 },
1948 { "push!P", { RMrDI }, 0 },
1949 /* 58 */
1950 { "pop!P", { RMrAX }, 0 },
1951 { "pop!P", { RMrCX }, 0 },
1952 { "pop!P", { RMrDX }, 0 },
1953 { "pop!P", { RMrBX }, 0 },
1954 { "pop!P", { RMrSP }, 0 },
1955 { "pop!P", { RMrBP }, 0 },
1956 { "pop!P", { RMrSI }, 0 },
1957 { "pop!P", { RMrDI }, 0 },
1958 /* 60 */
1959 { X86_64_TABLE (X86_64_60) },
1960 { X86_64_TABLE (X86_64_61) },
1961 { X86_64_TABLE (X86_64_62) },
1962 { X86_64_TABLE (X86_64_63) },
1963 { Bad_Opcode }, /* seg fs */
1964 { Bad_Opcode }, /* seg gs */
1965 { Bad_Opcode }, /* op size prefix */
1966 { Bad_Opcode }, /* adr size prefix */
1967 /* 68 */
1968 { "pushP", { sIv }, 0 },
1969 { "imulS", { Gv, Ev, Iv }, 0 },
1970 { "pushP", { sIbT }, 0 },
1971 { "imulS", { Gv, Ev, sIb }, 0 },
1972 { "ins{b|}", { Ybr, indirDX }, 0 },
1973 { X86_64_TABLE (X86_64_6D) },
1974 { "outs{b|}", { indirDXr, Xb }, 0 },
1975 { X86_64_TABLE (X86_64_6F) },
1976 /* 70 */
1977 { "joH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1978 { "jnoH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1979 { "jbH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1980 { "jaeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1981 { "jeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1982 { "jneH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1983 { "jbeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1984 { "jaH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1985 /* 78 */
1986 { "jsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1987 { "jnsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1988 { "jpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1989 { "jnpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1990 { "jlH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1991 { "jgeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1992 { "jleH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1993 { "jgH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1994 /* 80 */
1995 { REG_TABLE (REG_80) },
1996 { REG_TABLE (REG_81) },
1997 { X86_64_TABLE (X86_64_82) },
1998 { REG_TABLE (REG_83) },
1999 { "testB", { Eb, Gb }, 0 },
2000 { "testS", { Ev, Gv }, 0 },
2001 { "xchgB", { Ebh2, Gb }, 0 },
2002 { "xchgS", { Evh2, Gv }, 0 },
2003 /* 88 */
2004 { "movB", { Ebh3, Gb }, 0 },
2005 { "movS", { Evh3, Gv }, 0 },
2006 { "movB", { Gb, EbS }, 0 },
2007 { "movS", { Gv, EvS }, 0 },
2008 { "movD", { Sv, Sw }, 0 },
2009 { "leaS", { Gv, M }, 0 },
2010 { "movD", { Sw, Sv }, 0 },
2011 { REG_TABLE (REG_8F) },
2012 /* 90 */
2013 { PREFIX_TABLE (PREFIX_90) },
2014 { "xchgS", { RMeCX, eAX }, 0 },
2015 { "xchgS", { RMeDX, eAX }, 0 },
2016 { "xchgS", { RMeBX, eAX }, 0 },
2017 { "xchgS", { RMeSP, eAX }, 0 },
2018 { "xchgS", { RMeBP, eAX }, 0 },
2019 { "xchgS", { RMeSI, eAX }, 0 },
2020 { "xchgS", { RMeDI, eAX }, 0 },
2021 /* 98 */
2022 { "cW{t|}R", { XX }, 0 },
2023 { "cR{t|}O", { XX }, 0 },
2024 { X86_64_TABLE (X86_64_9A) },
2025 { Bad_Opcode }, /* fwait */
2026 { "pushfP", { XX }, 0 },
2027 { "popfP", { XX }, 0 },
2028 { "sahf", { XX }, 0 },
2029 { "lahf", { XX }, 0 },
2030 /* a0 */
2031 { "mov%LB", { AL, Ob }, PREFIX_REX2_ILLEGAL },
2032 { "mov%LS", { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2033 { "mov%LB", { Ob, AL }, PREFIX_REX2_ILLEGAL },
2034 { "mov%LS", { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2035 { "movs{b|}", { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2036 { "movs{R|}", { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2037 { "cmps{b|}", { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2038 { "cmps{R|}", { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2039 /* a8 */
2040 { "testB", { AL, Ib }, PREFIX_REX2_ILLEGAL },
2041 { "testS", { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2042 { "stosB", { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2043 { "stosS", { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2044 { "lodsB", { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2045 { "lodsS", { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2046 { "scasB", { AL, Yb }, PREFIX_REX2_ILLEGAL },
2047 { "scasS", { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2048 /* b0 */
2049 { "movB", { RMAL, Ib }, 0 },
2050 { "movB", { RMCL, Ib }, 0 },
2051 { "movB", { RMDL, Ib }, 0 },
2052 { "movB", { RMBL, Ib }, 0 },
2053 { "movB", { RMAH, Ib }, 0 },
2054 { "movB", { RMCH, Ib }, 0 },
2055 { "movB", { RMDH, Ib }, 0 },
2056 { "movB", { RMBH, Ib }, 0 },
2057 /* b8 */
2058 { "mov%LV", { RMeAX, Iv64 }, 0 },
2059 { "mov%LV", { RMeCX, Iv64 }, 0 },
2060 { "mov%LV", { RMeDX, Iv64 }, 0 },
2061 { "mov%LV", { RMeBX, Iv64 }, 0 },
2062 { "mov%LV", { RMeSP, Iv64 }, 0 },
2063 { "mov%LV", { RMeBP, Iv64 }, 0 },
2064 { "mov%LV", { RMeSI, Iv64 }, 0 },
2065 { "mov%LV", { RMeDI, Iv64 }, 0 },
2066 /* c0 */
2067 { REG_TABLE (REG_C0) },
2068 { REG_TABLE (REG_C1) },
2069 { X86_64_TABLE (X86_64_C2) },
2070 { X86_64_TABLE (X86_64_C3) },
2071 { X86_64_TABLE (X86_64_C4) },
2072 { X86_64_TABLE (X86_64_C5) },
2073 { REG_TABLE (REG_C6) },
2074 { REG_TABLE (REG_C7) },
2075 /* c8 */
2076 { "enterP", { Iw, Ib }, 0 },
2077 { "leaveP", { XX }, 0 },
2078 { "{l|}ret{|f}%LP", { Iw }, 0 },
2079 { "{l|}ret{|f}%LP", { XX }, 0 },
2080 { "int3", { XX }, 0 },
2081 { "int", { Ib }, 0 },
2082 { X86_64_TABLE (X86_64_CE) },
2083 { "iret%LP", { XX }, 0 },
2084 /* d0 */
2085 { REG_TABLE (REG_D0) },
2086 { REG_TABLE (REG_D1) },
2087 { REG_TABLE (REG_D2) },
2088 { REG_TABLE (REG_D3) },
2089 { X86_64_TABLE (X86_64_D4) },
2090 { X86_64_TABLE (X86_64_D5) },
2091 { Bad_Opcode },
2092 { "xlat", { DSBX }, 0 },
2093 /* d8 */
2094 { FLOAT },
2095 { FLOAT },
2096 { FLOAT },
2097 { FLOAT },
2098 { FLOAT },
2099 { FLOAT },
2100 { FLOAT },
2101 { FLOAT },
2102 /* e0 */
2103 { "loopneFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2104 { "loopeFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2105 { "loopFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2106 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2107 { "inB", { AL, Ib }, PREFIX_REX2_ILLEGAL },
2108 { "inG", { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2109 { "outB", { Ib, AL }, PREFIX_REX2_ILLEGAL },
2110 { "outG", { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2111 /* e8 */
2112 { X86_64_TABLE (X86_64_E8) },
2113 { X86_64_TABLE (X86_64_E9) },
2114 { X86_64_TABLE (X86_64_EA) },
2115 { "jmp", { Jb, BND }, PREFIX_REX2_ILLEGAL },
2116 { "inB", { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2117 { "inG", { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2118 { "outB", { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2119 { "outG", { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2120 /* f0 */
2121 { Bad_Opcode }, /* lock prefix */
2122 { "int1", { XX }, 0 },
2123 { Bad_Opcode }, /* repne */
2124 { Bad_Opcode }, /* repz */
2125 { "hlt", { XX }, 0 },
2126 { "cmc", { XX }, 0 },
2127 { REG_TABLE (REG_F6) },
2128 { REG_TABLE (REG_F7) },
2129 /* f8 */
2130 { "clc", { XX }, 0 },
2131 { "stc", { XX }, 0 },
2132 { "cli", { XX }, 0 },
2133 { "sti", { XX }, 0 },
2134 { "cld", { XX }, 0 },
2135 { "std", { XX }, 0 },
2136 { REG_TABLE (REG_FE) },
2137 { REG_TABLE (REG_FF) },
2138 };
2139
2140 static const struct dis386 dis386_twobyte[] = {
2141 /* 00 */
2142 { REG_TABLE (REG_0F00 ) },
2143 { REG_TABLE (REG_0F01 ) },
2144 { "larS", { Gv, Sv }, 0 },
2145 { "lslS", { Gv, Sv }, 0 },
2146 { Bad_Opcode },
2147 { "syscall", { XX }, 0 },
2148 { "clts", { XX }, 0 },
2149 { "sysret%LQ", { XX }, 0 },
2150 /* 08 */
2151 { "invd", { XX }, 0 },
2152 { PREFIX_TABLE (PREFIX_0F09) },
2153 { Bad_Opcode },
2154 { "ud2", { XX }, 0 },
2155 { Bad_Opcode },
2156 { REG_TABLE (REG_0F0D) },
2157 { "femms", { XX }, 0 },
2158 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2159 /* 10 */
2160 { PREFIX_TABLE (PREFIX_0F10) },
2161 { PREFIX_TABLE (PREFIX_0F11) },
2162 { PREFIX_TABLE (PREFIX_0F12) },
2163 { "movlpX", { Mq, XM }, PREFIX_OPCODE },
2164 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2165 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2166 { PREFIX_TABLE (PREFIX_0F16) },
2167 { "movhpX", { Mq, XM }, PREFIX_OPCODE },
2168 /* 18 */
2169 { REG_TABLE (REG_0F18) },
2170 { "nopQ", { Ev }, 0 },
2171 { PREFIX_TABLE (PREFIX_0F1A) },
2172 { PREFIX_TABLE (PREFIX_0F1B) },
2173 { PREFIX_TABLE (PREFIX_0F1C) },
2174 { "nopQ", { Ev }, 0 },
2175 { PREFIX_TABLE (PREFIX_0F1E) },
2176 { "nopQ", { Ev }, 0 },
2177 /* 20 */
2178 { "movZ", { Em, Cm }, 0 },
2179 { "movZ", { Em, Dm }, 0 },
2180 { "movZ", { Cm, Em }, 0 },
2181 { "movZ", { Dm, Em }, 0 },
2182 { X86_64_TABLE (X86_64_0F24) },
2183 { Bad_Opcode },
2184 { X86_64_TABLE (X86_64_0F26) },
2185 { Bad_Opcode },
2186 /* 28 */
2187 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2188 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2189 { PREFIX_TABLE (PREFIX_0F2A) },
2190 { PREFIX_TABLE (PREFIX_0F2B) },
2191 { PREFIX_TABLE (PREFIX_0F2C) },
2192 { PREFIX_TABLE (PREFIX_0F2D) },
2193 { PREFIX_TABLE (PREFIX_0F2E) },
2194 { PREFIX_TABLE (PREFIX_0F2F) },
2195 /* 30 */
2196 { "wrmsr", { XX }, PREFIX_REX2_ILLEGAL },
2197 { "rdtsc", { XX }, PREFIX_REX2_ILLEGAL },
2198 { "rdmsr", { XX }, PREFIX_REX2_ILLEGAL },
2199 { "rdpmc", { XX }, PREFIX_REX2_ILLEGAL },
2200 { "sysenter", { SEP }, PREFIX_REX2_ILLEGAL },
2201 { "sysexit%LQ", { SEP }, PREFIX_REX2_ILLEGAL },
2202 { Bad_Opcode },
2203 { "getsec", { XX }, 0 },
2204 /* 38 */
2205 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2206 { Bad_Opcode },
2207 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2208 { Bad_Opcode },
2209 { Bad_Opcode },
2210 { Bad_Opcode },
2211 { Bad_Opcode },
2212 { Bad_Opcode },
2213 /* 40 */
2214 { "cmovoS", { Gv, Ev }, 0 },
2215 { "cmovnoS", { Gv, Ev }, 0 },
2216 { "cmovbS", { Gv, Ev }, 0 },
2217 { "cmovaeS", { Gv, Ev }, 0 },
2218 { "cmoveS", { Gv, Ev }, 0 },
2219 { "cmovneS", { Gv, Ev }, 0 },
2220 { "cmovbeS", { Gv, Ev }, 0 },
2221 { "cmovaS", { Gv, Ev }, 0 },
2222 /* 48 */
2223 { "cmovsS", { Gv, Ev }, 0 },
2224 { "cmovnsS", { Gv, Ev }, 0 },
2225 { "cmovpS", { Gv, Ev }, 0 },
2226 { "cmovnpS", { Gv, Ev }, 0 },
2227 { "cmovlS", { Gv, Ev }, 0 },
2228 { "cmovgeS", { Gv, Ev }, 0 },
2229 { "cmovleS", { Gv, Ev }, 0 },
2230 { "cmovgS", { Gv, Ev }, 0 },
2231 /* 50 */
2232 { "movmskpX", { Gdq, Ux }, PREFIX_OPCODE },
2233 { PREFIX_TABLE (PREFIX_0F51) },
2234 { PREFIX_TABLE (PREFIX_0F52) },
2235 { PREFIX_TABLE (PREFIX_0F53) },
2236 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2237 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2238 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2239 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2240 /* 58 */
2241 { PREFIX_TABLE (PREFIX_0F58) },
2242 { PREFIX_TABLE (PREFIX_0F59) },
2243 { PREFIX_TABLE (PREFIX_0F5A) },
2244 { PREFIX_TABLE (PREFIX_0F5B) },
2245 { PREFIX_TABLE (PREFIX_0F5C) },
2246 { PREFIX_TABLE (PREFIX_0F5D) },
2247 { PREFIX_TABLE (PREFIX_0F5E) },
2248 { PREFIX_TABLE (PREFIX_0F5F) },
2249 /* 60 */
2250 { PREFIX_TABLE (PREFIX_0F60) },
2251 { PREFIX_TABLE (PREFIX_0F61) },
2252 { PREFIX_TABLE (PREFIX_0F62) },
2253 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2254 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2255 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2256 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2257 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2258 /* 68 */
2259 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2260 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2261 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2262 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2263 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2264 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2265 { "movK", { MX, Edq }, PREFIX_OPCODE },
2266 { PREFIX_TABLE (PREFIX_0F6F) },
2267 /* 70 */
2268 { PREFIX_TABLE (PREFIX_0F70) },
2269 { REG_TABLE (REG_0F71) },
2270 { REG_TABLE (REG_0F72) },
2271 { REG_TABLE (REG_0F73) },
2272 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2273 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2274 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2275 { "emms", { XX }, PREFIX_OPCODE },
2276 /* 78 */
2277 { PREFIX_TABLE (PREFIX_0F78) },
2278 { PREFIX_TABLE (PREFIX_0F79) },
2279 { Bad_Opcode },
2280 { Bad_Opcode },
2281 { PREFIX_TABLE (PREFIX_0F7C) },
2282 { PREFIX_TABLE (PREFIX_0F7D) },
2283 { PREFIX_TABLE (PREFIX_0F7E) },
2284 { PREFIX_TABLE (PREFIX_0F7F) },
2285 /* 80 */
2286 { "joH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2287 { "jnoH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2288 { "jbH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2289 { "jaeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2290 { "jeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2291 { "jneH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2292 { "jbeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2293 { "jaH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2294 /* 88 */
2295 { "jsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2296 { "jnsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2297 { "jpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2298 { "jnpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2299 { "jlH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2300 { "jgeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2301 { "jleH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2302 { "jgH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2303 /* 90 */
2304 { "seto", { Eb }, 0 },
2305 { "setno", { Eb }, 0 },
2306 { "setb", { Eb }, 0 },
2307 { "setae", { Eb }, 0 },
2308 { "sete", { Eb }, 0 },
2309 { "setne", { Eb }, 0 },
2310 { "setbe", { Eb }, 0 },
2311 { "seta", { Eb }, 0 },
2312 /* 98 */
2313 { "sets", { Eb }, 0 },
2314 { "setns", { Eb }, 0 },
2315 { "setp", { Eb }, 0 },
2316 { "setnp", { Eb }, 0 },
2317 { "setl", { Eb }, 0 },
2318 { "setge", { Eb }, 0 },
2319 { "setle", { Eb }, 0 },
2320 { "setg", { Eb }, 0 },
2321 /* a0 */
2322 { "pushP", { fs }, 0 },
2323 { "popP", { fs }, 0 },
2324 { "cpuid", { XX }, 0 },
2325 { "btS", { Ev, Gv }, 0 },
2326 { "shldS", { Ev, Gv, Ib }, 0 },
2327 { "shldS", { Ev, Gv, CL }, 0 },
2328 { REG_TABLE (REG_0FA6) },
2329 { REG_TABLE (REG_0FA7) },
2330 /* a8 */
2331 { "pushP", { gs }, 0 },
2332 { "popP", { gs }, 0 },
2333 { "rsm", { XX }, 0 },
2334 { "btsS", { Evh1, Gv }, 0 },
2335 { "shrdS", { Ev, Gv, Ib }, 0 },
2336 { "shrdS", { Ev, Gv, CL }, 0 },
2337 { REG_TABLE (REG_0FAE) },
2338 { "imulS", { Gv, Ev }, 0 },
2339 /* b0 */
2340 { "cmpxchgB", { Ebh1, Gb }, 0 },
2341 { "cmpxchgS", { Evh1, Gv }, 0 },
2342 { "lssS", { Gv, Mp }, 0 },
2343 { "btrS", { Evh1, Gv }, 0 },
2344 { "lfsS", { Gv, Mp }, 0 },
2345 { "lgsS", { Gv, Mp }, 0 },
2346 { "movz{bR|x}", { Gv, Eb }, 0 },
2347 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2348 /* b8 */
2349 { PREFIX_TABLE (PREFIX_0FB8) },
2350 { "ud1S", { Gv, Ev }, 0 },
2351 { REG_TABLE (REG_0FBA) },
2352 { "btcS", { Evh1, Gv }, 0 },
2353 { PREFIX_TABLE (PREFIX_0FBC) },
2354 { PREFIX_TABLE (PREFIX_0FBD) },
2355 { "movs{bR|x}", { Gv, Eb }, 0 },
2356 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2357 /* c0 */
2358 { "xaddB", { Ebh1, Gb }, 0 },
2359 { "xaddS", { Evh1, Gv }, 0 },
2360 { PREFIX_TABLE (PREFIX_0FC2) },
2361 { "movntiS", { Mdq, Gdq }, PREFIX_OPCODE },
2362 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
2363 { "pextrw", { Gd, Nq, Ib }, PREFIX_OPCODE },
2364 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2365 { REG_TABLE (REG_0FC7) },
2366 /* c8 */
2367 { "bswap", { RMeAX }, 0 },
2368 { "bswap", { RMeCX }, 0 },
2369 { "bswap", { RMeDX }, 0 },
2370 { "bswap", { RMeBX }, 0 },
2371 { "bswap", { RMeSP }, 0 },
2372 { "bswap", { RMeBP }, 0 },
2373 { "bswap", { RMeSI }, 0 },
2374 { "bswap", { RMeDI }, 0 },
2375 /* d0 */
2376 { PREFIX_TABLE (PREFIX_0FD0) },
2377 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2378 { "psrld", { MX, EM }, PREFIX_OPCODE },
2379 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2380 { "paddq", { MX, EM }, PREFIX_OPCODE },
2381 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2382 { PREFIX_TABLE (PREFIX_0FD6) },
2383 { "pmovmskb", { Gdq, Nq }, PREFIX_OPCODE },
2384 /* d8 */
2385 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2386 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2387 { "pminub", { MX, EM }, PREFIX_OPCODE },
2388 { "pand", { MX, EM }, PREFIX_OPCODE },
2389 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2390 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2391 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2392 { "pandn", { MX, EM }, PREFIX_OPCODE },
2393 /* e0 */
2394 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2395 { "psraw", { MX, EM }, PREFIX_OPCODE },
2396 { "psrad", { MX, EM }, PREFIX_OPCODE },
2397 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2398 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2399 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2400 { PREFIX_TABLE (PREFIX_0FE6) },
2401 { PREFIX_TABLE (PREFIX_0FE7) },
2402 /* e8 */
2403 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2404 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2405 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2406 { "por", { MX, EM }, PREFIX_OPCODE },
2407 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2408 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2409 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2410 { "pxor", { MX, EM }, PREFIX_OPCODE },
2411 /* f0 */
2412 { PREFIX_TABLE (PREFIX_0FF0) },
2413 { "psllw", { MX, EM }, PREFIX_OPCODE },
2414 { "pslld", { MX, EM }, PREFIX_OPCODE },
2415 { "psllq", { MX, EM }, PREFIX_OPCODE },
2416 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2417 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2418 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2419 { PREFIX_TABLE (PREFIX_0FF7) },
2420 /* f8 */
2421 { "psubb", { MX, EM }, PREFIX_OPCODE },
2422 { "psubw", { MX, EM }, PREFIX_OPCODE },
2423 { "psubd", { MX, EM }, PREFIX_OPCODE },
2424 { "psubq", { MX, EM }, PREFIX_OPCODE },
2425 { "paddb", { MX, EM }, PREFIX_OPCODE },
2426 { "paddw", { MX, EM }, PREFIX_OPCODE },
2427 { "paddd", { MX, EM }, PREFIX_OPCODE },
2428 { "ud0S", { Gv, Ev }, 0 },
2429 };
2430
2431 static const bool onebyte_has_modrm[256] = {
2432 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2433 /* ------------------------------- */
2434 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2435 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2436 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2437 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2438 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2439 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2440 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2441 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2442 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2443 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2444 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2445 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2446 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2447 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2448 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2449 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2450 /* ------------------------------- */
2451 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2452 };
2453
2454 static const bool twobyte_has_modrm[256] = {
2455 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2456 /* ------------------------------- */
2457 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2458 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2459 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2460 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2461 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2462 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2463 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2464 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2465 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2466 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2467 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2468 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2469 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2470 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2471 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2472 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2473 /* ------------------------------- */
2474 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2475 };
2476
2477
2478 struct op
2479 {
2480 const char *name;
2481 unsigned int len;
2482 };
2483
2484 /* If we are accessing mod/rm/reg without need_modrm set, then the
2485 values are stale. Hitting this abort likely indicates that you
2486 need to update onebyte_has_modrm or twobyte_has_modrm. */
2487 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2488
2489 static const char intel_index16[][6] = {
2490 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2491 };
2492
2493 static const char att_names64[][8] = {
2494 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2495 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2496 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2497 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2498 };
2499 static const char att_names32[][8] = {
2500 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2501 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2502 "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2503 "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2504 };
2505 static const char att_names16[][8] = {
2506 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2507 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2508 "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2509 "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2510 };
2511 static const char att_names8[][8] = {
2512 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2513 };
2514 static const char att_names8rex[][8] = {
2515 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2516 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2517 "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2518 "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2519 };
2520 static const char att_names_seg[][4] = {
2521 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2522 };
2523 static const char att_index64[] = "%riz";
2524 static const char att_index32[] = "%eiz";
2525 static const char att_index16[][8] = {
2526 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2527 };
2528
2529 static const char att_names_mm[][8] = {
2530 "%mm0", "%mm1", "%mm2", "%mm3",
2531 "%mm4", "%mm5", "%mm6", "%mm7"
2532 };
2533
2534 static const char att_names_bnd[][8] = {
2535 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2536 };
2537
2538 static const char att_names_xmm[][8] = {
2539 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2540 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2541 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2542 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2543 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2544 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2545 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2546 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2547 };
2548
2549 static const char att_names_ymm[][8] = {
2550 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2551 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2552 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2553 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2554 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2555 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2556 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2557 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2558 };
2559
2560 static const char att_names_zmm[][8] = {
2561 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2562 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2563 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2564 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2565 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2566 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2567 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2568 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2569 };
2570
2571 static const char att_names_tmm[][8] = {
2572 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2573 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2574 };
2575
2576 static const char att_names_mask[][8] = {
2577 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2578 };
2579
2580 static const char *const names_rounding[] =
2581 {
2582 "{rn-",
2583 "{rd-",
2584 "{ru-",
2585 "{rz-"
2586 };
2587
2588 static const struct dis386 reg_table[][8] = {
2589 /* REG_80 */
2590 {
2591 { "addA", { Ebh1, Ib }, 0 },
2592 { "orA", { Ebh1, Ib }, 0 },
2593 { "adcA", { Ebh1, Ib }, 0 },
2594 { "sbbA", { Ebh1, Ib }, 0 },
2595 { "andA", { Ebh1, Ib }, 0 },
2596 { "subA", { Ebh1, Ib }, 0 },
2597 { "xorA", { Ebh1, Ib }, 0 },
2598 { "cmpA", { Eb, Ib }, 0 },
2599 },
2600 /* REG_81 */
2601 {
2602 { "addQ", { Evh1, Iv }, 0 },
2603 { "orQ", { Evh1, Iv }, 0 },
2604 { "adcQ", { Evh1, Iv }, 0 },
2605 { "sbbQ", { Evh1, Iv }, 0 },
2606 { "andQ", { Evh1, Iv }, 0 },
2607 { "subQ", { Evh1, Iv }, 0 },
2608 { "xorQ", { Evh1, Iv }, 0 },
2609 { "cmpQ", { Ev, Iv }, 0 },
2610 },
2611 /* REG_83 */
2612 {
2613 { "addQ", { Evh1, sIb }, 0 },
2614 { "orQ", { Evh1, sIb }, 0 },
2615 { "adcQ", { Evh1, sIb }, 0 },
2616 { "sbbQ", { Evh1, sIb }, 0 },
2617 { "andQ", { Evh1, sIb }, 0 },
2618 { "subQ", { Evh1, sIb }, 0 },
2619 { "xorQ", { Evh1, sIb }, 0 },
2620 { "cmpQ", { Ev, sIb }, 0 },
2621 },
2622 /* REG_8F */
2623 {
2624 { "pop{P|}", { stackEv }, 0 },
2625 { XOP_8F_TABLE () },
2626 { Bad_Opcode },
2627 { Bad_Opcode },
2628 { Bad_Opcode },
2629 { XOP_8F_TABLE () },
2630 },
2631 /* REG_C0 */
2632 {
2633 { "%NFrolA", { VexGb, Eb, Ib }, NO_PREFIX },
2634 { "%NFrorA", { VexGb, Eb, Ib }, NO_PREFIX },
2635 { "rclA", { VexGb, Eb, Ib }, NO_PREFIX },
2636 { "rcrA", { VexGb, Eb, Ib }, NO_PREFIX },
2637 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX },
2638 { "%NFshrA", { VexGb, Eb, Ib }, NO_PREFIX },
2639 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX },
2640 { "%NFsarA", { VexGb, Eb, Ib }, NO_PREFIX },
2641 },
2642 /* REG_C1 */
2643 {
2644 { "%NFrolQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2645 { "%NFrorQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2646 { "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2647 { "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2648 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2649 { "%NFshrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2650 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2651 { "%NFsarQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2652 },
2653 /* REG_C6 */
2654 {
2655 { "movA", { Ebh3, Ib }, 0 },
2656 { Bad_Opcode },
2657 { Bad_Opcode },
2658 { Bad_Opcode },
2659 { Bad_Opcode },
2660 { Bad_Opcode },
2661 { Bad_Opcode },
2662 { RM_TABLE (RM_C6_REG_7) },
2663 },
2664 /* REG_C7 */
2665 {
2666 { "movQ", { Evh3, Iv }, 0 },
2667 { Bad_Opcode },
2668 { Bad_Opcode },
2669 { Bad_Opcode },
2670 { Bad_Opcode },
2671 { Bad_Opcode },
2672 { Bad_Opcode },
2673 { RM_TABLE (RM_C7_REG_7) },
2674 },
2675 /* REG_D0 */
2676 {
2677 { "%NFrolA", { VexGb, Eb, I1 }, NO_PREFIX },
2678 { "%NFrorA", { VexGb, Eb, I1 }, NO_PREFIX },
2679 { "rclA", { VexGb, Eb, I1 }, NO_PREFIX },
2680 { "rcrA", { VexGb, Eb, I1 }, NO_PREFIX },
2681 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX },
2682 { "%NFshrA", { VexGb, Eb, I1 }, NO_PREFIX },
2683 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX },
2684 { "%NFsarA", { VexGb, Eb, I1 }, NO_PREFIX },
2685 },
2686 /* REG_D1 */
2687 {
2688 { "%NFrolQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2689 { "%NFrorQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2690 { "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2691 { "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2692 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2693 { "%NFshrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2694 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2695 { "%NFsarQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2696 },
2697 /* REG_D2 */
2698 {
2699 { "%NFrolA", { VexGb, Eb, CL }, NO_PREFIX },
2700 { "%NFrorA", { VexGb, Eb, CL }, NO_PREFIX },
2701 { "rclA", { VexGb, Eb, CL }, NO_PREFIX },
2702 { "rcrA", { VexGb, Eb, CL }, NO_PREFIX },
2703 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX },
2704 { "%NFshrA", { VexGb, Eb, CL }, NO_PREFIX },
2705 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX },
2706 { "%NFsarA", { VexGb, Eb, CL }, NO_PREFIX },
2707 },
2708 /* REG_D3 */
2709 {
2710 { "%NFrolQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2711 { "%NFrorQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2712 { "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2713 { "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2714 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2715 { "%NFshrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2716 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2717 { "%NFsarQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2718 },
2719 /* REG_F6 */
2720 {
2721 { "testA", { Eb, Ib }, 0 },
2722 { "testA", { Eb, Ib }, 0 },
2723 { "notA", { Ebh1 }, 0 },
2724 { "negA", { Ebh1 }, 0 },
2725 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2726 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2727 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2728 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2729 },
2730 /* REG_F7 */
2731 {
2732 { "testQ", { Ev, Iv }, 0 },
2733 { "testQ", { Ev, Iv }, 0 },
2734 { "notQ", { Evh1 }, 0 },
2735 { "negQ", { Evh1 }, 0 },
2736 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2737 { "imulQ", { Ev }, 0 },
2738 { "divQ", { Ev }, 0 },
2739 { "idivQ", { Ev }, 0 },
2740 },
2741 /* REG_FE */
2742 {
2743 { "incA", { Ebh1 }, 0 },
2744 { "decA", { Ebh1 }, 0 },
2745 },
2746 /* REG_FF */
2747 {
2748 { "incQ", { Evh1 }, 0 },
2749 { "decQ", { Evh1 }, 0 },
2750 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2751 { "{l|}call^", { indirEp }, 0 },
2752 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2753 { "{l|}jmp^", { indirEp }, 0 },
2754 { "push{P|}", { stackEv }, 0 },
2755 { Bad_Opcode },
2756 },
2757 /* REG_0F00 */
2758 {
2759 { "sldtD", { Sv }, 0 },
2760 { "strD", { Sv }, 0 },
2761 { "lldtD", { Sv }, 0 },
2762 { "ltrD", { Sv }, 0 },
2763 { "verrD", { Sv }, 0 },
2764 { "verwD", { Sv }, 0 },
2765 { X86_64_TABLE (X86_64_0F00_REG_6) },
2766 { Bad_Opcode },
2767 },
2768 /* REG_0F01 */
2769 {
2770 { MOD_TABLE (MOD_0F01_REG_0) },
2771 { MOD_TABLE (MOD_0F01_REG_1) },
2772 { MOD_TABLE (MOD_0F01_REG_2) },
2773 { MOD_TABLE (MOD_0F01_REG_3) },
2774 { "smswD", { Sv }, 0 },
2775 { MOD_TABLE (MOD_0F01_REG_5) },
2776 { "lmsw", { Ew }, 0 },
2777 { MOD_TABLE (MOD_0F01_REG_7) },
2778 },
2779 /* REG_0F0D */
2780 {
2781 { "prefetch", { Mb }, 0 },
2782 { "prefetchw", { Mb }, 0 },
2783 { "prefetchwt1", { Mb }, 0 },
2784 { "prefetch", { Mb }, 0 },
2785 { "prefetch", { Mb }, 0 },
2786 { "prefetch", { Mb }, 0 },
2787 { "prefetch", { Mb }, 0 },
2788 { "prefetch", { Mb }, 0 },
2789 },
2790 /* REG_0F18 */
2791 {
2792 { MOD_TABLE (MOD_0F18_REG_0) },
2793 { MOD_TABLE (MOD_0F18_REG_1) },
2794 { MOD_TABLE (MOD_0F18_REG_2) },
2795 { MOD_TABLE (MOD_0F18_REG_3) },
2796 { "nopQ", { Ev }, 0 },
2797 { "nopQ", { Ev }, 0 },
2798 { MOD_TABLE (MOD_0F18_REG_6) },
2799 { MOD_TABLE (MOD_0F18_REG_7) },
2800 },
2801 /* REG_0F1C_P_0_MOD_0 */
2802 {
2803 { "cldemote", { Mb }, 0 },
2804 { "nopQ", { Ev }, 0 },
2805 { "nopQ", { Ev }, 0 },
2806 { "nopQ", { Ev }, 0 },
2807 { "nopQ", { Ev }, 0 },
2808 { "nopQ", { Ev }, 0 },
2809 { "nopQ", { Ev }, 0 },
2810 { "nopQ", { Ev }, 0 },
2811 },
2812 /* REG_0F1E_P_1_MOD_3 */
2813 {
2814 { "nopQ", { Ev }, PREFIX_IGNORED },
2815 { "rdsspK", { Edq }, 0 },
2816 { "nopQ", { Ev }, PREFIX_IGNORED },
2817 { "nopQ", { Ev }, PREFIX_IGNORED },
2818 { "nopQ", { Ev }, PREFIX_IGNORED },
2819 { "nopQ", { Ev }, PREFIX_IGNORED },
2820 { "nopQ", { Ev }, PREFIX_IGNORED },
2821 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2822 },
2823 /* REG_0F38D8_PREFIX_1 */
2824 {
2825 { "aesencwide128kl", { M }, 0 },
2826 { "aesdecwide128kl", { M }, 0 },
2827 { "aesencwide256kl", { M }, 0 },
2828 { "aesdecwide256kl", { M }, 0 },
2829 },
2830 /* REG_0F3A0F_P_1 */
2831 {
2832 { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2833 },
2834 /* REG_0F71 */
2835 {
2836 { Bad_Opcode },
2837 { Bad_Opcode },
2838 { "psrlw", { Nq, Ib }, PREFIX_OPCODE },
2839 { Bad_Opcode },
2840 { "psraw", { Nq, Ib }, PREFIX_OPCODE },
2841 { Bad_Opcode },
2842 { "psllw", { Nq, Ib }, PREFIX_OPCODE },
2843 },
2844 /* REG_0F72 */
2845 {
2846 { Bad_Opcode },
2847 { Bad_Opcode },
2848 { "psrld", { Nq, Ib }, PREFIX_OPCODE },
2849 { Bad_Opcode },
2850 { "psrad", { Nq, Ib }, PREFIX_OPCODE },
2851 { Bad_Opcode },
2852 { "pslld", { Nq, Ib }, PREFIX_OPCODE },
2853 },
2854 /* REG_0F73 */
2855 {
2856 { Bad_Opcode },
2857 { Bad_Opcode },
2858 { "psrlq", { Nq, Ib }, PREFIX_OPCODE },
2859 { "psrldq", { Ux, Ib }, PREFIX_DATA },
2860 { Bad_Opcode },
2861 { Bad_Opcode },
2862 { "psllq", { Nq, Ib }, PREFIX_OPCODE },
2863 { "pslldq", { Ux, Ib }, PREFIX_DATA },
2864 },
2865 /* REG_0FA6 */
2866 {
2867 { PREFIX_TABLE (PREFIX_0FA6_REG_0) },
2868 { "xsha1", { { OP_0f07, 0 } }, 0 },
2869 { "xsha256", { { OP_0f07, 0 } }, 0 },
2870 { Bad_Opcode },
2871 { Bad_Opcode },
2872 { PREFIX_TABLE (PREFIX_0FA6_REG_5) },
2873 },
2874 /* REG_0FA7 */
2875 {
2876 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2877 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2878 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2879 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2880 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2881 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2882 { PREFIX_TABLE (PREFIX_0FA7_REG_6) },
2883 },
2884 /* REG_0FAE */
2885 {
2886 { MOD_TABLE (MOD_0FAE_REG_0) },
2887 { MOD_TABLE (MOD_0FAE_REG_1) },
2888 { MOD_TABLE (MOD_0FAE_REG_2) },
2889 { MOD_TABLE (MOD_0FAE_REG_3) },
2890 { MOD_TABLE (MOD_0FAE_REG_4) },
2891 { MOD_TABLE (MOD_0FAE_REG_5) },
2892 { MOD_TABLE (MOD_0FAE_REG_6) },
2893 { MOD_TABLE (MOD_0FAE_REG_7) },
2894 },
2895 /* REG_0FBA */
2896 {
2897 { Bad_Opcode },
2898 { Bad_Opcode },
2899 { Bad_Opcode },
2900 { Bad_Opcode },
2901 { "btQ", { Ev, Ib }, 0 },
2902 { "btsQ", { Evh1, Ib }, 0 },
2903 { "btrQ", { Evh1, Ib }, 0 },
2904 { "btcQ", { Evh1, Ib }, 0 },
2905 },
2906 /* REG_0FC7 */
2907 {
2908 { Bad_Opcode },
2909 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2910 { Bad_Opcode },
2911 { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2912 { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2913 { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2914 { MOD_TABLE (MOD_0FC7_REG_6) },
2915 { MOD_TABLE (MOD_0FC7_REG_7) },
2916 },
2917 /* REG_VEX_0F71 */
2918 {
2919 { Bad_Opcode },
2920 { Bad_Opcode },
2921 { "vpsrlw", { Vex, Ux, Ib }, PREFIX_DATA },
2922 { Bad_Opcode },
2923 { "vpsraw", { Vex, Ux, Ib }, PREFIX_DATA },
2924 { Bad_Opcode },
2925 { "vpsllw", { Vex, Ux, Ib }, PREFIX_DATA },
2926 },
2927 /* REG_VEX_0F72 */
2928 {
2929 { Bad_Opcode },
2930 { Bad_Opcode },
2931 { "vpsrld", { Vex, Ux, Ib }, PREFIX_DATA },
2932 { Bad_Opcode },
2933 { "vpsrad", { Vex, Ux, Ib }, PREFIX_DATA },
2934 { Bad_Opcode },
2935 { "vpslld", { Vex, Ux, Ib }, PREFIX_DATA },
2936 },
2937 /* REG_VEX_0F73 */
2938 {
2939 { Bad_Opcode },
2940 { Bad_Opcode },
2941 { "vpsrlq", { Vex, Ux, Ib }, PREFIX_DATA },
2942 { "vpsrldq", { Vex, Ux, Ib }, PREFIX_DATA },
2943 { Bad_Opcode },
2944 { Bad_Opcode },
2945 { "vpsllq", { Vex, Ux, Ib }, PREFIX_DATA },
2946 { "vpslldq", { Vex, Ux, Ib }, PREFIX_DATA },
2947 },
2948 /* REG_VEX_0FAE */
2949 {
2950 { Bad_Opcode },
2951 { Bad_Opcode },
2952 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
2953 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
2954 },
2955 /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2956 {
2957 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2958 },
2959 /* REG_VEX_0F38F3_L_0_P_0 */
2960 {
2961 { Bad_Opcode },
2962 { "%NFblsrS", { VexGdq, Edq }, 0 },
2963 { "%NFblsmskS", { VexGdq, Edq }, 0 },
2964 { "%NFblsiS", { VexGdq, Edq }, 0 },
2965 },
2966 /* REG_VEX_MAP7_F6_L_0_W_0 */
2967 {
2968 { X86_64_TABLE (X86_64_VEX_MAP7_F6_L_0_W_0_R_0) },
2969 },
2970 /* REG_VEX_MAP7_F8_L_0_W_0 */
2971 {
2972 { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
2973 },
2974 /* REG_XOP_09_01_L_0 */
2975 {
2976 { Bad_Opcode },
2977 { "blcfill", { VexGdq, Edq }, 0 },
2978 { "blsfill", { VexGdq, Edq }, 0 },
2979 { "blcs", { VexGdq, Edq }, 0 },
2980 { "tzmsk", { VexGdq, Edq }, 0 },
2981 { "blcic", { VexGdq, Edq }, 0 },
2982 { "blsic", { VexGdq, Edq }, 0 },
2983 { "t1mskc", { VexGdq, Edq }, 0 },
2984 },
2985 /* REG_XOP_09_02_L_0 */
2986 {
2987 { Bad_Opcode },
2988 { "blcmsk", { VexGdq, Edq }, 0 },
2989 { Bad_Opcode },
2990 { Bad_Opcode },
2991 { Bad_Opcode },
2992 { Bad_Opcode },
2993 { "blci", { VexGdq, Edq }, 0 },
2994 },
2995 /* REG_XOP_09_12_L_0 */
2996 {
2997 { "llwpcb", { Rdq }, 0 },
2998 { "slwpcb", { Rdq }, 0 },
2999 },
3000 /* REG_XOP_0A_12_L_0 */
3001 {
3002 { "lwpins", { VexGdq, Ed, Id }, 0 },
3003 { "lwpval", { VexGdq, Ed, Id }, 0 },
3004 },
3005
3006 #include "i386-dis-evex-reg.h"
3007 };
3008
3009 static const struct dis386 prefix_table[][4] = {
3010 /* PREFIX_90 */
3011 {
3012 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3013 { "pause", { XX }, 0 },
3014 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3015 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3016 },
3017
3018 /* PREFIX_0F00_REG_6_X86_64 */
3019 {
3020 { Bad_Opcode },
3021 { Bad_Opcode },
3022 { Bad_Opcode },
3023 { "lkgsD", { Sv }, 0 },
3024 },
3025
3026 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3027 {
3028 { "wrmsrns", { Skip_MODRM }, 0 },
3029 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3030 { Bad_Opcode },
3031 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3032 },
3033
3034 /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3035 {
3036 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3037 },
3038
3039 /* PREFIX_0F01_REG_1_RM_2 */
3040 {
3041 { "clac", { Skip_MODRM }, 0 },
3042 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3043 { Bad_Opcode },
3044 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3045 },
3046
3047 /* PREFIX_0F01_REG_1_RM_4 */
3048 {
3049 { Bad_Opcode },
3050 { Bad_Opcode },
3051 { "tdcall", { Skip_MODRM }, 0 },
3052 { Bad_Opcode },
3053 },
3054
3055 /* PREFIX_0F01_REG_1_RM_5 */
3056 {
3057 { Bad_Opcode },
3058 { Bad_Opcode },
3059 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3060 { Bad_Opcode },
3061 },
3062
3063 /* PREFIX_0F01_REG_1_RM_6 */
3064 {
3065 { Bad_Opcode },
3066 { Bad_Opcode },
3067 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3068 { Bad_Opcode },
3069 },
3070
3071 /* PREFIX_0F01_REG_1_RM_7 */
3072 {
3073 { "encls", { Skip_MODRM }, 0 },
3074 { Bad_Opcode },
3075 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3076 { Bad_Opcode },
3077 },
3078
3079 /* PREFIX_0F01_REG_3_RM_1 */
3080 {
3081 { "vmmcall", { Skip_MODRM }, 0 },
3082 { "vmgexit", { Skip_MODRM }, 0 },
3083 { Bad_Opcode },
3084 { "vmgexit", { Skip_MODRM }, 0 },
3085 },
3086
3087 /* PREFIX_0F01_REG_5_MOD_0 */
3088 {
3089 { Bad_Opcode },
3090 { "rstorssp", { Mq }, PREFIX_OPCODE },
3091 },
3092
3093 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3094 {
3095 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3096 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3097 { Bad_Opcode },
3098 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3099 },
3100
3101 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3102 {
3103 { Bad_Opcode },
3104 { Bad_Opcode },
3105 { Bad_Opcode },
3106 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3107 },
3108
3109 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3110 {
3111 { Bad_Opcode },
3112 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3113 },
3114
3115 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3116 {
3117 { Bad_Opcode },
3118 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3119 },
3120
3121 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3122 {
3123 { Bad_Opcode },
3124 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3125 },
3126
3127 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3128 {
3129 { "rdpkru", { Skip_MODRM }, 0 },
3130 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3131 },
3132
3133 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3134 {
3135 { "wrpkru", { Skip_MODRM }, 0 },
3136 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3137 },
3138
3139 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3140 {
3141 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3142 { "mcommit", { Skip_MODRM }, 0 },
3143 },
3144
3145 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3146 {
3147 { "rdpru", { Skip_MODRM }, 0 },
3148 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3149 },
3150
3151 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3152 {
3153 { "invlpgb", { Skip_MODRM }, 0 },
3154 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3155 { Bad_Opcode },
3156 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3157 },
3158
3159 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3160 {
3161 { "tlbsync", { Skip_MODRM }, 0 },
3162 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3163 { Bad_Opcode },
3164 { "pvalidate", { Skip_MODRM }, 0 },
3165 },
3166
3167 /* PREFIX_0F09 */
3168 {
3169 { "wbinvd", { XX }, 0 },
3170 { "wbnoinvd", { XX }, 0 },
3171 },
3172
3173 /* PREFIX_0F10 */
3174 {
3175 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3176 { "%XEVmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3177 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3178 { "%XEVmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3179 },
3180
3181 /* PREFIX_0F11 */
3182 {
3183 { "%XEVmovupX", { EXxS, XM }, 0 },
3184 { "%XEVmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3185 { "%XEVmovupX", { EXxS, XM }, 0 },
3186 { "%XEVmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3187 },
3188
3189 /* PREFIX_0F12 */
3190 {
3191 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3192 { "movsldup", { XM, EXx }, 0 },
3193 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
3194 { "movddup", { XM, EXq }, 0 },
3195 },
3196
3197 /* PREFIX_0F16 */
3198 {
3199 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3200 { "movshdup", { XM, EXx }, 0 },
3201 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
3202 },
3203
3204 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3205 {
3206 { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
3207 { "nopQ", { Ev }, 0 },
3208 { "nopQ", { Ev }, 0 },
3209 { "nopQ", { Ev }, 0 },
3210 },
3211
3212 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3213 {
3214 { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
3215 { "nopQ", { Ev }, 0 },
3216 { "nopQ", { Ev }, 0 },
3217 { "nopQ", { Ev }, 0 },
3218 },
3219
3220 /* PREFIX_0F1A */
3221 {
3222 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3223 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3224 { "bndmov", { Gbnd, Ebnd }, 0 },
3225 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3226 },
3227
3228 /* PREFIX_0F1B */
3229 {
3230 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3231 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3232 { "bndmov", { EbndS, Gbnd }, 0 },
3233 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3234 },
3235
3236 /* PREFIX_0F1C */
3237 {
3238 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3239 { "nopQ", { Ev }, PREFIX_IGNORED },
3240 { "nopQ", { Ev }, 0 },
3241 { "nopQ", { Ev }, PREFIX_IGNORED },
3242 },
3243
3244 /* PREFIX_0F1E */
3245 {
3246 { "nopQ", { Ev }, 0 },
3247 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3248 { "nopQ", { Ev }, 0 },
3249 { NULL, { XX }, PREFIX_IGNORED },
3250 },
3251
3252 /* PREFIX_0F2A */
3253 {
3254 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3255 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3256 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3257 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3258 },
3259
3260 /* PREFIX_0F2B */
3261 {
3262 { "movntps", { Mx, XM }, 0 },
3263 { "movntss", { Md, XM }, 0 },
3264 { "movntpd", { Mx, XM }, 0 },
3265 { "movntsd", { Mq, XM }, 0 },
3266 },
3267
3268 /* PREFIX_0F2C */
3269 {
3270 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3271 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3272 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3273 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3274 },
3275
3276 /* PREFIX_0F2D */
3277 {
3278 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3279 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3280 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3281 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3282 },
3283
3284 /* PREFIX_0F2E */
3285 {
3286 { "%XEVucomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3287 { Bad_Opcode },
3288 { "%XEVucomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3289 },
3290
3291 /* PREFIX_0F2F */
3292 {
3293 { "%XEVcomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3294 { Bad_Opcode },
3295 { "%XEVcomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3296 },
3297
3298 /* PREFIX_0F51 */
3299 {
3300 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3301 { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3302 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3303 { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3304 },
3305
3306 /* PREFIX_0F52 */
3307 {
3308 { "Vrsqrtps", { XM, EXx }, 0 },
3309 { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3310 },
3311
3312 /* PREFIX_0F53 */
3313 {
3314 { "Vrcpps", { XM, EXx }, 0 },
3315 { "Vrcpss", { XMScalar, VexScalar, EXd }, 0 },
3316 },
3317
3318 /* PREFIX_0F58 */
3319 {
3320 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3321 { "%XEVadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3322 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3323 { "%XEVadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3324 },
3325
3326 /* PREFIX_0F59 */
3327 {
3328 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3329 { "%XEVmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3330 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3331 { "%XEVmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3332 },
3333
3334 /* PREFIX_0F5A */
3335 {
3336 { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3337 { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3338 { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3339 { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3340 },
3341
3342 /* PREFIX_0F5B */
3343 {
3344 { "Vcvtdq2ps", { XM, EXx }, 0 },
3345 { "Vcvttps2dq", { XM, EXx }, 0 },
3346 { "Vcvtps2dq", { XM, EXx }, 0 },
3347 },
3348
3349 /* PREFIX_0F5C */
3350 {
3351 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3352 { "%XEVsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3353 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3354 { "%XEVsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3355 },
3356
3357 /* PREFIX_0F5D */
3358 {
3359 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3360 { "%XEVmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3361 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3362 { "%XEVmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3363 },
3364
3365 /* PREFIX_0F5E */
3366 {
3367 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3368 { "%XEVdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3369 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3370 { "%XEVdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3371 },
3372
3373 /* PREFIX_0F5F */
3374 {
3375 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3376 { "%XEVmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3377 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3378 { "%XEVmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3379 },
3380
3381 /* PREFIX_0F60 */
3382 {
3383 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3384 { Bad_Opcode },
3385 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3386 },
3387
3388 /* PREFIX_0F61 */
3389 {
3390 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3391 { Bad_Opcode },
3392 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3393 },
3394
3395 /* PREFIX_0F62 */
3396 {
3397 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3398 { Bad_Opcode },
3399 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3400 },
3401
3402 /* PREFIX_0F6F */
3403 {
3404 { "movq", { MX, EM }, PREFIX_OPCODE },
3405 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3406 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3407 },
3408
3409 /* PREFIX_0F70 */
3410 {
3411 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3412 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3413 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3414 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3415 },
3416
3417 /* PREFIX_0F78 */
3418 {
3419 {"vmread", { Em, Gm }, 0 },
3420 { Bad_Opcode },
3421 {"extrq", { Uxmm, Ib, Ib }, 0 },
3422 {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3423 },
3424
3425 /* PREFIX_0F79 */
3426 {
3427 {"vmwrite", { Gm, Em }, 0 },
3428 { Bad_Opcode },
3429 {"extrq", { XM, Uxmm }, 0 },
3430 {"insertq", { XM, Uxmm }, 0 },
3431 },
3432
3433 /* PREFIX_0F7C */
3434 {
3435 { Bad_Opcode },
3436 { Bad_Opcode },
3437 { "Vhaddpd", { XM, Vex, EXx }, 0 },
3438 { "Vhaddps", { XM, Vex, EXx }, 0 },
3439 },
3440
3441 /* PREFIX_0F7D */
3442 {
3443 { Bad_Opcode },
3444 { Bad_Opcode },
3445 { "Vhsubpd", { XM, Vex, EXx }, 0 },
3446 { "Vhsubps", { XM, Vex, EXx }, 0 },
3447 },
3448
3449 /* PREFIX_0F7E */
3450 {
3451 { "movK", { Edq, MX }, PREFIX_OPCODE },
3452 { "movq", { XM, EXq }, PREFIX_OPCODE },
3453 { "movK", { Edq, XM }, PREFIX_OPCODE },
3454 },
3455
3456 /* PREFIX_0F7F */
3457 {
3458 { "movq", { EMS, MX }, PREFIX_OPCODE },
3459 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3460 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3461 },
3462
3463 /* PREFIX_0FA6_REG_0 */
3464 {
3465 { Bad_Opcode },
3466 { "montmul", { { MONTMUL_Fixup, 0 } }, 0},
3467 { Bad_Opcode },
3468 { "sm2", { Skip_MODRM }, 0 },
3469 },
3470
3471 /* PREFIX_0FA6_REG_5 */
3472 {
3473 { Bad_Opcode },
3474 { "sm3", { Skip_MODRM }, 0 },
3475 },
3476
3477 /* PREFIX_0FA7_REG_6 */
3478 {
3479 { Bad_Opcode },
3480 { "sm4", { Skip_MODRM }, 0 },
3481 },
3482
3483 /* PREFIX_0FAE_REG_0_MOD_3 */
3484 {
3485 { Bad_Opcode },
3486 { "rdfsbase", { Ev }, 0 },
3487 },
3488
3489 /* PREFIX_0FAE_REG_1_MOD_3 */
3490 {
3491 { Bad_Opcode },
3492 { "rdgsbase", { Ev }, 0 },
3493 },
3494
3495 /* PREFIX_0FAE_REG_2_MOD_3 */
3496 {
3497 { Bad_Opcode },
3498 { "wrfsbase", { Ev }, 0 },
3499 },
3500
3501 /* PREFIX_0FAE_REG_3_MOD_3 */
3502 {
3503 { Bad_Opcode },
3504 { "wrgsbase", { Ev }, 0 },
3505 },
3506
3507 /* PREFIX_0FAE_REG_4_MOD_0 */
3508 {
3509 { "xsave", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3510 { "ptwrite{%LQ|}", { Edq }, 0 },
3511 },
3512
3513 /* PREFIX_0FAE_REG_4_MOD_3 */
3514 {
3515 { Bad_Opcode },
3516 { "ptwrite{%LQ|}", { Edq }, 0 },
3517 },
3518
3519 /* PREFIX_0FAE_REG_5_MOD_3 */
3520 {
3521 { "lfence", { Skip_MODRM }, 0 },
3522 { "incsspK", { Edq }, PREFIX_OPCODE },
3523 },
3524
3525 /* PREFIX_0FAE_REG_6_MOD_0 */
3526 {
3527 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3528 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3529 { "clwb", { Mb }, PREFIX_OPCODE },
3530 },
3531
3532 /* PREFIX_0FAE_REG_6_MOD_3 */
3533 {
3534 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3535 { "umonitor", { Eva }, PREFIX_OPCODE },
3536 { "tpause", { Edq }, PREFIX_OPCODE },
3537 { "umwait", { Edq }, PREFIX_OPCODE },
3538 },
3539
3540 /* PREFIX_0FAE_REG_7_MOD_0 */
3541 {
3542 { "clflush", { Mb }, 0 },
3543 { Bad_Opcode },
3544 { "clflushopt", { Mb }, 0 },
3545 },
3546
3547 /* PREFIX_0FB8 */
3548 {
3549 { Bad_Opcode },
3550 { "popcntS", { Gv, Ev }, 0 },
3551 },
3552
3553 /* PREFIX_0FBC */
3554 {
3555 { "bsfS", { Gv, Ev }, 0 },
3556 { "tzcntS", { Gv, Ev }, 0 },
3557 { "bsfS", { Gv, Ev }, 0 },
3558 },
3559
3560 /* PREFIX_0FBD */
3561 {
3562 { "bsrS", { Gv, Ev }, 0 },
3563 { "lzcntS", { Gv, Ev }, 0 },
3564 { "bsrS", { Gv, Ev }, 0 },
3565 },
3566
3567 /* PREFIX_0FC2 */
3568 {
3569 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3570 { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3571 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3572 { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3573 },
3574
3575 /* PREFIX_0FC7_REG_6_MOD_0 */
3576 {
3577 { "vmptrld",{ Mq }, 0 },
3578 { "vmxon", { Mq }, 0 },
3579 { "vmclear",{ Mq }, 0 },
3580 },
3581
3582 /* PREFIX_0FC7_REG_6_MOD_3 */
3583 {
3584 { "rdrand", { Ev }, 0 },
3585 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3586 { "rdrand", { Ev }, 0 }
3587 },
3588
3589 /* PREFIX_0FC7_REG_7_MOD_3 */
3590 {
3591 { "rdseed", { Ev }, 0 },
3592 { "rdpid", { Em }, 0 },
3593 { "rdseed", { Ev }, 0 },
3594 },
3595
3596 /* PREFIX_0FD0 */
3597 {
3598 { Bad_Opcode },
3599 { Bad_Opcode },
3600 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3601 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3602 },
3603
3604 /* PREFIX_0FD6 */
3605 {
3606 { Bad_Opcode },
3607 { "movq2dq",{ XM, Nq }, 0 },
3608 { "movq", { EXqS, XM }, 0 },
3609 { "movdq2q",{ MX, Ux }, 0 },
3610 },
3611
3612 /* PREFIX_0FE6 */
3613 {
3614 { Bad_Opcode },
3615 { "Vcvtdq2pd", { XM, EXxmmq }, 0 },
3616 { "Vcvttpd2dq%XY", { XMM, EXx }, 0 },
3617 { "Vcvtpd2dq%XY", { XMM, EXx }, 0 },
3618 },
3619
3620 /* PREFIX_0FE7 */
3621 {
3622 { "movntq", { Mq, MX }, 0 },
3623 { Bad_Opcode },
3624 { "movntdq", { Mx, XM }, 0 },
3625 },
3626
3627 /* PREFIX_0FF0 */
3628 {
3629 { Bad_Opcode },
3630 { Bad_Opcode },
3631 { Bad_Opcode },
3632 { "Vlddqu", { XM, M }, 0 },
3633 },
3634
3635 /* PREFIX_0FF7 */
3636 {
3637 { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3638 { Bad_Opcode },
3639 { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3640 },
3641
3642 /* PREFIX_0F38D8 */
3643 {
3644 { Bad_Opcode },
3645 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3646 },
3647
3648 /* PREFIX_0F38DC */
3649 {
3650 { Bad_Opcode },
3651 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3652 { "aesenc", { XM, EXx }, 0 },
3653 },
3654
3655 /* PREFIX_0F38DD */
3656 {
3657 { Bad_Opcode },
3658 { "aesdec128kl", { XM, M }, 0 },
3659 { "aesenclast", { XM, EXx }, 0 },
3660 },
3661
3662 /* PREFIX_0F38DE */
3663 {
3664 { Bad_Opcode },
3665 { "aesenc256kl", { XM, M }, 0 },
3666 { "aesdec", { XM, EXx }, 0 },
3667 },
3668
3669 /* PREFIX_0F38DF */
3670 {
3671 { Bad_Opcode },
3672 { "aesdec256kl", { XM, M }, 0 },
3673 { "aesdeclast", { XM, EXx }, 0 },
3674 },
3675
3676 /* PREFIX_0F38F0 */
3677 {
3678 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3679 { Bad_Opcode },
3680 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3681 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3682 },
3683
3684 /* PREFIX_0F38F1 */
3685 {
3686 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3687 { Bad_Opcode },
3688 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3689 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3690 },
3691
3692 /* PREFIX_0F38F6 */
3693 {
3694 { "wrssK", { M, Gdq }, 0 },
3695 { "adoxL", { VexGdq, Gdq, Edq }, 0 },
3696 { "adcxL", { VexGdq, Gdq, Edq }, 0 },
3697 { Bad_Opcode },
3698 },
3699
3700 /* PREFIX_0F38F8_M_0 */
3701 {
3702 { Bad_Opcode },
3703 { "enqcmds", { Gva, M }, 0 },
3704 { "movdir64b", { Gva, M }, 0 },
3705 { "enqcmd", { Gva, M }, 0 },
3706 },
3707
3708 /* PREFIX_0F38F8_M_1_X86_64 */
3709 {
3710 { Bad_Opcode },
3711 { "uwrmsr", { Gq, Rq }, 0 },
3712 { Bad_Opcode },
3713 { "urdmsr", { Rq, Gq }, 0 },
3714 },
3715
3716 /* PREFIX_0F38FA */
3717 {
3718 { Bad_Opcode },
3719 { "encodekey128", { Gd, Rd }, 0 },
3720 },
3721
3722 /* PREFIX_0F38FB */
3723 {
3724 { Bad_Opcode },
3725 { "encodekey256", { Gd, Rd }, 0 },
3726 },
3727
3728 /* PREFIX_0F38FC */
3729 {
3730 { "aadd", { Mdq, Gdq }, 0 },
3731 { "axor", { Mdq, Gdq }, 0 },
3732 { "aand", { Mdq, Gdq }, 0 },
3733 { "aor", { Mdq, Gdq }, 0 },
3734 },
3735
3736 /* PREFIX_0F3A0F */
3737 {
3738 { Bad_Opcode },
3739 { REG_TABLE (REG_0F3A0F_P_1) },
3740 },
3741
3742 /* PREFIX_VEX_0F12 */
3743 {
3744 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3745 { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3746 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3747 { "%XEvmov%XDdup", { XM, EXymmq }, 0 },
3748 },
3749
3750 /* PREFIX_VEX_0F16 */
3751 {
3752 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3753 { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3754 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3755 },
3756
3757 /* PREFIX_VEX_0F2A */
3758 {
3759 { Bad_Opcode },
3760 { "%XEvcvtsi2ssY{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3761 { Bad_Opcode },
3762 { "%XEvcvtsi2sdY{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3763 },
3764
3765 /* PREFIX_VEX_0F2C */
3766 {
3767 { Bad_Opcode },
3768 { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3769 { Bad_Opcode },
3770 { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3771 },
3772
3773 /* PREFIX_VEX_0F2D */
3774 {
3775 { Bad_Opcode },
3776 { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3777 { Bad_Opcode },
3778 { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3779 },
3780
3781 /* PREFIX_VEX_0F41_L_1_W_0 */
3782 {
3783 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
3784 { Bad_Opcode },
3785 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
3786 },
3787
3788 /* PREFIX_VEX_0F41_L_1_W_1 */
3789 {
3790 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
3791 { Bad_Opcode },
3792 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
3793 },
3794
3795 /* PREFIX_VEX_0F42_L_1_W_0 */
3796 {
3797 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
3798 { Bad_Opcode },
3799 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
3800 },
3801
3802 /* PREFIX_VEX_0F42_L_1_W_1 */
3803 {
3804 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
3805 { Bad_Opcode },
3806 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
3807 },
3808
3809 /* PREFIX_VEX_0F44_L_0_W_0 */
3810 {
3811 { "knotw", { MaskG, MaskR }, 0 },
3812 { Bad_Opcode },
3813 { "knotb", { MaskG, MaskR }, 0 },
3814 },
3815
3816 /* PREFIX_VEX_0F44_L_0_W_1 */
3817 {
3818 { "knotq", { MaskG, MaskR }, 0 },
3819 { Bad_Opcode },
3820 { "knotd", { MaskG, MaskR }, 0 },
3821 },
3822
3823 /* PREFIX_VEX_0F45_L_1_W_0 */
3824 {
3825 { "korw", { MaskG, MaskVex, MaskR }, 0 },
3826 { Bad_Opcode },
3827 { "korb", { MaskG, MaskVex, MaskR }, 0 },
3828 },
3829
3830 /* PREFIX_VEX_0F45_L_1_W_1 */
3831 {
3832 { "korq", { MaskG, MaskVex, MaskR }, 0 },
3833 { Bad_Opcode },
3834 { "kord", { MaskG, MaskVex, MaskR }, 0 },
3835 },
3836
3837 /* PREFIX_VEX_0F46_L_1_W_0 */
3838 {
3839 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
3840 { Bad_Opcode },
3841 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
3842 },
3843
3844 /* PREFIX_VEX_0F46_L_1_W_1 */
3845 {
3846 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
3847 { Bad_Opcode },
3848 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
3849 },
3850
3851 /* PREFIX_VEX_0F47_L_1_W_0 */
3852 {
3853 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
3854 { Bad_Opcode },
3855 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
3856 },
3857
3858 /* PREFIX_VEX_0F47_L_1_W_1 */
3859 {
3860 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
3861 { Bad_Opcode },
3862 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
3863 },
3864
3865 /* PREFIX_VEX_0F4A_L_1_W_0 */
3866 {
3867 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
3868 { Bad_Opcode },
3869 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
3870 },
3871
3872 /* PREFIX_VEX_0F4A_L_1_W_1 */
3873 {
3874 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
3875 { Bad_Opcode },
3876 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
3877 },
3878
3879 /* PREFIX_VEX_0F4B_L_1_W_0 */
3880 {
3881 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
3882 { Bad_Opcode },
3883 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
3884 },
3885
3886 /* PREFIX_VEX_0F4B_L_1_W_1 */
3887 {
3888 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
3889 },
3890
3891 /* PREFIX_VEX_0F6F */
3892 {
3893 { Bad_Opcode },
3894 { "vmovdqu", { XM, EXx }, 0 },
3895 { "vmovdqa", { XM, EXx }, 0 },
3896 },
3897
3898 /* PREFIX_VEX_0F70 */
3899 {
3900 { Bad_Opcode },
3901 { "vpshufhw", { XM, EXx, Ib }, 0 },
3902 { "vpshufd", { XM, EXx, Ib }, 0 },
3903 { "vpshuflw", { XM, EXx, Ib }, 0 },
3904 },
3905
3906 /* PREFIX_VEX_0F7E */
3907 {
3908 { Bad_Opcode },
3909 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3910 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3911 },
3912
3913 /* PREFIX_VEX_0F7F */
3914 {
3915 { Bad_Opcode },
3916 { "vmovdqu", { EXxS, XM }, 0 },
3917 { "vmovdqa", { EXxS, XM }, 0 },
3918 },
3919
3920 /* PREFIX_VEX_0F90_L_0_W_0 */
3921 {
3922 { "%XEkmovw", { MaskG, MaskE }, 0 },
3923 { Bad_Opcode },
3924 { "%XEkmovb", { MaskG, MaskBDE }, 0 },
3925 },
3926
3927 /* PREFIX_VEX_0F90_L_0_W_1 */
3928 {
3929 { "%XEkmovq", { MaskG, MaskE }, 0 },
3930 { Bad_Opcode },
3931 { "%XEkmovd", { MaskG, MaskBDE }, 0 },
3932 },
3933
3934 /* PREFIX_VEX_0F91_L_0_W_0 */
3935 {
3936 { "%XEkmovw", { Mw, MaskG }, 0 },
3937 { Bad_Opcode },
3938 { "%XEkmovb", { Mb, MaskG }, 0 },
3939 },
3940
3941 /* PREFIX_VEX_0F91_L_0_W_1 */
3942 {
3943 { "%XEkmovq", { Mq, MaskG }, 0 },
3944 { Bad_Opcode },
3945 { "%XEkmovd", { Md, MaskG }, 0 },
3946 },
3947
3948 /* PREFIX_VEX_0F92_L_0_W_0 */
3949 {
3950 { "%XEkmovw", { MaskG, Rdq }, 0 },
3951 { Bad_Opcode },
3952 { "%XEkmovb", { MaskG, Rdq }, 0 },
3953 { "%XEkmovd", { MaskG, Rdq }, 0 },
3954 },
3955
3956 /* PREFIX_VEX_0F92_L_0_W_1 */
3957 {
3958 { Bad_Opcode },
3959 { Bad_Opcode },
3960 { Bad_Opcode },
3961 { "%XEkmovK", { MaskG, Rdq }, 0 },
3962 },
3963
3964 /* PREFIX_VEX_0F93_L_0_W_0 */
3965 {
3966 { "%XEkmovw", { Gdq, MaskR }, 0 },
3967 { Bad_Opcode },
3968 { "%XEkmovb", { Gdq, MaskR }, 0 },
3969 { "%XEkmovd", { Gdq, MaskR }, 0 },
3970 },
3971
3972 /* PREFIX_VEX_0F93_L_0_W_1 */
3973 {
3974 { Bad_Opcode },
3975 { Bad_Opcode },
3976 { Bad_Opcode },
3977 { "%XEkmovK", { Gdq, MaskR }, 0 },
3978 },
3979
3980 /* PREFIX_VEX_0F98_L_0_W_0 */
3981 {
3982 { "kortestw", { MaskG, MaskR }, 0 },
3983 { Bad_Opcode },
3984 { "kortestb", { MaskG, MaskR }, 0 },
3985 },
3986
3987 /* PREFIX_VEX_0F98_L_0_W_1 */
3988 {
3989 { "kortestq", { MaskG, MaskR }, 0 },
3990 { Bad_Opcode },
3991 { "kortestd", { MaskG, MaskR }, 0 },
3992 },
3993
3994 /* PREFIX_VEX_0F99_L_0_W_0 */
3995 {
3996 { "ktestw", { MaskG, MaskR }, 0 },
3997 { Bad_Opcode },
3998 { "ktestb", { MaskG, MaskR }, 0 },
3999 },
4000
4001 /* PREFIX_VEX_0F99_L_0_W_1 */
4002 {
4003 { "ktestq", { MaskG, MaskR }, 0 },
4004 { Bad_Opcode },
4005 { "ktestd", { MaskG, MaskR }, 0 },
4006 },
4007
4008 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
4009 {
4010 { "ldtilecfg", { M }, 0 },
4011 { Bad_Opcode },
4012 { "sttilecfg", { M }, 0 },
4013 },
4014
4015 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
4016 {
4017 { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
4018 { Bad_Opcode },
4019 { Bad_Opcode },
4020 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
4021 },
4022
4023 /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
4024 {
4025 { Bad_Opcode },
4026 { "tilestored", { MVexSIBMEM, TMM }, 0 },
4027 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
4028 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
4029 },
4030
4031 /* PREFIX_VEX_0F3850_W_0 */
4032 {
4033 { "%XEvpdpbuud", { XM, Vex, EXx }, 0 },
4034 { "%XEvpdpbsud", { XM, Vex, EXx }, 0 },
4035 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 },
4036 { "%XEvpdpbssd", { XM, Vex, EXx }, 0 },
4037 },
4038
4039 /* PREFIX_VEX_0F3851_W_0 */
4040 {
4041 { "%XEvpdpbuuds", { XM, Vex, EXx }, 0 },
4042 { "%XEvpdpbsuds", { XM, Vex, EXx }, 0 },
4043 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
4044 { "%XEvpdpbssds", { XM, Vex, EXx }, 0 },
4045 },
4046 /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4047 {
4048 { Bad_Opcode },
4049 { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4050 { Bad_Opcode },
4051 { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4052 },
4053
4054 /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4055 {
4056 { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4057 { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4058 { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4059 { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4060 },
4061
4062 /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4063 {
4064 { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4065 { Bad_Opcode },
4066 { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4067 },
4068
4069 /* PREFIX_VEX_0F3872 */
4070 {
4071 { Bad_Opcode },
4072 { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4073 },
4074
4075 /* PREFIX_VEX_0F38B0_W_0 */
4076 {
4077 { "vcvtneoph2ps", { XM, Mx }, 0 },
4078 { "vcvtneebf162ps", { XM, Mx }, 0 },
4079 { "vcvtneeph2ps", { XM, Mx }, 0 },
4080 { "vcvtneobf162ps", { XM, Mx }, 0 },
4081 },
4082
4083 /* PREFIX_VEX_0F38B1_W_0 */
4084 {
4085 { Bad_Opcode },
4086 { "vbcstnebf162ps", { XM, Mw }, 0 },
4087 { "vbcstnesh2ps", { XM, Mw }, 0 },
4088 },
4089
4090 /* PREFIX_VEX_0F38D2_W_0 */
4091 {
4092 { "%XEvpdpwuud", { XM, Vex, EXx }, 0 },
4093 { "%XEvpdpwsud", { XM, Vex, EXx }, 0 },
4094 { "%XEvpdpwusd", { XM, Vex, EXx }, 0 },
4095 },
4096
4097 /* PREFIX_VEX_0F38D3_W_0 */
4098 {
4099 { "%XEvpdpwuuds", { XM, Vex, EXx }, 0 },
4100 { "%XEvpdpwsuds", { XM, Vex, EXx }, 0 },
4101 { "%XEvpdpwusds", { XM, Vex, EXx }, 0 },
4102 },
4103
4104 /* PREFIX_VEX_0F38CB */
4105 {
4106 { Bad_Opcode },
4107 { Bad_Opcode },
4108 { Bad_Opcode },
4109 { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4110 },
4111
4112 /* PREFIX_VEX_0F38CC */
4113 {
4114 { Bad_Opcode },
4115 { Bad_Opcode },
4116 { Bad_Opcode },
4117 { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4118 },
4119
4120 /* PREFIX_VEX_0F38CD */
4121 {
4122 { Bad_Opcode },
4123 { Bad_Opcode },
4124 { Bad_Opcode },
4125 { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4126 },
4127
4128 /* PREFIX_VEX_0F38DA_W_0 */
4129 {
4130 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4131 { "vsm4key4", { XM, Vex, EXx }, 0 },
4132 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4133 { "vsm4rnds4", { XM, Vex, EXx }, 0 },
4134 },
4135
4136 /* PREFIX_VEX_0F38F2_L_0 */
4137 {
4138 { "%NFandnS", { Gdq, VexGdq, Edq }, 0 },
4139 },
4140
4141 /* PREFIX_VEX_0F38F3_L_0 */
4142 {
4143 { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4144 },
4145
4146 /* PREFIX_VEX_0F38F5_L_0 */
4147 {
4148 { "%NFbzhiS", { Gdq, Edq, VexGdq }, 0 },
4149 { "%XEpextS", { Gdq, VexGdq, Edq }, 0 },
4150 { Bad_Opcode },
4151 { "%XEpdepS", { Gdq, VexGdq, Edq }, 0 },
4152 },
4153
4154 /* PREFIX_VEX_0F38F6_L_0 */
4155 {
4156 { Bad_Opcode },
4157 { Bad_Opcode },
4158 { Bad_Opcode },
4159 { "%XEmulxS", { Gdq, VexGdq, Edq }, 0 },
4160 },
4161
4162 /* PREFIX_VEX_0F38F7_L_0 */
4163 {
4164 { "%NFbextrS", { Gdq, Edq, VexGdq }, 0 },
4165 { "%XEsarxS", { Gdq, Edq, VexGdq }, 0 },
4166 { "%XEshlxS", { Gdq, Edq, VexGdq }, 0 },
4167 { "%XEshrxS", { Gdq, Edq, VexGdq }, 0 },
4168 },
4169
4170 /* PREFIX_VEX_0F3AF0_L_0 */
4171 {
4172 { Bad_Opcode },
4173 { Bad_Opcode },
4174 { Bad_Opcode },
4175 { "%XErorxS", { Gdq, Edq, Ib }, 0 },
4176 },
4177
4178 /* PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64 */
4179 {
4180 { Bad_Opcode },
4181 { "wrmsrns", { Skip_MODRM, Id, Rq }, 0 },
4182 { Bad_Opcode },
4183 { "rdmsr", { Rq, Id }, 0 },
4184 },
4185
4186 /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4187 {
4188 { Bad_Opcode },
4189 { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4190 { Bad_Opcode },
4191 { "urdmsr", { Rq, Id }, 0 },
4192 },
4193
4194 #include "i386-dis-evex-prefix.h"
4195 };
4196
4197 static const struct dis386 x86_64_table[][2] = {
4198 /* X86_64_06 */
4199 {
4200 { "pushP", { es }, 0 },
4201 },
4202
4203 /* X86_64_07 */
4204 {
4205 { "popP", { es }, 0 },
4206 },
4207
4208 /* X86_64_0E */
4209 {
4210 { "pushP", { cs }, 0 },
4211 },
4212
4213 /* X86_64_16 */
4214 {
4215 { "pushP", { ss }, 0 },
4216 },
4217
4218 /* X86_64_17 */
4219 {
4220 { "popP", { ss }, 0 },
4221 },
4222
4223 /* X86_64_1E */
4224 {
4225 { "pushP", { ds }, 0 },
4226 },
4227
4228 /* X86_64_1F */
4229 {
4230 { "popP", { ds }, 0 },
4231 },
4232
4233 /* X86_64_27 */
4234 {
4235 { "daa", { XX }, 0 },
4236 },
4237
4238 /* X86_64_2F */
4239 {
4240 { "das", { XX }, 0 },
4241 },
4242
4243 /* X86_64_37 */
4244 {
4245 { "aaa", { XX }, 0 },
4246 },
4247
4248 /* X86_64_3F */
4249 {
4250 { "aas", { XX }, 0 },
4251 },
4252
4253 /* X86_64_60 */
4254 {
4255 { "pushaP", { XX }, 0 },
4256 },
4257
4258 /* X86_64_61 */
4259 {
4260 { "popaP", { XX }, 0 },
4261 },
4262
4263 /* X86_64_62 */
4264 {
4265 { MOD_TABLE (MOD_62_32BIT) },
4266 { EVEX_TABLE () },
4267 },
4268
4269 /* X86_64_63 */
4270 {
4271 { "arplS", { Sv, Gv }, 0 },
4272 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4273 },
4274
4275 /* X86_64_6D */
4276 {
4277 { "ins{R|}", { Yzr, indirDX }, 0 },
4278 { "ins{G|}", { Yzr, indirDX }, 0 },
4279 },
4280
4281 /* X86_64_6F */
4282 {
4283 { "outs{R|}", { indirDXr, Xz }, 0 },
4284 { "outs{G|}", { indirDXr, Xz }, 0 },
4285 },
4286
4287 /* X86_64_82 */
4288 {
4289 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4290 { REG_TABLE (REG_80) },
4291 },
4292
4293 /* X86_64_9A */
4294 {
4295 { "{l|}call{P|}", { Ap }, 0 },
4296 },
4297
4298 /* X86_64_C2 */
4299 {
4300 { "retP", { Iw, BND }, 0 },
4301 { "ret@", { Iw, BND }, 0 },
4302 },
4303
4304 /* X86_64_C3 */
4305 {
4306 { "retP", { BND }, 0 },
4307 { "ret@", { BND }, 0 },
4308 },
4309
4310 /* X86_64_C4 */
4311 {
4312 { MOD_TABLE (MOD_C4_32BIT) },
4313 { VEX_C4_TABLE () },
4314 },
4315
4316 /* X86_64_C5 */
4317 {
4318 { MOD_TABLE (MOD_C5_32BIT) },
4319 { VEX_C5_TABLE () },
4320 },
4321
4322 /* X86_64_CE */
4323 {
4324 { "into", { XX }, 0 },
4325 },
4326
4327 /* X86_64_D4 */
4328 {
4329 { "aam", { Ib }, 0 },
4330 },
4331
4332 /* X86_64_D5 */
4333 {
4334 { "aad", { Ib }, 0 },
4335 },
4336
4337 /* X86_64_E8 */
4338 {
4339 { "callP", { Jv, BND }, 0 },
4340 { "call@", { Jv, BND }, PREFIX_REX2_ILLEGAL }
4341 },
4342
4343 /* X86_64_E9 */
4344 {
4345 { "jmpP", { Jv, BND }, 0 },
4346 { "jmp@", { Jv, BND }, PREFIX_REX2_ILLEGAL }
4347 },
4348
4349 /* X86_64_EA */
4350 {
4351 { "{l|}jmp{P|}", { Ap }, 0 },
4352 },
4353
4354 /* X86_64_0F00_REG_6 */
4355 {
4356 { Bad_Opcode },
4357 { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4358 },
4359
4360 /* X86_64_0F01_REG_0 */
4361 {
4362 { "sgdt{Q|Q}", { M }, 0 },
4363 { "sgdt", { M }, 0 },
4364 },
4365
4366 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4367 {
4368 { Bad_Opcode },
4369 { "wrmsrlist", { Skip_MODRM }, 0 },
4370 },
4371
4372 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4373 {
4374 { Bad_Opcode },
4375 { "rdmsrlist", { Skip_MODRM }, 0 },
4376 },
4377
4378 /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4379 {
4380 { Bad_Opcode },
4381 { "pbndkb", { Skip_MODRM }, 0 },
4382 },
4383
4384 /* X86_64_0F01_REG_1 */
4385 {
4386 { "sidt{Q|Q}", { M }, 0 },
4387 { "sidt", { M }, 0 },
4388 },
4389
4390 /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4391 {
4392 { Bad_Opcode },
4393 { "eretu", { Skip_MODRM }, 0 },
4394 },
4395
4396 /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4397 {
4398 { Bad_Opcode },
4399 { "erets", { Skip_MODRM }, 0 },
4400 },
4401
4402 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4403 {
4404 { Bad_Opcode },
4405 { "seamret", { Skip_MODRM }, 0 },
4406 },
4407
4408 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4409 {
4410 { Bad_Opcode },
4411 { "seamops", { Skip_MODRM }, 0 },
4412 },
4413
4414 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4415 {
4416 { Bad_Opcode },
4417 { "seamcall", { Skip_MODRM }, 0 },
4418 },
4419
4420 /* X86_64_0F01_REG_2 */
4421 {
4422 { "lgdt{Q|Q}", { M }, 0 },
4423 { "lgdt", { M }, 0 },
4424 },
4425
4426 /* X86_64_0F01_REG_3 */
4427 {
4428 { "lidt{Q|Q}", { M }, 0 },
4429 { "lidt", { M }, 0 },
4430 },
4431
4432 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4433 {
4434 { Bad_Opcode },
4435 { "uiret", { Skip_MODRM }, 0 },
4436 },
4437
4438 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4439 {
4440 { Bad_Opcode },
4441 { "testui", { Skip_MODRM }, 0 },
4442 },
4443
4444 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4445 {
4446 { Bad_Opcode },
4447 { "clui", { Skip_MODRM }, 0 },
4448 },
4449
4450 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4451 {
4452 { Bad_Opcode },
4453 { "stui", { Skip_MODRM }, 0 },
4454 },
4455
4456 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4457 {
4458 { Bad_Opcode },
4459 { "rmpquery", { Skip_MODRM }, 0 },
4460 },
4461
4462 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4463 {
4464 { Bad_Opcode },
4465 { "rmpadjust", { Skip_MODRM }, 0 },
4466 },
4467
4468 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4469 {
4470 { Bad_Opcode },
4471 { "rmpupdate", { Skip_MODRM }, 0 },
4472 },
4473
4474 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4475 {
4476 { Bad_Opcode },
4477 { "psmash", { Skip_MODRM }, 0 },
4478 },
4479
4480 /* X86_64_0F18_REG_6_MOD_0 */
4481 {
4482 { "nopQ", { Ev }, 0 },
4483 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4484 },
4485
4486 /* X86_64_0F18_REG_7_MOD_0 */
4487 {
4488 { "nopQ", { Ev }, 0 },
4489 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4490 },
4491
4492 {
4493 /* X86_64_0F24 */
4494 { "movZ", { Em, Td }, 0 },
4495 },
4496
4497 {
4498 /* X86_64_0F26 */
4499 { "movZ", { Td, Em }, 0 },
4500 },
4501
4502 {
4503 /* X86_64_0F38F8_M_1 */
4504 { Bad_Opcode },
4505 { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4506 },
4507
4508 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4509 {
4510 { Bad_Opcode },
4511 { "senduipi", { Eq }, 0 },
4512 },
4513
4514 /* X86_64_VEX_0F3849 */
4515 {
4516 { Bad_Opcode },
4517 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4518 },
4519
4520 /* X86_64_VEX_0F384B */
4521 {
4522 { Bad_Opcode },
4523 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4524 },
4525
4526 /* X86_64_VEX_0F385C */
4527 {
4528 { Bad_Opcode },
4529 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4530 },
4531
4532 /* X86_64_VEX_0F385E */
4533 {
4534 { Bad_Opcode },
4535 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4536 },
4537
4538 /* X86_64_VEX_0F386C */
4539 {
4540 { Bad_Opcode },
4541 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4542 },
4543
4544 /* X86_64_VEX_0F38Ex */
4545 {
4546 { Bad_Opcode },
4547 { "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4548 },
4549
4550 /* X86_64_VEX_MAP7_F6_L_0_W_0_R_0 */
4551 {
4552 { Bad_Opcode },
4553 { PREFIX_TABLE (PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64) },
4554 },
4555
4556 /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4557 {
4558 { Bad_Opcode },
4559 { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4560 },
4561 };
4562
4563 static const struct dis386 three_byte_table[][256] = {
4564
4565 /* THREE_BYTE_0F38 */
4566 {
4567 /* 00 */
4568 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4569 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4570 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4571 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4572 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4573 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4574 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4575 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4576 /* 08 */
4577 { "psignb", { MX, EM }, PREFIX_OPCODE },
4578 { "psignw", { MX, EM }, PREFIX_OPCODE },
4579 { "psignd", { MX, EM }, PREFIX_OPCODE },
4580 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4581 { Bad_Opcode },
4582 { Bad_Opcode },
4583 { Bad_Opcode },
4584 { Bad_Opcode },
4585 /* 10 */
4586 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4591 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4592 { Bad_Opcode },
4593 { "ptest", { XM, EXx }, PREFIX_DATA },
4594 /* 18 */
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4600 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4601 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4602 { Bad_Opcode },
4603 /* 20 */
4604 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4605 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4606 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4607 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4608 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4609 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4610 { Bad_Opcode },
4611 { Bad_Opcode },
4612 /* 28 */
4613 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4614 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4615 { "movntdqa", { XM, Mx }, PREFIX_DATA },
4616 { "packusdw", { XM, EXx }, PREFIX_DATA },
4617 { Bad_Opcode },
4618 { Bad_Opcode },
4619 { Bad_Opcode },
4620 { Bad_Opcode },
4621 /* 30 */
4622 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4623 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4624 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4625 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4626 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4627 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4628 { Bad_Opcode },
4629 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4630 /* 38 */
4631 { "pminsb", { XM, EXx }, PREFIX_DATA },
4632 { "pminsd", { XM, EXx }, PREFIX_DATA },
4633 { "pminuw", { XM, EXx }, PREFIX_DATA },
4634 { "pminud", { XM, EXx }, PREFIX_DATA },
4635 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4636 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4637 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4638 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4639 /* 40 */
4640 { "pmulld", { XM, EXx }, PREFIX_DATA },
4641 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 { Bad_Opcode },
4647 { Bad_Opcode },
4648 /* 48 */
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 { Bad_Opcode },
4655 { Bad_Opcode },
4656 { Bad_Opcode },
4657 /* 50 */
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { Bad_Opcode },
4665 { Bad_Opcode },
4666 /* 58 */
4667 { Bad_Opcode },
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 { Bad_Opcode },
4675 /* 60 */
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 { Bad_Opcode },
4683 { Bad_Opcode },
4684 /* 68 */
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 { Bad_Opcode },
4693 /* 70 */
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 { Bad_Opcode },
4702 /* 78 */
4703 { Bad_Opcode },
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 { Bad_Opcode },
4710 { Bad_Opcode },
4711 /* 80 */
4712 { "invept", { Gm, Mo }, PREFIX_DATA },
4713 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4714 { "invpcid", { Gm, M }, PREFIX_DATA },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 { Bad_Opcode },
4720 /* 88 */
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 { Bad_Opcode },
4729 /* 90 */
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 { Bad_Opcode },
4738 /* 98 */
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 { Bad_Opcode },
4747 /* a0 */
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { Bad_Opcode },
4756 /* a8 */
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 { Bad_Opcode },
4765 /* b0 */
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 { Bad_Opcode },
4774 /* b8 */
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 /* c0 */
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 /* c8 */
4793 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4794 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4795 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4796 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4797 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4798 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4799 { Bad_Opcode },
4800 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4801 /* d0 */
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 /* d8 */
4811 { PREFIX_TABLE (PREFIX_0F38D8) },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { "aesimc", { XM, EXx }, PREFIX_DATA },
4815 { PREFIX_TABLE (PREFIX_0F38DC) },
4816 { PREFIX_TABLE (PREFIX_0F38DD) },
4817 { PREFIX_TABLE (PREFIX_0F38DE) },
4818 { PREFIX_TABLE (PREFIX_0F38DF) },
4819 /* e0 */
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 /* e8 */
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 /* f0 */
4838 { PREFIX_TABLE (PREFIX_0F38F0) },
4839 { PREFIX_TABLE (PREFIX_0F38F1) },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { "wrussK", { M, Gdq }, PREFIX_DATA },
4844 { PREFIX_TABLE (PREFIX_0F38F6) },
4845 { Bad_Opcode },
4846 /* f8 */
4847 { MOD_TABLE (MOD_0F38F8) },
4848 { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE },
4849 { PREFIX_TABLE (PREFIX_0F38FA) },
4850 { PREFIX_TABLE (PREFIX_0F38FB) },
4851 { PREFIX_TABLE (PREFIX_0F38FC) },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 },
4856 /* THREE_BYTE_0F3A */
4857 {
4858 /* 00 */
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 /* 08 */
4868 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4869 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4870 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4871 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4872 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4873 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4874 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4875 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4876 /* 10 */
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4882 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4883 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4884 { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4885 /* 18 */
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 /* 20 */
4895 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4896 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4897 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 /* 28 */
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 /* 30 */
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 { Bad_Opcode },
4921 /* 38 */
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 /* 40 */
4931 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4932 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4933 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4934 { Bad_Opcode },
4935 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { Bad_Opcode },
4939 /* 48 */
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 /* 50 */
4949 { Bad_Opcode },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 { Bad_Opcode },
4957 /* 58 */
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 /* 60 */
4967 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4968 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4969 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4970 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 /* 68 */
4976 { Bad_Opcode },
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 /* 70 */
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 /* 78 */
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 { Bad_Opcode },
5002 /* 80 */
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 /* 88 */
5012 { Bad_Opcode },
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { Bad_Opcode },
5020 /* 90 */
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 /* 98 */
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 /* a0 */
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 /* a8 */
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 /* b0 */
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 /* b8 */
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { Bad_Opcode },
5074 /* c0 */
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { Bad_Opcode },
5083 /* c8 */
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5089 { Bad_Opcode },
5090 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5091 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5092 /* d0 */
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 /* d8 */
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5110 /* e0 */
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 /* e8 */
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 /* f0 */
5129 { PREFIX_TABLE (PREFIX_0F3A0F) },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 /* f8 */
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 },
5147 };
5148
5149 static const struct dis386 xop_table[][256] = {
5150 /* XOP_08 */
5151 {
5152 /* 00 */
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 /* 08 */
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 /* 10 */
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 /* 18 */
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 /* 20 */
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 /* 28 */
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 /* 30 */
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 { Bad_Opcode },
5215 /* 38 */
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 { Bad_Opcode },
5224 /* 40 */
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 { Bad_Opcode },
5232 { Bad_Opcode },
5233 /* 48 */
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 { Bad_Opcode },
5242 /* 50 */
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 { Bad_Opcode },
5250 { Bad_Opcode },
5251 /* 58 */
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 { Bad_Opcode },
5260 /* 60 */
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 { Bad_Opcode },
5269 /* 68 */
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 { Bad_Opcode },
5278 /* 70 */
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 { Bad_Opcode },
5287 /* 78 */
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 { Bad_Opcode },
5296 /* 80 */
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5303 { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5304 { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5305 /* 88 */
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5313 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5314 /* 90 */
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5321 { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5322 { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5323 /* 98 */
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5331 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5332 /* a0 */
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5336 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5340 { Bad_Opcode },
5341 /* a8 */
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 { Bad_Opcode },
5350 /* b0 */
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5358 { Bad_Opcode },
5359 /* b8 */
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 /* c0 */
5369 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5370 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5371 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5372 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 /* c8 */
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5383 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5384 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5385 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5386 /* d0 */
5387 { Bad_Opcode },
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 /* d8 */
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 /* e0 */
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 /* e8 */
5414 { Bad_Opcode },
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5419 { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5420 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5421 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5422 /* f0 */
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 /* f8 */
5432 { Bad_Opcode },
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 },
5441 /* XOP_09 */
5442 {
5443 /* 00 */
5444 { Bad_Opcode },
5445 { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5446 { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 { Bad_Opcode },
5452 /* 08 */
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 /* 10 */
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 /* 18 */
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 /* 20 */
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 { Bad_Opcode },
5488 /* 28 */
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 /* 30 */
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 /* 38 */
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 /* 40 */
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 { Bad_Opcode },
5524 /* 48 */
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 { Bad_Opcode },
5533 /* 50 */
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 { Bad_Opcode },
5542 /* 58 */
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 { Bad_Opcode },
5551 /* 60 */
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 { Bad_Opcode },
5560 /* 68 */
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 { Bad_Opcode },
5569 /* 70 */
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 { Bad_Opcode },
5578 /* 78 */
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 { Bad_Opcode },
5587 /* 80 */
5588 { VEX_W_TABLE (VEX_W_XOP_09_80) },
5589 { VEX_W_TABLE (VEX_W_XOP_09_81) },
5590 { VEX_W_TABLE (VEX_W_XOP_09_82) },
5591 { VEX_W_TABLE (VEX_W_XOP_09_83) },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 { Bad_Opcode },
5596 /* 88 */
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 /* 90 */
5606 { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5607 { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5608 { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5609 { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5610 { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5611 { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5612 { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5613 { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5614 /* 98 */
5615 { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5616 { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5617 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5618 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 { Bad_Opcode },
5623 /* a0 */
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 /* a8 */
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 /* b0 */
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 /* b8 */
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 /* c0 */
5660 { Bad_Opcode },
5661 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5662 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5663 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5667 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5668 /* c8 */
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 /* d0 */
5678 { Bad_Opcode },
5679 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5680 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5681 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5685 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5686 /* d8 */
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 /* e0 */
5696 { Bad_Opcode },
5697 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5698 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5699 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 /* e8 */
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 /* f0 */
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 /* f8 */
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 },
5732 /* XOP_0A */
5733 {
5734 /* 00 */
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { Bad_Opcode },
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 /* 08 */
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 { Bad_Opcode },
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 /* 10 */
5753 { "bextrS", { Gdq, Edq, Id }, 0 },
5754 { Bad_Opcode },
5755 { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 /* 18 */
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { Bad_Opcode },
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 /* 20 */
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 { Bad_Opcode },
5776 { Bad_Opcode },
5777 { Bad_Opcode },
5778 { Bad_Opcode },
5779 /* 28 */
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 /* 30 */
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 /* 38 */
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 /* 40 */
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 /* 48 */
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 /* 50 */
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 /* 58 */
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 /* 60 */
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { Bad_Opcode },
5851 /* 68 */
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 /* 70 */
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 /* 78 */
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 { Bad_Opcode },
5878 /* 80 */
5879 { Bad_Opcode },
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 /* 88 */
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 { Bad_Opcode },
5896 /* 90 */
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 { Bad_Opcode },
5905 /* 98 */
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 { Bad_Opcode },
5914 /* a0 */
5915 { Bad_Opcode },
5916 { Bad_Opcode },
5917 { Bad_Opcode },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 { Bad_Opcode },
5923 /* a8 */
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 { Bad_Opcode },
5932 /* b0 */
5933 { Bad_Opcode },
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { Bad_Opcode },
5940 { Bad_Opcode },
5941 /* b8 */
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 { Bad_Opcode },
5950 /* c0 */
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 { Bad_Opcode },
5959 /* c8 */
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 { Bad_Opcode },
5968 /* d0 */
5969 { Bad_Opcode },
5970 { Bad_Opcode },
5971 { Bad_Opcode },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 { Bad_Opcode },
5977 /* d8 */
5978 { Bad_Opcode },
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 { Bad_Opcode },
5986 /* e0 */
5987 { Bad_Opcode },
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 { Bad_Opcode },
5995 /* e8 */
5996 { Bad_Opcode },
5997 { Bad_Opcode },
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 { Bad_Opcode },
6004 /* f0 */
6005 { Bad_Opcode },
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 { Bad_Opcode },
6013 /* f8 */
6014 { Bad_Opcode },
6015 { Bad_Opcode },
6016 { Bad_Opcode },
6017 { Bad_Opcode },
6018 { Bad_Opcode },
6019 { Bad_Opcode },
6020 { Bad_Opcode },
6021 { Bad_Opcode },
6022 },
6023 };
6024
6025 static const struct dis386 vex_table[][256] = {
6026 /* VEX_0F */
6027 {
6028 /* 00 */
6029 { Bad_Opcode },
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 /* 08 */
6038 { Bad_Opcode },
6039 { Bad_Opcode },
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 /* 10 */
6047 { PREFIX_TABLE (PREFIX_0F10) },
6048 { PREFIX_TABLE (PREFIX_0F11) },
6049 { PREFIX_TABLE (PREFIX_VEX_0F12) },
6050 { VEX_LEN_TABLE (VEX_LEN_0F13) },
6051 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6052 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6053 { PREFIX_TABLE (PREFIX_VEX_0F16) },
6054 { VEX_LEN_TABLE (VEX_LEN_0F17) },
6055 /* 18 */
6056 { Bad_Opcode },
6057 { Bad_Opcode },
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 /* 20 */
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 { Bad_Opcode },
6073 /* 28 */
6074 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
6075 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
6076 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6077 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
6078 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6079 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6080 { PREFIX_TABLE (PREFIX_0F2E) },
6081 { PREFIX_TABLE (PREFIX_0F2F) },
6082 /* 30 */
6083 { Bad_Opcode },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { Bad_Opcode },
6091 /* 38 */
6092 { Bad_Opcode },
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 /* 40 */
6101 { Bad_Opcode },
6102 { VEX_LEN_TABLE (VEX_LEN_0F41) },
6103 { VEX_LEN_TABLE (VEX_LEN_0F42) },
6104 { Bad_Opcode },
6105 { VEX_LEN_TABLE (VEX_LEN_0F44) },
6106 { VEX_LEN_TABLE (VEX_LEN_0F45) },
6107 { VEX_LEN_TABLE (VEX_LEN_0F46) },
6108 { VEX_LEN_TABLE (VEX_LEN_0F47) },
6109 /* 48 */
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6113 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6114 { Bad_Opcode },
6115 { Bad_Opcode },
6116 { Bad_Opcode },
6117 { Bad_Opcode },
6118 /* 50 */
6119 { "vmovmskpX", { Gdq, Ux }, PREFIX_OPCODE },
6120 { PREFIX_TABLE (PREFIX_0F51) },
6121 { PREFIX_TABLE (PREFIX_0F52) },
6122 { PREFIX_TABLE (PREFIX_0F53) },
6123 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6124 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6125 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6126 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6127 /* 58 */
6128 { PREFIX_TABLE (PREFIX_0F58) },
6129 { PREFIX_TABLE (PREFIX_0F59) },
6130 { PREFIX_TABLE (PREFIX_0F5A) },
6131 { PREFIX_TABLE (PREFIX_0F5B) },
6132 { PREFIX_TABLE (PREFIX_0F5C) },
6133 { PREFIX_TABLE (PREFIX_0F5D) },
6134 { PREFIX_TABLE (PREFIX_0F5E) },
6135 { PREFIX_TABLE (PREFIX_0F5F) },
6136 /* 60 */
6137 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6138 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6139 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6140 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6141 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6142 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6143 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6144 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6145 /* 68 */
6146 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6147 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6148 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6149 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6150 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6151 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6152 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6153 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6154 /* 70 */
6155 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6156 { REG_TABLE (REG_VEX_0F71) },
6157 { REG_TABLE (REG_VEX_0F72) },
6158 { REG_TABLE (REG_VEX_0F73) },
6159 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6160 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6161 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6162 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6163 /* 78 */
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { PREFIX_TABLE (PREFIX_0F7C) },
6169 { PREFIX_TABLE (PREFIX_0F7D) },
6170 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6171 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6172 /* 80 */
6173 { Bad_Opcode },
6174 { Bad_Opcode },
6175 { Bad_Opcode },
6176 { Bad_Opcode },
6177 { Bad_Opcode },
6178 { Bad_Opcode },
6179 { Bad_Opcode },
6180 { Bad_Opcode },
6181 /* 88 */
6182 { Bad_Opcode },
6183 { Bad_Opcode },
6184 { Bad_Opcode },
6185 { Bad_Opcode },
6186 { Bad_Opcode },
6187 { Bad_Opcode },
6188 { Bad_Opcode },
6189 { Bad_Opcode },
6190 /* 90 */
6191 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6192 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6193 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6194 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6195 { Bad_Opcode },
6196 { Bad_Opcode },
6197 { Bad_Opcode },
6198 { Bad_Opcode },
6199 /* 98 */
6200 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6201 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6202 { Bad_Opcode },
6203 { Bad_Opcode },
6204 { Bad_Opcode },
6205 { Bad_Opcode },
6206 { Bad_Opcode },
6207 { Bad_Opcode },
6208 /* a0 */
6209 { Bad_Opcode },
6210 { Bad_Opcode },
6211 { Bad_Opcode },
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 { Bad_Opcode },
6215 { Bad_Opcode },
6216 { Bad_Opcode },
6217 /* a8 */
6218 { Bad_Opcode },
6219 { Bad_Opcode },
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { Bad_Opcode },
6223 { Bad_Opcode },
6224 { REG_TABLE (REG_VEX_0FAE) },
6225 { Bad_Opcode },
6226 /* b0 */
6227 { Bad_Opcode },
6228 { Bad_Opcode },
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 { Bad_Opcode },
6233 { Bad_Opcode },
6234 { Bad_Opcode },
6235 /* b8 */
6236 { Bad_Opcode },
6237 { Bad_Opcode },
6238 { Bad_Opcode },
6239 { Bad_Opcode },
6240 { Bad_Opcode },
6241 { Bad_Opcode },
6242 { Bad_Opcode },
6243 { Bad_Opcode },
6244 /* c0 */
6245 { Bad_Opcode },
6246 { Bad_Opcode },
6247 { PREFIX_TABLE (PREFIX_0FC2) },
6248 { Bad_Opcode },
6249 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6250 { "vpextrw", { Gd, Uxmm, Ib }, PREFIX_DATA },
6251 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6252 { Bad_Opcode },
6253 /* c8 */
6254 { Bad_Opcode },
6255 { Bad_Opcode },
6256 { Bad_Opcode },
6257 { Bad_Opcode },
6258 { Bad_Opcode },
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 { Bad_Opcode },
6262 /* d0 */
6263 { PREFIX_TABLE (PREFIX_0FD0) },
6264 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6265 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6266 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6267 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6268 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6269 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6270 { "vpmovmskb", { Gdq, Ux }, PREFIX_DATA },
6271 /* d8 */
6272 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6273 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6274 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6275 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6276 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6277 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6278 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6279 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6280 /* e0 */
6281 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6282 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6283 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6284 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6285 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6286 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6287 { PREFIX_TABLE (PREFIX_0FE6) },
6288 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
6289 /* e8 */
6290 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6291 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6292 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6293 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6294 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6295 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6296 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6297 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6298 /* f0 */
6299 { PREFIX_TABLE (PREFIX_0FF0) },
6300 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6301 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6302 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6303 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6304 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6305 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6306 { "vmaskmovdqu", { XM, Uxmm }, PREFIX_DATA },
6307 /* f8 */
6308 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6309 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6310 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6311 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6312 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6313 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6314 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6315 { Bad_Opcode },
6316 },
6317 /* VEX_0F38 */
6318 {
6319 /* 00 */
6320 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6321 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6322 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6323 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6324 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6325 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6326 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6327 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6328 /* 08 */
6329 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6330 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6331 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6332 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6333 { VEX_W_TABLE (VEX_W_0F380C) },
6334 { VEX_W_TABLE (VEX_W_0F380D) },
6335 { VEX_W_TABLE (VEX_W_0F380E) },
6336 { VEX_W_TABLE (VEX_W_0F380F) },
6337 /* 10 */
6338 { Bad_Opcode },
6339 { Bad_Opcode },
6340 { Bad_Opcode },
6341 { VEX_W_TABLE (VEX_W_0F3813) },
6342 { Bad_Opcode },
6343 { Bad_Opcode },
6344 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6345 { "vptest", { XM, EXx }, PREFIX_DATA },
6346 /* 18 */
6347 { VEX_W_TABLE (VEX_W_0F3818) },
6348 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6349 { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6350 { Bad_Opcode },
6351 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6352 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6353 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6354 { Bad_Opcode },
6355 /* 20 */
6356 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6357 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6358 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6359 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6360 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6361 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6362 { Bad_Opcode },
6363 { Bad_Opcode },
6364 /* 28 */
6365 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6366 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6367 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
6368 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6369 { VEX_W_TABLE (VEX_W_0F382C) },
6370 { VEX_W_TABLE (VEX_W_0F382D) },
6371 { VEX_W_TABLE (VEX_W_0F382E) },
6372 { VEX_W_TABLE (VEX_W_0F382F) },
6373 /* 30 */
6374 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6375 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6376 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6377 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6378 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6379 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6380 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6381 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6382 /* 38 */
6383 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6384 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6385 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6386 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6387 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6388 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6389 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6390 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6391 /* 40 */
6392 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6393 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6394 { Bad_Opcode },
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6398 { VEX_W_TABLE (VEX_W_0F3846) },
6399 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6400 /* 48 */
6401 { Bad_Opcode },
6402 { X86_64_TABLE (X86_64_VEX_0F3849) },
6403 { Bad_Opcode },
6404 { X86_64_TABLE (X86_64_VEX_0F384B) },
6405 { Bad_Opcode },
6406 { Bad_Opcode },
6407 { Bad_Opcode },
6408 { Bad_Opcode },
6409 /* 50 */
6410 { VEX_W_TABLE (VEX_W_0F3850) },
6411 { VEX_W_TABLE (VEX_W_0F3851) },
6412 { VEX_W_TABLE (VEX_W_0F3852) },
6413 { VEX_W_TABLE (VEX_W_0F3853) },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 { Bad_Opcode },
6417 { Bad_Opcode },
6418 /* 58 */
6419 { VEX_W_TABLE (VEX_W_0F3858) },
6420 { VEX_W_TABLE (VEX_W_0F3859) },
6421 { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6422 { Bad_Opcode },
6423 { X86_64_TABLE (X86_64_VEX_0F385C) },
6424 { Bad_Opcode },
6425 { X86_64_TABLE (X86_64_VEX_0F385E) },
6426 { Bad_Opcode },
6427 /* 60 */
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 { Bad_Opcode },
6435 { Bad_Opcode },
6436 /* 68 */
6437 { Bad_Opcode },
6438 { Bad_Opcode },
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { X86_64_TABLE (X86_64_VEX_0F386C) },
6442 { Bad_Opcode },
6443 { Bad_Opcode },
6444 { Bad_Opcode },
6445 /* 70 */
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 { Bad_Opcode },
6454 /* 78 */
6455 { VEX_W_TABLE (VEX_W_0F3878) },
6456 { VEX_W_TABLE (VEX_W_0F3879) },
6457 { Bad_Opcode },
6458 { Bad_Opcode },
6459 { Bad_Opcode },
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 { Bad_Opcode },
6463 /* 80 */
6464 { Bad_Opcode },
6465 { Bad_Opcode },
6466 { Bad_Opcode },
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 { Bad_Opcode },
6472 /* 88 */
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
6478 { Bad_Opcode },
6479 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
6480 { Bad_Opcode },
6481 /* 90 */
6482 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6483 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6484 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6485 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6489 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6490 /* 98 */
6491 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6492 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6493 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6494 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6495 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6496 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6497 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6498 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6499 /* a0 */
6500 { Bad_Opcode },
6501 { Bad_Opcode },
6502 { Bad_Opcode },
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6507 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6508 /* a8 */
6509 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6510 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6511 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6512 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6513 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6514 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6515 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6516 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6517 /* b0 */
6518 { VEX_W_TABLE (VEX_W_0F38B0) },
6519 { VEX_W_TABLE (VEX_W_0F38B1) },
6520 { Bad_Opcode },
6521 { Bad_Opcode },
6522 { VEX_W_TABLE (VEX_W_0F38B4) },
6523 { VEX_W_TABLE (VEX_W_0F38B5) },
6524 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6525 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6526 /* b8 */
6527 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6528 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6529 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6530 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6531 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6532 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6533 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6534 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6535 /* c0 */
6536 { Bad_Opcode },
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 { Bad_Opcode },
6540 { Bad_Opcode },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 { Bad_Opcode },
6544 /* c8 */
6545 { Bad_Opcode },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6549 { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6550 { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6551 { Bad_Opcode },
6552 { VEX_W_TABLE (VEX_W_0F38CF) },
6553 /* d0 */
6554 { Bad_Opcode },
6555 { Bad_Opcode },
6556 { VEX_W_TABLE (VEX_W_0F38D2) },
6557 { VEX_W_TABLE (VEX_W_0F38D3) },
6558 { Bad_Opcode },
6559 { Bad_Opcode },
6560 { Bad_Opcode },
6561 { Bad_Opcode },
6562 /* d8 */
6563 { Bad_Opcode },
6564 { Bad_Opcode },
6565 { VEX_W_TABLE (VEX_W_0F38DA) },
6566 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6567 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6568 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6569 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6570 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6571 /* e0 */
6572 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6573 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6574 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6575 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6576 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6577 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6578 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6579 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6580 /* e8 */
6581 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6582 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6583 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6584 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6585 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6586 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6587 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6588 { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6589 /* f0 */
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6593 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6594 { Bad_Opcode },
6595 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6596 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6597 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6598 /* f8 */
6599 { Bad_Opcode },
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 { Bad_Opcode },
6606 { Bad_Opcode },
6607 },
6608 /* VEX_0F3A */
6609 {
6610 /* 00 */
6611 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6612 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6613 { VEX_W_TABLE (VEX_W_0F3A02) },
6614 { Bad_Opcode },
6615 { VEX_W_TABLE (VEX_W_0F3A04) },
6616 { VEX_W_TABLE (VEX_W_0F3A05) },
6617 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6618 { Bad_Opcode },
6619 /* 08 */
6620 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6621 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6622 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6623 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6624 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6625 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6626 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6627 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6628 /* 10 */
6629 { Bad_Opcode },
6630 { Bad_Opcode },
6631 { Bad_Opcode },
6632 { Bad_Opcode },
6633 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6634 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6635 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6636 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6637 /* 18 */
6638 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6639 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6640 { Bad_Opcode },
6641 { Bad_Opcode },
6642 { Bad_Opcode },
6643 { VEX_W_TABLE (VEX_W_0F3A1D) },
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 /* 20 */
6647 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6649 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6650 { Bad_Opcode },
6651 { Bad_Opcode },
6652 { Bad_Opcode },
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 /* 28 */
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 { Bad_Opcode },
6660 { Bad_Opcode },
6661 { Bad_Opcode },
6662 { Bad_Opcode },
6663 { Bad_Opcode },
6664 /* 30 */
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6666 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6667 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6668 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6669 { Bad_Opcode },
6670 { Bad_Opcode },
6671 { Bad_Opcode },
6672 { Bad_Opcode },
6673 /* 38 */
6674 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6675 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6676 { Bad_Opcode },
6677 { Bad_Opcode },
6678 { Bad_Opcode },
6679 { Bad_Opcode },
6680 { Bad_Opcode },
6681 { Bad_Opcode },
6682 /* 40 */
6683 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6684 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6685 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6686 { Bad_Opcode },
6687 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6688 { Bad_Opcode },
6689 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6690 { Bad_Opcode },
6691 /* 48 */
6692 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6693 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6694 { VEX_W_TABLE (VEX_W_0F3A4A) },
6695 { VEX_W_TABLE (VEX_W_0F3A4B) },
6696 { VEX_W_TABLE (VEX_W_0F3A4C) },
6697 { Bad_Opcode },
6698 { Bad_Opcode },
6699 { Bad_Opcode },
6700 /* 50 */
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 { Bad_Opcode },
6708 { Bad_Opcode },
6709 /* 58 */
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6715 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6716 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6717 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6718 /* 60 */
6719 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6720 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6721 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6722 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6723 { Bad_Opcode },
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 { Bad_Opcode },
6727 /* 68 */
6728 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6729 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6730 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6731 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6732 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6733 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6734 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6735 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6736 /* 70 */
6737 { Bad_Opcode },
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 { Bad_Opcode },
6745 /* 78 */
6746 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6747 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6748 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6749 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6750 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6751 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6752 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6753 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6754 /* 80 */
6755 { Bad_Opcode },
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 { Bad_Opcode },
6763 /* 88 */
6764 { Bad_Opcode },
6765 { Bad_Opcode },
6766 { Bad_Opcode },
6767 { Bad_Opcode },
6768 { Bad_Opcode },
6769 { Bad_Opcode },
6770 { Bad_Opcode },
6771 { Bad_Opcode },
6772 /* 90 */
6773 { Bad_Opcode },
6774 { Bad_Opcode },
6775 { Bad_Opcode },
6776 { Bad_Opcode },
6777 { Bad_Opcode },
6778 { Bad_Opcode },
6779 { Bad_Opcode },
6780 { Bad_Opcode },
6781 /* 98 */
6782 { Bad_Opcode },
6783 { Bad_Opcode },
6784 { Bad_Opcode },
6785 { Bad_Opcode },
6786 { Bad_Opcode },
6787 { Bad_Opcode },
6788 { Bad_Opcode },
6789 { Bad_Opcode },
6790 /* a0 */
6791 { Bad_Opcode },
6792 { Bad_Opcode },
6793 { Bad_Opcode },
6794 { Bad_Opcode },
6795 { Bad_Opcode },
6796 { Bad_Opcode },
6797 { Bad_Opcode },
6798 { Bad_Opcode },
6799 /* a8 */
6800 { Bad_Opcode },
6801 { Bad_Opcode },
6802 { Bad_Opcode },
6803 { Bad_Opcode },
6804 { Bad_Opcode },
6805 { Bad_Opcode },
6806 { Bad_Opcode },
6807 { Bad_Opcode },
6808 /* b0 */
6809 { Bad_Opcode },
6810 { Bad_Opcode },
6811 { Bad_Opcode },
6812 { Bad_Opcode },
6813 { Bad_Opcode },
6814 { Bad_Opcode },
6815 { Bad_Opcode },
6816 { Bad_Opcode },
6817 /* b8 */
6818 { Bad_Opcode },
6819 { Bad_Opcode },
6820 { Bad_Opcode },
6821 { Bad_Opcode },
6822 { Bad_Opcode },
6823 { Bad_Opcode },
6824 { Bad_Opcode },
6825 { Bad_Opcode },
6826 /* c0 */
6827 { Bad_Opcode },
6828 { Bad_Opcode },
6829 { Bad_Opcode },
6830 { Bad_Opcode },
6831 { Bad_Opcode },
6832 { Bad_Opcode },
6833 { Bad_Opcode },
6834 { Bad_Opcode },
6835 /* c8 */
6836 { Bad_Opcode },
6837 { Bad_Opcode },
6838 { Bad_Opcode },
6839 { Bad_Opcode },
6840 { Bad_Opcode },
6841 { Bad_Opcode },
6842 { VEX_W_TABLE (VEX_W_0F3ACE) },
6843 { VEX_W_TABLE (VEX_W_0F3ACF) },
6844 /* d0 */
6845 { Bad_Opcode },
6846 { Bad_Opcode },
6847 { Bad_Opcode },
6848 { Bad_Opcode },
6849 { Bad_Opcode },
6850 { Bad_Opcode },
6851 { Bad_Opcode },
6852 { Bad_Opcode },
6853 /* d8 */
6854 { Bad_Opcode },
6855 { Bad_Opcode },
6856 { Bad_Opcode },
6857 { Bad_Opcode },
6858 { Bad_Opcode },
6859 { Bad_Opcode },
6860 { VEX_W_TABLE (VEX_W_0F3ADE) },
6861 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6862 /* e0 */
6863 { Bad_Opcode },
6864 { Bad_Opcode },
6865 { Bad_Opcode },
6866 { Bad_Opcode },
6867 { Bad_Opcode },
6868 { Bad_Opcode },
6869 { Bad_Opcode },
6870 { Bad_Opcode },
6871 /* e8 */
6872 { Bad_Opcode },
6873 { Bad_Opcode },
6874 { Bad_Opcode },
6875 { Bad_Opcode },
6876 { Bad_Opcode },
6877 { Bad_Opcode },
6878 { Bad_Opcode },
6879 { Bad_Opcode },
6880 /* f0 */
6881 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6882 { Bad_Opcode },
6883 { Bad_Opcode },
6884 { Bad_Opcode },
6885 { Bad_Opcode },
6886 { Bad_Opcode },
6887 { Bad_Opcode },
6888 { Bad_Opcode },
6889 /* f8 */
6890 { Bad_Opcode },
6891 { Bad_Opcode },
6892 { Bad_Opcode },
6893 { Bad_Opcode },
6894 { Bad_Opcode },
6895 { Bad_Opcode },
6896 { Bad_Opcode },
6897 { Bad_Opcode },
6898 },
6899 };
6900
6901 #include "i386-dis-evex.h"
6902
6903 static const struct dis386 vex_len_table[][2] = {
6904 /* VEX_LEN_0F12_P_0 */
6905 {
6906 { MOD_TABLE (MOD_0F12_PREFIX_0) },
6907 },
6908
6909 /* VEX_LEN_0F12_P_2 */
6910 {
6911 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
6912 },
6913
6914 /* VEX_LEN_0F13 */
6915 {
6916 { "%XEVmovlpYX", { Mq, XM }, PREFIX_OPCODE },
6917 },
6918
6919 /* VEX_LEN_0F16_P_0 */
6920 {
6921 { MOD_TABLE (MOD_0F16_PREFIX_0) },
6922 },
6923
6924 /* VEX_LEN_0F16_P_2 */
6925 {
6926 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
6927 },
6928
6929 /* VEX_LEN_0F17 */
6930 {
6931 { "%XEVmovhpYX", { Mq, XM }, PREFIX_OPCODE },
6932 },
6933
6934 /* VEX_LEN_0F41 */
6935 {
6936 { Bad_Opcode },
6937 { VEX_W_TABLE (VEX_W_0F41_L_1) },
6938 },
6939
6940 /* VEX_LEN_0F42 */
6941 {
6942 { Bad_Opcode },
6943 { VEX_W_TABLE (VEX_W_0F42_L_1) },
6944 },
6945
6946 /* VEX_LEN_0F44 */
6947 {
6948 { VEX_W_TABLE (VEX_W_0F44_L_0) },
6949 },
6950
6951 /* VEX_LEN_0F45 */
6952 {
6953 { Bad_Opcode },
6954 { VEX_W_TABLE (VEX_W_0F45_L_1) },
6955 },
6956
6957 /* VEX_LEN_0F46 */
6958 {
6959 { Bad_Opcode },
6960 { VEX_W_TABLE (VEX_W_0F46_L_1) },
6961 },
6962
6963 /* VEX_LEN_0F47 */
6964 {
6965 { Bad_Opcode },
6966 { VEX_W_TABLE (VEX_W_0F47_L_1) },
6967 },
6968
6969 /* VEX_LEN_0F4A */
6970 {
6971 { Bad_Opcode },
6972 { VEX_W_TABLE (VEX_W_0F4A_L_1) },
6973 },
6974
6975 /* VEX_LEN_0F4B */
6976 {
6977 { Bad_Opcode },
6978 { VEX_W_TABLE (VEX_W_0F4B_L_1) },
6979 },
6980
6981 /* VEX_LEN_0F6E */
6982 {
6983 { "%XEvmovYK", { XMScalar, Edq }, PREFIX_DATA },
6984 },
6985
6986 /* VEX_LEN_0F77 */
6987 {
6988 { "vzeroupper", { XX }, 0 },
6989 { "vzeroall", { XX }, 0 },
6990 },
6991
6992 /* VEX_LEN_0F7E_P_1 */
6993 {
6994 { "%XEvmovqY", { XMScalar, EXq }, 0 },
6995 },
6996
6997 /* VEX_LEN_0F7E_P_2 */
6998 {
6999 { "%XEvmovK", { Edq, XMScalar }, 0 },
7000 },
7001
7002 /* VEX_LEN_0F90 */
7003 {
7004 { VEX_W_TABLE (VEX_W_0F90_L_0) },
7005 },
7006
7007 /* VEX_LEN_0F91 */
7008 {
7009 { VEX_W_TABLE (VEX_W_0F91_L_0) },
7010 },
7011
7012 /* VEX_LEN_0F92 */
7013 {
7014 { VEX_W_TABLE (VEX_W_0F92_L_0) },
7015 },
7016
7017 /* VEX_LEN_0F93 */
7018 {
7019 { VEX_W_TABLE (VEX_W_0F93_L_0) },
7020 },
7021
7022 /* VEX_LEN_0F98 */
7023 {
7024 { VEX_W_TABLE (VEX_W_0F98_L_0) },
7025 },
7026
7027 /* VEX_LEN_0F99 */
7028 {
7029 { VEX_W_TABLE (VEX_W_0F99_L_0) },
7030 },
7031
7032 /* VEX_LEN_0FAE_R_2 */
7033 {
7034 { "vldmxcsr", { Md }, 0 },
7035 },
7036
7037 /* VEX_LEN_0FAE_R_3 */
7038 {
7039 { "vstmxcsr", { Md }, 0 },
7040 },
7041
7042 /* VEX_LEN_0FC4 */
7043 {
7044 { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA },
7045 },
7046
7047 /* VEX_LEN_0FD6 */
7048 {
7049 { "%XEvmovqY", { EXqS, XMScalar }, PREFIX_DATA },
7050 },
7051
7052 /* VEX_LEN_0F3816 */
7053 {
7054 { Bad_Opcode },
7055 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7056 },
7057
7058 /* VEX_LEN_0F3819 */
7059 {
7060 { Bad_Opcode },
7061 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7062 },
7063
7064 /* VEX_LEN_0F381A */
7065 {
7066 { Bad_Opcode },
7067 { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7068 },
7069
7070 /* VEX_LEN_0F3836 */
7071 {
7072 { Bad_Opcode },
7073 { VEX_W_TABLE (VEX_W_0F3836) },
7074 },
7075
7076 /* VEX_LEN_0F3841 */
7077 {
7078 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
7079 },
7080
7081 /* VEX_LEN_0F3849_X86_64 */
7082 {
7083 { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7084 },
7085
7086 /* VEX_LEN_0F384B_X86_64 */
7087 {
7088 { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7089 },
7090
7091 /* VEX_LEN_0F385A */
7092 {
7093 { Bad_Opcode },
7094 { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7095 },
7096
7097 /* VEX_LEN_0F385C_X86_64 */
7098 {
7099 { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7100 },
7101
7102 /* VEX_LEN_0F385E_X86_64 */
7103 {
7104 { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7105 },
7106
7107 /* VEX_LEN_0F386C_X86_64 */
7108 {
7109 { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7110 },
7111
7112 /* VEX_LEN_0F38CB_P_3_W_0 */
7113 {
7114 { Bad_Opcode },
7115 { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7116 },
7117
7118 /* VEX_LEN_0F38CC_P_3_W_0 */
7119 {
7120 { Bad_Opcode },
7121 { "vsha512msg1", { XM, Rxmmq }, 0 },
7122 },
7123
7124 /* VEX_LEN_0F38CD_P_3_W_0 */
7125 {
7126 { Bad_Opcode },
7127 { "vsha512msg2", { XM, Rymm }, 0 },
7128 },
7129
7130 /* VEX_LEN_0F38DA_W_0_P_0 */
7131 {
7132 { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7133 },
7134
7135 /* VEX_LEN_0F38DA_W_0_P_2 */
7136 {
7137 { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7138 },
7139
7140 /* VEX_LEN_0F38DB */
7141 {
7142 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7143 },
7144
7145 /* VEX_LEN_0F38F2 */
7146 {
7147 { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7148 },
7149
7150 /* VEX_LEN_0F38F3 */
7151 {
7152 { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7153 },
7154
7155 /* VEX_LEN_0F38F5 */
7156 {
7157 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7158 },
7159
7160 /* VEX_LEN_0F38F6 */
7161 {
7162 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7163 },
7164
7165 /* VEX_LEN_0F38F7 */
7166 {
7167 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7168 },
7169
7170 /* VEX_LEN_0F3A00 */
7171 {
7172 { Bad_Opcode },
7173 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7174 },
7175
7176 /* VEX_LEN_0F3A01 */
7177 {
7178 { Bad_Opcode },
7179 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7180 },
7181
7182 /* VEX_LEN_0F3A06 */
7183 {
7184 { Bad_Opcode },
7185 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7186 },
7187
7188 /* VEX_LEN_0F3A14 */
7189 {
7190 { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
7191 },
7192
7193 /* VEX_LEN_0F3A15 */
7194 {
7195 { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
7196 },
7197
7198 /* VEX_LEN_0F3A16 */
7199 {
7200 { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7201 },
7202
7203 /* VEX_LEN_0F3A17 */
7204 {
7205 { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA },
7206 },
7207
7208 /* VEX_LEN_0F3A18 */
7209 {
7210 { Bad_Opcode },
7211 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7212 },
7213
7214 /* VEX_LEN_0F3A19 */
7215 {
7216 { Bad_Opcode },
7217 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7218 },
7219
7220 /* VEX_LEN_0F3A20 */
7221 {
7222 { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7223 },
7224
7225 /* VEX_LEN_0F3A21 */
7226 {
7227 { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7228 },
7229
7230 /* VEX_LEN_0F3A22 */
7231 {
7232 { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7233 },
7234
7235 /* VEX_LEN_0F3A30 */
7236 {
7237 { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7238 },
7239
7240 /* VEX_LEN_0F3A31 */
7241 {
7242 { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7243 },
7244
7245 /* VEX_LEN_0F3A32 */
7246 {
7247 { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7248 },
7249
7250 /* VEX_LEN_0F3A33 */
7251 {
7252 { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7253 },
7254
7255 /* VEX_LEN_0F3A38 */
7256 {
7257 { Bad_Opcode },
7258 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7259 },
7260
7261 /* VEX_LEN_0F3A39 */
7262 {
7263 { Bad_Opcode },
7264 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7265 },
7266
7267 /* VEX_LEN_0F3A41 */
7268 {
7269 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7270 },
7271
7272 /* VEX_LEN_0F3A46 */
7273 {
7274 { Bad_Opcode },
7275 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7276 },
7277
7278 /* VEX_LEN_0F3A60 */
7279 {
7280 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7281 },
7282
7283 /* VEX_LEN_0F3A61 */
7284 {
7285 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7286 },
7287
7288 /* VEX_LEN_0F3A62 */
7289 {
7290 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7291 },
7292
7293 /* VEX_LEN_0F3A63 */
7294 {
7295 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7296 },
7297
7298 /* VEX_LEN_0F3ADE_W_0 */
7299 {
7300 { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7301 },
7302
7303 /* VEX_LEN_0F3ADF */
7304 {
7305 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7306 },
7307
7308 /* VEX_LEN_0F3AF0 */
7309 {
7310 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7311 },
7312
7313 /* VEX_LEN_MAP7_F6 */
7314 {
7315 { VEX_W_TABLE (VEX_W_MAP7_F6_L_0) },
7316 },
7317
7318 /* VEX_LEN_MAP7_F8 */
7319 {
7320 { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7321 },
7322
7323 /* VEX_LEN_XOP_08_85 */
7324 {
7325 { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7326 },
7327
7328 /* VEX_LEN_XOP_08_86 */
7329 {
7330 { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7331 },
7332
7333 /* VEX_LEN_XOP_08_87 */
7334 {
7335 { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7336 },
7337
7338 /* VEX_LEN_XOP_08_8E */
7339 {
7340 { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7341 },
7342
7343 /* VEX_LEN_XOP_08_8F */
7344 {
7345 { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7346 },
7347
7348 /* VEX_LEN_XOP_08_95 */
7349 {
7350 { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7351 },
7352
7353 /* VEX_LEN_XOP_08_96 */
7354 {
7355 { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7356 },
7357
7358 /* VEX_LEN_XOP_08_97 */
7359 {
7360 { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7361 },
7362
7363 /* VEX_LEN_XOP_08_9E */
7364 {
7365 { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7366 },
7367
7368 /* VEX_LEN_XOP_08_9F */
7369 {
7370 { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7371 },
7372
7373 /* VEX_LEN_XOP_08_A3 */
7374 {
7375 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7376 },
7377
7378 /* VEX_LEN_XOP_08_A6 */
7379 {
7380 { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7381 },
7382
7383 /* VEX_LEN_XOP_08_B6 */
7384 {
7385 { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7386 },
7387
7388 /* VEX_LEN_XOP_08_C0 */
7389 {
7390 { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7391 },
7392
7393 /* VEX_LEN_XOP_08_C1 */
7394 {
7395 { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7396 },
7397
7398 /* VEX_LEN_XOP_08_C2 */
7399 {
7400 { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7401 },
7402
7403 /* VEX_LEN_XOP_08_C3 */
7404 {
7405 { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7406 },
7407
7408 /* VEX_LEN_XOP_08_CC */
7409 {
7410 { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7411 },
7412
7413 /* VEX_LEN_XOP_08_CD */
7414 {
7415 { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7416 },
7417
7418 /* VEX_LEN_XOP_08_CE */
7419 {
7420 { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7421 },
7422
7423 /* VEX_LEN_XOP_08_CF */
7424 {
7425 { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7426 },
7427
7428 /* VEX_LEN_XOP_08_EC */
7429 {
7430 { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7431 },
7432
7433 /* VEX_LEN_XOP_08_ED */
7434 {
7435 { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7436 },
7437
7438 /* VEX_LEN_XOP_08_EE */
7439 {
7440 { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7441 },
7442
7443 /* VEX_LEN_XOP_08_EF */
7444 {
7445 { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7446 },
7447
7448 /* VEX_LEN_XOP_09_01 */
7449 {
7450 { REG_TABLE (REG_XOP_09_01_L_0) },
7451 },
7452
7453 /* VEX_LEN_XOP_09_02 */
7454 {
7455 { REG_TABLE (REG_XOP_09_02_L_0) },
7456 },
7457
7458 /* VEX_LEN_XOP_09_12 */
7459 {
7460 { REG_TABLE (REG_XOP_09_12_L_0) },
7461 },
7462
7463 /* VEX_LEN_XOP_09_82_W_0 */
7464 {
7465 { "vfrczss", { XM, EXd }, 0 },
7466 },
7467
7468 /* VEX_LEN_XOP_09_83_W_0 */
7469 {
7470 { "vfrczsd", { XM, EXq }, 0 },
7471 },
7472
7473 /* VEX_LEN_XOP_09_90 */
7474 {
7475 { "vprotb", { XM, EXx, VexW }, 0 },
7476 },
7477
7478 /* VEX_LEN_XOP_09_91 */
7479 {
7480 { "vprotw", { XM, EXx, VexW }, 0 },
7481 },
7482
7483 /* VEX_LEN_XOP_09_92 */
7484 {
7485 { "vprotd", { XM, EXx, VexW }, 0 },
7486 },
7487
7488 /* VEX_LEN_XOP_09_93 */
7489 {
7490 { "vprotq", { XM, EXx, VexW }, 0 },
7491 },
7492
7493 /* VEX_LEN_XOP_09_94 */
7494 {
7495 { "vpshlb", { XM, EXx, VexW }, 0 },
7496 },
7497
7498 /* VEX_LEN_XOP_09_95 */
7499 {
7500 { "vpshlw", { XM, EXx, VexW }, 0 },
7501 },
7502
7503 /* VEX_LEN_XOP_09_96 */
7504 {
7505 { "vpshld", { XM, EXx, VexW }, 0 },
7506 },
7507
7508 /* VEX_LEN_XOP_09_97 */
7509 {
7510 { "vpshlq", { XM, EXx, VexW }, 0 },
7511 },
7512
7513 /* VEX_LEN_XOP_09_98 */
7514 {
7515 { "vpshab", { XM, EXx, VexW }, 0 },
7516 },
7517
7518 /* VEX_LEN_XOP_09_99 */
7519 {
7520 { "vpshaw", { XM, EXx, VexW }, 0 },
7521 },
7522
7523 /* VEX_LEN_XOP_09_9A */
7524 {
7525 { "vpshad", { XM, EXx, VexW }, 0 },
7526 },
7527
7528 /* VEX_LEN_XOP_09_9B */
7529 {
7530 { "vpshaq", { XM, EXx, VexW }, 0 },
7531 },
7532
7533 /* VEX_LEN_XOP_09_C1 */
7534 {
7535 { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7536 },
7537
7538 /* VEX_LEN_XOP_09_C2 */
7539 {
7540 { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7541 },
7542
7543 /* VEX_LEN_XOP_09_C3 */
7544 {
7545 { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7546 },
7547
7548 /* VEX_LEN_XOP_09_C6 */
7549 {
7550 { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7551 },
7552
7553 /* VEX_LEN_XOP_09_C7 */
7554 {
7555 { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7556 },
7557
7558 /* VEX_LEN_XOP_09_CB */
7559 {
7560 { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7561 },
7562
7563 /* VEX_LEN_XOP_09_D1 */
7564 {
7565 { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7566 },
7567
7568 /* VEX_LEN_XOP_09_D2 */
7569 {
7570 { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7571 },
7572
7573 /* VEX_LEN_XOP_09_D3 */
7574 {
7575 { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7576 },
7577
7578 /* VEX_LEN_XOP_09_D6 */
7579 {
7580 { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7581 },
7582
7583 /* VEX_LEN_XOP_09_D7 */
7584 {
7585 { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7586 },
7587
7588 /* VEX_LEN_XOP_09_DB */
7589 {
7590 { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7591 },
7592
7593 /* VEX_LEN_XOP_09_E1 */
7594 {
7595 { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7596 },
7597
7598 /* VEX_LEN_XOP_09_E2 */
7599 {
7600 { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7601 },
7602
7603 /* VEX_LEN_XOP_09_E3 */
7604 {
7605 { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7606 },
7607
7608 /* VEX_LEN_XOP_0A_12 */
7609 {
7610 { REG_TABLE (REG_XOP_0A_12_L_0) },
7611 },
7612 };
7613
7614 #include "i386-dis-evex-len.h"
7615
7616 static const struct dis386 vex_w_table[][2] = {
7617 {
7618 /* VEX_W_0F41_L_1_M_1 */
7619 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7620 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7621 },
7622 {
7623 /* VEX_W_0F42_L_1_M_1 */
7624 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7625 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7626 },
7627 {
7628 /* VEX_W_0F44_L_0_M_1 */
7629 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7630 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7631 },
7632 {
7633 /* VEX_W_0F45_L_1_M_1 */
7634 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7635 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7636 },
7637 {
7638 /* VEX_W_0F46_L_1_M_1 */
7639 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7640 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7641 },
7642 {
7643 /* VEX_W_0F47_L_1_M_1 */
7644 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7645 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7646 },
7647 {
7648 /* VEX_W_0F4A_L_1_M_1 */
7649 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7650 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7651 },
7652 {
7653 /* VEX_W_0F4B_L_1_M_1 */
7654 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7655 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7656 },
7657 {
7658 /* VEX_W_0F90_L_0 */
7659 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7660 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7661 },
7662 {
7663 /* VEX_W_0F91_L_0_M_0 */
7664 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7665 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7666 },
7667 {
7668 /* VEX_W_0F92_L_0_M_1 */
7669 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7670 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7671 },
7672 {
7673 /* VEX_W_0F93_L_0_M_1 */
7674 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7675 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7676 },
7677 {
7678 /* VEX_W_0F98_L_0_M_1 */
7679 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7680 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7681 },
7682 {
7683 /* VEX_W_0F99_L_0_M_1 */
7684 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7685 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7686 },
7687 {
7688 /* VEX_W_0F380C */
7689 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7690 },
7691 {
7692 /* VEX_W_0F380D */
7693 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7694 },
7695 {
7696 /* VEX_W_0F380E */
7697 { "vtestps", { XM, EXx }, PREFIX_DATA },
7698 },
7699 {
7700 /* VEX_W_0F380F */
7701 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7702 },
7703 {
7704 /* VEX_W_0F3813 */
7705 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7706 },
7707 {
7708 /* VEX_W_0F3816_L_1 */
7709 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7710 },
7711 {
7712 /* VEX_W_0F3818 */
7713 { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA },
7714 },
7715 {
7716 /* VEX_W_0F3819_L_1 */
7717 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7718 },
7719 {
7720 /* VEX_W_0F381A_L_1 */
7721 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7722 },
7723 {
7724 /* VEX_W_0F382C */
7725 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7726 },
7727 {
7728 /* VEX_W_0F382D */
7729 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7730 },
7731 {
7732 /* VEX_W_0F382E */
7733 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7734 },
7735 {
7736 /* VEX_W_0F382F */
7737 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7738 },
7739 {
7740 /* VEX_W_0F3836 */
7741 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7742 },
7743 {
7744 /* VEX_W_0F3846 */
7745 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7746 },
7747 {
7748 /* VEX_W_0F3849_X86_64_L_0 */
7749 { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7750 },
7751 {
7752 /* VEX_W_0F384B_X86_64_L_0 */
7753 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
7754 },
7755 {
7756 /* VEX_W_0F3850 */
7757 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7758 },
7759 {
7760 /* VEX_W_0F3851 */
7761 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7762 },
7763 {
7764 /* VEX_W_0F3852 */
7765 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA },
7766 },
7767 {
7768 /* VEX_W_0F3853 */
7769 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
7770 },
7771 {
7772 /* VEX_W_0F3858 */
7773 { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7774 },
7775 {
7776 /* VEX_W_0F3859 */
7777 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7778 },
7779 {
7780 /* VEX_W_0F385A_L_0 */
7781 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7782 },
7783 {
7784 /* VEX_W_0F385C_X86_64_L_0 */
7785 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
7786 },
7787 {
7788 /* VEX_W_0F385E_X86_64_L_0 */
7789 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
7790 },
7791 {
7792 /* VEX_W_0F386C_X86_64_L_0 */
7793 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
7794 },
7795 {
7796 /* VEX_W_0F3872_P_1 */
7797 { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7798 },
7799 {
7800 /* VEX_W_0F3878 */
7801 { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA },
7802 },
7803 {
7804 /* VEX_W_0F3879 */
7805 { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA },
7806 },
7807 {
7808 /* VEX_W_0F38B0 */
7809 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7810 },
7811 {
7812 /* VEX_W_0F38B1 */
7813 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7814 },
7815 {
7816 /* VEX_W_0F38B4 */
7817 { Bad_Opcode },
7818 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7819 },
7820 {
7821 /* VEX_W_0F38B5 */
7822 { Bad_Opcode },
7823 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7824 },
7825 {
7826 /* VEX_W_0F38CB_P_3 */
7827 { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
7828 },
7829 {
7830 /* VEX_W_0F38CC_P_3 */
7831 { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
7832 },
7833 {
7834 /* VEX_W_0F38CD_P_3 */
7835 { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
7836 },
7837 {
7838 /* VEX_W_0F38CF */
7839 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7840 },
7841 {
7842 /* VEX_W_0F38D2 */
7843 { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
7844 },
7845 {
7846 /* VEX_W_0F38D3 */
7847 { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
7848 },
7849 {
7850 /* VEX_W_0F38DA */
7851 { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
7852 },
7853 {
7854 /* VEX_W_0F3A00_L_1 */
7855 { Bad_Opcode },
7856 { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA },
7857 },
7858 {
7859 /* VEX_W_0F3A01_L_1 */
7860 { Bad_Opcode },
7861 { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7862 },
7863 {
7864 /* VEX_W_0F3A02 */
7865 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7866 },
7867 {
7868 /* VEX_W_0F3A04 */
7869 { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7870 },
7871 {
7872 /* VEX_W_0F3A05 */
7873 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7874 },
7875 {
7876 /* VEX_W_0F3A06_L_1 */
7877 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7878 },
7879 {
7880 /* VEX_W_0F3A18_L_1 */
7881 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7882 },
7883 {
7884 /* VEX_W_0F3A19_L_1 */
7885 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7886 },
7887 {
7888 /* VEX_W_0F3A1D */
7889 { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7890 },
7891 {
7892 /* VEX_W_0F3A38_L_1 */
7893 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7894 },
7895 {
7896 /* VEX_W_0F3A39_L_1 */
7897 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7898 },
7899 {
7900 /* VEX_W_0F3A46_L_1 */
7901 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7902 },
7903 {
7904 /* VEX_W_0F3A4A */
7905 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7906 },
7907 {
7908 /* VEX_W_0F3A4B */
7909 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7910 },
7911 {
7912 /* VEX_W_0F3A4C */
7913 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7914 },
7915 {
7916 /* VEX_W_0F3ACE */
7917 { Bad_Opcode },
7918 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7919 },
7920 {
7921 /* VEX_W_0F3ACF */
7922 { Bad_Opcode },
7923 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7924 },
7925 {
7926 /* VEX_W_0F3ADE */
7927 { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
7928 },
7929 {
7930 /* VEX_W_MAP7_F6_L_0 */
7931 { REG_TABLE (REG_VEX_MAP7_F6_L_0_W_0) },
7932 },
7933 {
7934 /* VEX_W_MAP7_F8_L_0 */
7935 { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
7936 },
7937 /* VEX_W_XOP_08_85_L_0 */
7938 {
7939 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7940 },
7941 /* VEX_W_XOP_08_86_L_0 */
7942 {
7943 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7944 },
7945 /* VEX_W_XOP_08_87_L_0 */
7946 {
7947 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7948 },
7949 /* VEX_W_XOP_08_8E_L_0 */
7950 {
7951 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7952 },
7953 /* VEX_W_XOP_08_8F_L_0 */
7954 {
7955 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7956 },
7957 /* VEX_W_XOP_08_95_L_0 */
7958 {
7959 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7960 },
7961 /* VEX_W_XOP_08_96_L_0 */
7962 {
7963 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7964 },
7965 /* VEX_W_XOP_08_97_L_0 */
7966 {
7967 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7968 },
7969 /* VEX_W_XOP_08_9E_L_0 */
7970 {
7971 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7972 },
7973 /* VEX_W_XOP_08_9F_L_0 */
7974 {
7975 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7976 },
7977 /* VEX_W_XOP_08_A6_L_0 */
7978 {
7979 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7980 },
7981 /* VEX_W_XOP_08_B6_L_0 */
7982 {
7983 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7984 },
7985 /* VEX_W_XOP_08_C0_L_0 */
7986 {
7987 { "vprotb", { XM, EXx, Ib }, 0 },
7988 },
7989 /* VEX_W_XOP_08_C1_L_0 */
7990 {
7991 { "vprotw", { XM, EXx, Ib }, 0 },
7992 },
7993 /* VEX_W_XOP_08_C2_L_0 */
7994 {
7995 { "vprotd", { XM, EXx, Ib }, 0 },
7996 },
7997 /* VEX_W_XOP_08_C3_L_0 */
7998 {
7999 { "vprotq", { XM, EXx, Ib }, 0 },
8000 },
8001 /* VEX_W_XOP_08_CC_L_0 */
8002 {
8003 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
8004 },
8005 /* VEX_W_XOP_08_CD_L_0 */
8006 {
8007 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
8008 },
8009 /* VEX_W_XOP_08_CE_L_0 */
8010 {
8011 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
8012 },
8013 /* VEX_W_XOP_08_CF_L_0 */
8014 {
8015 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
8016 },
8017 /* VEX_W_XOP_08_EC_L_0 */
8018 {
8019 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8020 },
8021 /* VEX_W_XOP_08_ED_L_0 */
8022 {
8023 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8024 },
8025 /* VEX_W_XOP_08_EE_L_0 */
8026 {
8027 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8028 },
8029 /* VEX_W_XOP_08_EF_L_0 */
8030 {
8031 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8032 },
8033 /* VEX_W_XOP_09_80 */
8034 {
8035 { "vfrczps", { XM, EXx }, 0 },
8036 },
8037 /* VEX_W_XOP_09_81 */
8038 {
8039 { "vfrczpd", { XM, EXx }, 0 },
8040 },
8041 /* VEX_W_XOP_09_82 */
8042 {
8043 { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
8044 },
8045 /* VEX_W_XOP_09_83 */
8046 {
8047 { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
8048 },
8049 /* VEX_W_XOP_09_C1_L_0 */
8050 {
8051 { "vphaddbw", { XM, EXxmm }, 0 },
8052 },
8053 /* VEX_W_XOP_09_C2_L_0 */
8054 {
8055 { "vphaddbd", { XM, EXxmm }, 0 },
8056 },
8057 /* VEX_W_XOP_09_C3_L_0 */
8058 {
8059 { "vphaddbq", { XM, EXxmm }, 0 },
8060 },
8061 /* VEX_W_XOP_09_C6_L_0 */
8062 {
8063 { "vphaddwd", { XM, EXxmm }, 0 },
8064 },
8065 /* VEX_W_XOP_09_C7_L_0 */
8066 {
8067 { "vphaddwq", { XM, EXxmm }, 0 },
8068 },
8069 /* VEX_W_XOP_09_CB_L_0 */
8070 {
8071 { "vphadddq", { XM, EXxmm }, 0 },
8072 },
8073 /* VEX_W_XOP_09_D1_L_0 */
8074 {
8075 { "vphaddubw", { XM, EXxmm }, 0 },
8076 },
8077 /* VEX_W_XOP_09_D2_L_0 */
8078 {
8079 { "vphaddubd", { XM, EXxmm }, 0 },
8080 },
8081 /* VEX_W_XOP_09_D3_L_0 */
8082 {
8083 { "vphaddubq", { XM, EXxmm }, 0 },
8084 },
8085 /* VEX_W_XOP_09_D6_L_0 */
8086 {
8087 { "vphadduwd", { XM, EXxmm }, 0 },
8088 },
8089 /* VEX_W_XOP_09_D7_L_0 */
8090 {
8091 { "vphadduwq", { XM, EXxmm }, 0 },
8092 },
8093 /* VEX_W_XOP_09_DB_L_0 */
8094 {
8095 { "vphaddudq", { XM, EXxmm }, 0 },
8096 },
8097 /* VEX_W_XOP_09_E1_L_0 */
8098 {
8099 { "vphsubbw", { XM, EXxmm }, 0 },
8100 },
8101 /* VEX_W_XOP_09_E2_L_0 */
8102 {
8103 { "vphsubwd", { XM, EXxmm }, 0 },
8104 },
8105 /* VEX_W_XOP_09_E3_L_0 */
8106 {
8107 { "vphsubdq", { XM, EXxmm }, 0 },
8108 },
8109
8110 #include "i386-dis-evex-w.h"
8111 };
8112
8113 static const struct dis386 mod_table[][2] = {
8114 {
8115 /* MOD_62_32BIT */
8116 { "bound{S|}", { Gv, Ma }, 0 },
8117 { EVEX_TABLE () },
8118 },
8119 {
8120 /* MOD_C4_32BIT */
8121 { "lesS", { Gv, Mp }, 0 },
8122 { VEX_C4_TABLE () },
8123 },
8124 {
8125 /* MOD_C5_32BIT */
8126 { "ldsS", { Gv, Mp }, 0 },
8127 { VEX_C5_TABLE () },
8128 },
8129 {
8130 /* MOD_0F01_REG_0 */
8131 { X86_64_TABLE (X86_64_0F01_REG_0) },
8132 { RM_TABLE (RM_0F01_REG_0) },
8133 },
8134 {
8135 /* MOD_0F01_REG_1 */
8136 { X86_64_TABLE (X86_64_0F01_REG_1) },
8137 { RM_TABLE (RM_0F01_REG_1) },
8138 },
8139 {
8140 /* MOD_0F01_REG_2 */
8141 { X86_64_TABLE (X86_64_0F01_REG_2) },
8142 { RM_TABLE (RM_0F01_REG_2) },
8143 },
8144 {
8145 /* MOD_0F01_REG_3 */
8146 { X86_64_TABLE (X86_64_0F01_REG_3) },
8147 { RM_TABLE (RM_0F01_REG_3) },
8148 },
8149 {
8150 /* MOD_0F01_REG_5 */
8151 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8152 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8153 },
8154 {
8155 /* MOD_0F01_REG_7 */
8156 { "invlpg", { Mb }, 0 },
8157 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8158 },
8159 {
8160 /* MOD_0F12_PREFIX_0 */
8161 { "%XEVmovlpYX", { XM, Vex, EXq }, 0 },
8162 { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8163 },
8164 {
8165 /* MOD_0F16_PREFIX_0 */
8166 { "%XEVmovhpYX", { XM, Vex, EXq }, 0 },
8167 { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8168 },
8169 {
8170 /* MOD_0F18_REG_0 */
8171 { "prefetchnta", { Mb }, 0 },
8172 { "nopQ", { Ev }, 0 },
8173 },
8174 {
8175 /* MOD_0F18_REG_1 */
8176 { "prefetcht0", { Mb }, 0 },
8177 { "nopQ", { Ev }, 0 },
8178 },
8179 {
8180 /* MOD_0F18_REG_2 */
8181 { "prefetcht1", { Mb }, 0 },
8182 { "nopQ", { Ev }, 0 },
8183 },
8184 {
8185 /* MOD_0F18_REG_3 */
8186 { "prefetcht2", { Mb }, 0 },
8187 { "nopQ", { Ev }, 0 },
8188 },
8189 {
8190 /* MOD_0F18_REG_6 */
8191 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8192 { "nopQ", { Ev }, 0 },
8193 },
8194 {
8195 /* MOD_0F18_REG_7 */
8196 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8197 { "nopQ", { Ev }, 0 },
8198 },
8199 {
8200 /* MOD_0F1A_PREFIX_0 */
8201 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8202 { "nopQ", { Ev }, 0 },
8203 },
8204 {
8205 /* MOD_0F1B_PREFIX_0 */
8206 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8207 { "nopQ", { Ev }, 0 },
8208 },
8209 {
8210 /* MOD_0F1B_PREFIX_1 */
8211 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8212 { "nopQ", { Ev }, PREFIX_IGNORED },
8213 },
8214 {
8215 /* MOD_0F1C_PREFIX_0 */
8216 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8217 { "nopQ", { Ev }, 0 },
8218 },
8219 {
8220 /* MOD_0F1E_PREFIX_1 */
8221 { "nopQ", { Ev }, PREFIX_IGNORED },
8222 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8223 },
8224 {
8225 /* MOD_0FAE_REG_0 */
8226 { "fxsave", { FXSAVE }, 0 },
8227 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8228 },
8229 {
8230 /* MOD_0FAE_REG_1 */
8231 { "fxrstor", { FXSAVE }, 0 },
8232 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8233 },
8234 {
8235 /* MOD_0FAE_REG_2 */
8236 { "ldmxcsr", { Md }, 0 },
8237 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8238 },
8239 {
8240 /* MOD_0FAE_REG_3 */
8241 { "stmxcsr", { Md }, 0 },
8242 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8243 },
8244 {
8245 /* MOD_0FAE_REG_4 */
8246 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8247 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8248 },
8249 {
8250 /* MOD_0FAE_REG_5 */
8251 { "xrstor", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8252 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8253 },
8254 {
8255 /* MOD_0FAE_REG_6 */
8256 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8257 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8258 },
8259 {
8260 /* MOD_0FAE_REG_7 */
8261 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8262 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8263 },
8264 {
8265 /* MOD_0FC7_REG_6 */
8266 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8267 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8268 },
8269 {
8270 /* MOD_0FC7_REG_7 */
8271 { "vmptrst", { Mq }, 0 },
8272 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8273 },
8274 {
8275 /* MOD_0F38DC_PREFIX_1 */
8276 { "aesenc128kl", { XM, M }, 0 },
8277 { "loadiwkey", { XM, EXx }, 0 },
8278 },
8279 /* MOD_0F38F8 */
8280 {
8281 { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8282 { X86_64_TABLE (X86_64_0F38F8_M_1) },
8283 },
8284 {
8285 /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8286 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8287 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8288 },
8289
8290 #include "i386-dis-evex-mod.h"
8291 };
8292
8293 static const struct dis386 rm_table[][8] = {
8294 {
8295 /* RM_C6_REG_7 */
8296 { "xabort", { Skip_MODRM, Ib }, 0 },
8297 },
8298 {
8299 /* RM_C7_REG_7 */
8300 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8301 },
8302 {
8303 /* RM_0F01_REG_0 */
8304 { "enclv", { Skip_MODRM }, 0 },
8305 { "vmcall", { Skip_MODRM }, 0 },
8306 { "vmlaunch", { Skip_MODRM }, 0 },
8307 { "vmresume", { Skip_MODRM }, 0 },
8308 { "vmxoff", { Skip_MODRM }, 0 },
8309 { "pconfig", { Skip_MODRM }, 0 },
8310 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8311 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8312 },
8313 {
8314 /* RM_0F01_REG_1 */
8315 { "monitor", { { OP_Monitor, 0 } }, 0 },
8316 { "mwait", { { OP_Mwait, 0 } }, 0 },
8317 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8318 { "stac", { Skip_MODRM }, 0 },
8319 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8320 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8321 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8322 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8323 },
8324 {
8325 /* RM_0F01_REG_2 */
8326 { "xgetbv", { Skip_MODRM }, 0 },
8327 { "xsetbv", { Skip_MODRM }, 0 },
8328 { Bad_Opcode },
8329 { Bad_Opcode },
8330 { "vmfunc", { Skip_MODRM }, 0 },
8331 { "xend", { Skip_MODRM }, 0 },
8332 { "xtest", { Skip_MODRM }, 0 },
8333 { "enclu", { Skip_MODRM }, 0 },
8334 },
8335 {
8336 /* RM_0F01_REG_3 */
8337 { "vmrun", { Skip_MODRM }, 0 },
8338 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8339 { "vmload", { Skip_MODRM }, 0 },
8340 { "vmsave", { Skip_MODRM }, 0 },
8341 { "stgi", { Skip_MODRM }, 0 },
8342 { "clgi", { Skip_MODRM }, 0 },
8343 { "skinit", { Skip_MODRM }, 0 },
8344 { "invlpga", { Skip_MODRM }, 0 },
8345 },
8346 {
8347 /* RM_0F01_REG_5_MOD_3 */
8348 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8349 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8350 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8351 { Bad_Opcode },
8352 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8353 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8354 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8355 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8356 },
8357 {
8358 /* RM_0F01_REG_7_MOD_3 */
8359 { "swapgs", { Skip_MODRM }, 0 },
8360 { "rdtscp", { Skip_MODRM }, 0 },
8361 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8362 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8363 { "clzero", { Skip_MODRM }, 0 },
8364 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8365 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8366 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8367 },
8368 {
8369 /* RM_0F1E_P_1_MOD_3_REG_7 */
8370 { "nopQ", { Ev }, PREFIX_IGNORED },
8371 { "nopQ", { Ev }, PREFIX_IGNORED },
8372 { "endbr64", { Skip_MODRM }, 0 },
8373 { "endbr32", { Skip_MODRM }, 0 },
8374 { "nopQ", { Ev }, PREFIX_IGNORED },
8375 { "nopQ", { Ev }, PREFIX_IGNORED },
8376 { "nopQ", { Ev }, PREFIX_IGNORED },
8377 { "nopQ", { Ev }, PREFIX_IGNORED },
8378 },
8379 {
8380 /* RM_0FAE_REG_6_MOD_3 */
8381 { "mfence", { Skip_MODRM }, 0 },
8382 },
8383 {
8384 /* RM_0FAE_REG_7_MOD_3 */
8385 { "sfence", { Skip_MODRM }, 0 },
8386 },
8387 {
8388 /* RM_0F3A0F_P_1_R_0 */
8389 { "hreset", { Skip_MODRM, Ib }, 0 },
8390 },
8391 {
8392 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8393 { "tilerelease", { Skip_MODRM }, 0 },
8394 },
8395 {
8396 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8397 { "tilezero", { TMM, Skip_MODRM }, 0 },
8398 },
8399 };
8400
8401 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8402
8403 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8404 in conflict with actual prefix opcodes. */
8405 #define REP_PREFIX 0x01
8406 #define XACQUIRE_PREFIX 0x02
8407 #define XRELEASE_PREFIX 0x03
8408 #define BND_PREFIX 0x04
8409 #define NOTRACK_PREFIX 0x05
8410
8411 static enum {
8412 ckp_okay,
8413 ckp_bogus,
8414 ckp_fetch_error,
8415 }
8416 ckprefix (instr_info *ins)
8417 {
8418 int i, length;
8419 uint8_t newrex;
8420
8421 i = 0;
8422 length = 0;
8423 /* The maximum instruction length is 15bytes. */
8424 while (length < MAX_CODE_LENGTH - 1)
8425 {
8426 if (!fetch_code (ins->info, ins->codep + 1))
8427 return ckp_fetch_error;
8428 newrex = 0;
8429 switch (*ins->codep)
8430 {
8431 /* REX prefixes family. */
8432 case 0x40:
8433 case 0x41:
8434 case 0x42:
8435 case 0x43:
8436 case 0x44:
8437 case 0x45:
8438 case 0x46:
8439 case 0x47:
8440 case 0x48:
8441 case 0x49:
8442 case 0x4a:
8443 case 0x4b:
8444 case 0x4c:
8445 case 0x4d:
8446 case 0x4e:
8447 case 0x4f:
8448 if (ins->address_mode == mode_64bit)
8449 newrex = *ins->codep;
8450 else
8451 return ckp_okay;
8452 ins->last_rex_prefix = i;
8453 break;
8454 /* REX2 must be the last prefix. */
8455 case REX2_OPCODE:
8456 if (ins->address_mode == mode_64bit)
8457 {
8458 if (ins->last_rex_prefix >= 0)
8459 return ckp_bogus;
8460
8461 ins->codep++;
8462 if (!fetch_code (ins->info, ins->codep + 1))
8463 return ckp_fetch_error;
8464 ins->rex2_payload = *ins->codep;
8465 ins->rex2 = ins->rex2_payload >> 4;
8466 ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8467 ins->codep++;
8468 ins->last_rex2_prefix = i;
8469 ins->all_prefixes[i] = REX2_OPCODE;
8470 }
8471 return ckp_okay;
8472 case 0xf3:
8473 ins->prefixes |= PREFIX_REPZ;
8474 ins->last_repz_prefix = i;
8475 break;
8476 case 0xf2:
8477 ins->prefixes |= PREFIX_REPNZ;
8478 ins->last_repnz_prefix = i;
8479 break;
8480 case 0xf0:
8481 ins->prefixes |= PREFIX_LOCK;
8482 ins->last_lock_prefix = i;
8483 break;
8484 case 0x2e:
8485 ins->prefixes |= PREFIX_CS;
8486 ins->last_seg_prefix = i;
8487 if (ins->address_mode != mode_64bit)
8488 ins->active_seg_prefix = PREFIX_CS;
8489 break;
8490 case 0x36:
8491 ins->prefixes |= PREFIX_SS;
8492 ins->last_seg_prefix = i;
8493 if (ins->address_mode != mode_64bit)
8494 ins->active_seg_prefix = PREFIX_SS;
8495 break;
8496 case 0x3e:
8497 ins->prefixes |= PREFIX_DS;
8498 ins->last_seg_prefix = i;
8499 if (ins->address_mode != mode_64bit)
8500 ins->active_seg_prefix = PREFIX_DS;
8501 break;
8502 case 0x26:
8503 ins->prefixes |= PREFIX_ES;
8504 ins->last_seg_prefix = i;
8505 if (ins->address_mode != mode_64bit)
8506 ins->active_seg_prefix = PREFIX_ES;
8507 break;
8508 case 0x64:
8509 ins->prefixes |= PREFIX_FS;
8510 ins->last_seg_prefix = i;
8511 ins->active_seg_prefix = PREFIX_FS;
8512 break;
8513 case 0x65:
8514 ins->prefixes |= PREFIX_GS;
8515 ins->last_seg_prefix = i;
8516 ins->active_seg_prefix = PREFIX_GS;
8517 break;
8518 case 0x66:
8519 ins->prefixes |= PREFIX_DATA;
8520 ins->last_data_prefix = i;
8521 break;
8522 case 0x67:
8523 ins->prefixes |= PREFIX_ADDR;
8524 ins->last_addr_prefix = i;
8525 break;
8526 case FWAIT_OPCODE:
8527 /* fwait is really an instruction. If there are prefixes
8528 before the fwait, they belong to the fwait, *not* to the
8529 following instruction. */
8530 ins->fwait_prefix = i;
8531 if (ins->prefixes || ins->rex)
8532 {
8533 ins->prefixes |= PREFIX_FWAIT;
8534 ins->codep++;
8535 /* This ensures that the previous REX prefixes are noticed
8536 as unused prefixes, as in the return case below. */
8537 return ins->rex ? ckp_bogus : ckp_okay;
8538 }
8539 ins->prefixes = PREFIX_FWAIT;
8540 break;
8541 default:
8542 return ckp_okay;
8543 }
8544 /* Rex is ignored when followed by another prefix. */
8545 if (ins->rex)
8546 return ckp_bogus;
8547 if (*ins->codep != FWAIT_OPCODE)
8548 ins->all_prefixes[i++] = *ins->codep;
8549 ins->rex = newrex;
8550 ins->codep++;
8551 length++;
8552 }
8553 return ckp_bogus;
8554 }
8555
8556 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8557 prefix byte. */
8558
8559 static const char *
8560 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8561 {
8562 static const char *rexes [16] =
8563 {
8564 "rex", /* 0x40 */
8565 "rex.B", /* 0x41 */
8566 "rex.X", /* 0x42 */
8567 "rex.XB", /* 0x43 */
8568 "rex.R", /* 0x44 */
8569 "rex.RB", /* 0x45 */
8570 "rex.RX", /* 0x46 */
8571 "rex.RXB", /* 0x47 */
8572 "rex.W", /* 0x48 */
8573 "rex.WB", /* 0x49 */
8574 "rex.WX", /* 0x4a */
8575 "rex.WXB", /* 0x4b */
8576 "rex.WR", /* 0x4c */
8577 "rex.WRB", /* 0x4d */
8578 "rex.WRX", /* 0x4e */
8579 "rex.WRXB", /* 0x4f */
8580 };
8581
8582 switch (pref)
8583 {
8584 /* REX prefixes family. */
8585 case 0x40:
8586 case 0x41:
8587 case 0x42:
8588 case 0x43:
8589 case 0x44:
8590 case 0x45:
8591 case 0x46:
8592 case 0x47:
8593 case 0x48:
8594 case 0x49:
8595 case 0x4a:
8596 case 0x4b:
8597 case 0x4c:
8598 case 0x4d:
8599 case 0x4e:
8600 case 0x4f:
8601 return rexes [pref - 0x40];
8602 case 0xf3:
8603 return "repz";
8604 case 0xf2:
8605 return "repnz";
8606 case 0xf0:
8607 return "lock";
8608 case 0x2e:
8609 return "cs";
8610 case 0x36:
8611 return "ss";
8612 case 0x3e:
8613 return "ds";
8614 case 0x26:
8615 return "es";
8616 case 0x64:
8617 return "fs";
8618 case 0x65:
8619 return "gs";
8620 case 0x66:
8621 return (sizeflag & DFLAG) ? "data16" : "data32";
8622 case 0x67:
8623 if (mode == mode_64bit)
8624 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8625 else
8626 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8627 case FWAIT_OPCODE:
8628 return "fwait";
8629 case REP_PREFIX:
8630 return "rep";
8631 case XACQUIRE_PREFIX:
8632 return "xacquire";
8633 case XRELEASE_PREFIX:
8634 return "xrelease";
8635 case BND_PREFIX:
8636 return "bnd";
8637 case NOTRACK_PREFIX:
8638 return "notrack";
8639 case REX2_OPCODE:
8640 return "rex2";
8641 default:
8642 return NULL;
8643 }
8644 }
8645
8646 void
8647 print_i386_disassembler_options (FILE *stream)
8648 {
8649 fprintf (stream, _("\n\
8650 The following i386/x86-64 specific disassembler options are supported for use\n\
8651 with the -M switch (multiple options should be separated by commas):\n"));
8652
8653 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8654 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8655 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8656 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8657 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8658 fprintf (stream, _(" att-mnemonic (AT&T syntax only)\n"
8659 " Display instruction with AT&T mnemonic\n"));
8660 fprintf (stream, _(" intel-mnemonic (AT&T syntax only)\n"
8661 " Display instruction with Intel mnemonic\n"));
8662 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8663 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8664 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8665 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8666 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8667 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8668 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8669 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8670 }
8671
8672 /* Bad opcode. */
8673 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8674
8675 /* Fetch error indicator. */
8676 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
8677
8678 static const struct dis386 map7_f6_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F6) };
8679 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
8680
8681 /* Get a pointer to struct dis386 with a valid name. */
8682
8683 static const struct dis386 *
8684 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8685 {
8686 int vindex, vex_table_index;
8687
8688 if (dp->name != NULL)
8689 return dp;
8690
8691 switch (dp->op[0].bytemode)
8692 {
8693 case USE_REG_TABLE:
8694 dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8695 break;
8696
8697 case USE_MOD_TABLE:
8698 vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8699 dp = &mod_table[dp->op[1].bytemode][vindex];
8700 break;
8701
8702 case USE_RM_TABLE:
8703 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8704 break;
8705
8706 case USE_PREFIX_TABLE:
8707 use_prefix_table:
8708 if (ins->need_vex)
8709 {
8710 /* The prefix in VEX is implicit. */
8711 switch (ins->vex.prefix)
8712 {
8713 case 0:
8714 vindex = 0;
8715 break;
8716 case REPE_PREFIX_OPCODE:
8717 vindex = 1;
8718 break;
8719 case DATA_PREFIX_OPCODE:
8720 vindex = 2;
8721 break;
8722 case REPNE_PREFIX_OPCODE:
8723 vindex = 3;
8724 break;
8725 default:
8726 abort ();
8727 break;
8728 }
8729 }
8730 else
8731 {
8732 int last_prefix = -1;
8733 int prefix = 0;
8734 vindex = 0;
8735 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8736 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8737 last one wins. */
8738 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8739 {
8740 if (ins->last_repz_prefix > ins->last_repnz_prefix)
8741 {
8742 vindex = 1;
8743 prefix = PREFIX_REPZ;
8744 last_prefix = ins->last_repz_prefix;
8745 }
8746 else
8747 {
8748 vindex = 3;
8749 prefix = PREFIX_REPNZ;
8750 last_prefix = ins->last_repnz_prefix;
8751 }
8752
8753 /* Check if prefix should be ignored. */
8754 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8755 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8756 & prefix) != 0
8757 && !prefix_table[dp->op[1].bytemode][vindex].name)
8758 vindex = 0;
8759 }
8760
8761 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8762 {
8763 vindex = 2;
8764 prefix = PREFIX_DATA;
8765 last_prefix = ins->last_data_prefix;
8766 }
8767
8768 if (vindex != 0)
8769 {
8770 ins->used_prefixes |= prefix;
8771 ins->all_prefixes[last_prefix] = 0;
8772 }
8773 }
8774 dp = &prefix_table[dp->op[1].bytemode][vindex];
8775 break;
8776
8777 case USE_X86_64_EVEX_FROM_VEX_TABLE:
8778 case USE_X86_64_EVEX_PFX_TABLE:
8779 case USE_X86_64_EVEX_W_TABLE:
8780 case USE_X86_64_EVEX_MEM_W_TABLE:
8781 ins->evex_type = evex_from_vex;
8782 /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
8783 EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0. */
8784 if (ins->address_mode != mode_64bit
8785 || (ins->vex.mask_register_specifier & 0x3) != 0
8786 || ins->vex.ll != 0
8787 || ins->vex.zeroing != 0
8788 || ins->vex.b)
8789 return &bad_opcode;
8790
8791 if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE)
8792 goto use_prefix_table;
8793 if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE)
8794 goto use_vex_w_table;
8795 if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE)
8796 {
8797 if (ins->modrm.mod == 3)
8798 return &bad_opcode;
8799 goto use_vex_w_table;
8800 }
8801
8802 /* Fall through. */
8803 case USE_X86_64_TABLE:
8804 vindex = ins->address_mode == mode_64bit ? 1 : 0;
8805 dp = &x86_64_table[dp->op[1].bytemode][vindex];
8806 break;
8807
8808 case USE_3BYTE_TABLE:
8809 if (ins->last_rex2_prefix >= 0)
8810 return &err_opcode;
8811 if (!fetch_code (ins->info, ins->codep + 2))
8812 return &err_opcode;
8813 vindex = *ins->codep++;
8814 dp = &three_byte_table[dp->op[1].bytemode][vindex];
8815 ins->end_codep = ins->codep;
8816 if (!fetch_modrm (ins))
8817 return &err_opcode;
8818 break;
8819
8820 case USE_VEX_LEN_TABLE:
8821 if (!ins->need_vex)
8822 abort ();
8823
8824 switch (ins->vex.length)
8825 {
8826 case 128:
8827 vindex = 0;
8828 break;
8829 case 512:
8830 /* This allows re-using in particular table entries where only
8831 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
8832 if (ins->vex.evex)
8833 {
8834 case 256:
8835 vindex = 1;
8836 break;
8837 }
8838 /* Fall through. */
8839 default:
8840 abort ();
8841 break;
8842 }
8843
8844 dp = &vex_len_table[dp->op[1].bytemode][vindex];
8845 break;
8846
8847 case USE_EVEX_LEN_TABLE:
8848 if (!ins->vex.evex)
8849 abort ();
8850
8851 switch (ins->vex.length)
8852 {
8853 case 128:
8854 vindex = 0;
8855 break;
8856 case 256:
8857 vindex = 1;
8858 break;
8859 case 512:
8860 vindex = 2;
8861 break;
8862 default:
8863 abort ();
8864 break;
8865 }
8866
8867 dp = &evex_len_table[dp->op[1].bytemode][vindex];
8868 break;
8869
8870 case USE_XOP_8F_TABLE:
8871 if (!fetch_code (ins->info, ins->codep + 3))
8872 return &err_opcode;
8873 ins->rex = ~(*ins->codep >> 5) & 0x7;
8874
8875 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
8876 switch ((*ins->codep & 0x1f))
8877 {
8878 default:
8879 dp = &bad_opcode;
8880 return dp;
8881 case 0x8:
8882 vex_table_index = XOP_08;
8883 break;
8884 case 0x9:
8885 vex_table_index = XOP_09;
8886 break;
8887 case 0xa:
8888 vex_table_index = XOP_0A;
8889 break;
8890 }
8891 ins->codep++;
8892 ins->vex.w = *ins->codep & 0x80;
8893 if (ins->vex.w && ins->address_mode == mode_64bit)
8894 ins->rex |= REX_W;
8895
8896 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8897 if (ins->address_mode != mode_64bit)
8898 {
8899 /* In 16/32-bit mode REX_B is silently ignored. */
8900 ins->rex &= ~REX_B;
8901 }
8902
8903 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8904 switch ((*ins->codep & 0x3))
8905 {
8906 case 0:
8907 break;
8908 case 1:
8909 ins->vex.prefix = DATA_PREFIX_OPCODE;
8910 break;
8911 case 2:
8912 ins->vex.prefix = REPE_PREFIX_OPCODE;
8913 break;
8914 case 3:
8915 ins->vex.prefix = REPNE_PREFIX_OPCODE;
8916 break;
8917 }
8918 ins->need_vex = 3;
8919 ins->codep++;
8920 vindex = *ins->codep++;
8921 dp = &xop_table[vex_table_index][vindex];
8922
8923 ins->end_codep = ins->codep;
8924 if (!fetch_modrm (ins))
8925 return &err_opcode;
8926
8927 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
8928 having to decode the bits for every otherwise valid encoding. */
8929 if (ins->vex.prefix)
8930 return &bad_opcode;
8931 break;
8932
8933 case USE_VEX_C4_TABLE:
8934 /* VEX prefix. */
8935 if (!fetch_code (ins->info, ins->codep + 3))
8936 return &err_opcode;
8937 ins->rex = ~(*ins->codep >> 5) & 0x7;
8938 switch ((*ins->codep & 0x1f))
8939 {
8940 default:
8941 dp = &bad_opcode;
8942 return dp;
8943 case 0x1:
8944 vex_table_index = VEX_0F;
8945 break;
8946 case 0x2:
8947 vex_table_index = VEX_0F38;
8948 break;
8949 case 0x3:
8950 vex_table_index = VEX_0F3A;
8951 break;
8952 case 0x7:
8953 vex_table_index = VEX_MAP7;
8954 break;
8955 }
8956 ins->codep++;
8957 ins->vex.w = *ins->codep & 0x80;
8958 if (ins->address_mode == mode_64bit)
8959 {
8960 if (ins->vex.w)
8961 ins->rex |= REX_W;
8962 }
8963 else
8964 {
8965 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
8966 is ignored, other REX bits are 0 and the highest bit in
8967 VEX.vvvv is also ignored (but we mustn't clear it here). */
8968 ins->rex = 0;
8969 }
8970 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8971 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8972 switch ((*ins->codep & 0x3))
8973 {
8974 case 0:
8975 break;
8976 case 1:
8977 ins->vex.prefix = DATA_PREFIX_OPCODE;
8978 break;
8979 case 2:
8980 ins->vex.prefix = REPE_PREFIX_OPCODE;
8981 break;
8982 case 3:
8983 ins->vex.prefix = REPNE_PREFIX_OPCODE;
8984 break;
8985 }
8986 ins->need_vex = 3;
8987 ins->codep++;
8988 vindex = *ins->codep++;
8989 ins->condition_code = vindex & 0xf;
8990 if (vex_table_index != VEX_MAP7)
8991 dp = &vex_table[vex_table_index][vindex];
8992 else if (vindex == 0xf6)
8993 dp = &map7_f6_opcode;
8994 else if (vindex == 0xf8)
8995 dp = &map7_f8_opcode;
8996 else
8997 dp = &bad_opcode;
8998 ins->end_codep = ins->codep;
8999 /* There is no MODRM byte for VEX0F 77. */
9000 if ((vex_table_index != VEX_0F || vindex != 0x77)
9001 && !fetch_modrm (ins))
9002 return &err_opcode;
9003 break;
9004
9005 case USE_VEX_C5_TABLE:
9006 /* VEX prefix. */
9007 if (!fetch_code (ins->info, ins->codep + 2))
9008 return &err_opcode;
9009 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9010
9011 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9012 VEX.vvvv is 1. */
9013 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9014 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9015 switch ((*ins->codep & 0x3))
9016 {
9017 case 0:
9018 break;
9019 case 1:
9020 ins->vex.prefix = DATA_PREFIX_OPCODE;
9021 break;
9022 case 2:
9023 ins->vex.prefix = REPE_PREFIX_OPCODE;
9024 break;
9025 case 3:
9026 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9027 break;
9028 }
9029 ins->need_vex = 2;
9030 ins->codep++;
9031 vindex = *ins->codep++;
9032 dp = &vex_table[VEX_0F][vindex];
9033 ins->end_codep = ins->codep;
9034 /* There is no MODRM byte for VEX 77. */
9035 if (vindex != 0x77 && !fetch_modrm (ins))
9036 return &err_opcode;
9037 break;
9038
9039 case USE_VEX_W_TABLE:
9040 use_vex_w_table:
9041 if (!ins->need_vex)
9042 abort ();
9043
9044 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9045 break;
9046
9047 case USE_EVEX_TABLE:
9048 ins->two_source_ops = false;
9049 /* EVEX prefix. */
9050 ins->vex.evex = true;
9051 if (!fetch_code (ins->info, ins->codep + 4))
9052 return &err_opcode;
9053 /* The first byte after 0x62. */
9054 if (*ins->codep & 0x8)
9055 ins->rex2 |= REX_B;
9056 if (!(*ins->codep & 0x10))
9057 ins->rex2 |= REX_R;
9058
9059 ins->rex = ~(*ins->codep >> 5) & 0x7;
9060 switch (*ins->codep & 0x7)
9061 {
9062 default:
9063 return &bad_opcode;
9064 case 0x1:
9065 vex_table_index = EVEX_0F;
9066 break;
9067 case 0x2:
9068 vex_table_index = EVEX_0F38;
9069 break;
9070 case 0x3:
9071 vex_table_index = EVEX_0F3A;
9072 break;
9073 case 0x4:
9074 vex_table_index = EVEX_MAP4;
9075 ins->evex_type = evex_from_legacy;
9076 if (ins->address_mode != mode_64bit)
9077 return &bad_opcode;
9078 ins->rex |= REX_OPCODE;
9079 break;
9080 case 0x5:
9081 vex_table_index = EVEX_MAP5;
9082 break;
9083 case 0x6:
9084 vex_table_index = EVEX_MAP6;
9085 break;
9086 case 0x7:
9087 vex_table_index = EVEX_MAP7;
9088 break;
9089 }
9090
9091 /* The second byte after 0x62. */
9092 ins->codep++;
9093 ins->vex.w = *ins->codep & 0x80;
9094 if (ins->vex.w && ins->address_mode == mode_64bit)
9095 ins->rex |= REX_W;
9096
9097 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9098
9099 if (!(*ins->codep & 0x4))
9100 ins->rex2 |= REX_X;
9101
9102 ins->vex.u = *ins->codep & 0x4;
9103
9104 switch ((*ins->codep & 0x3))
9105 {
9106 case 0:
9107 break;
9108 case 1:
9109 ins->vex.prefix = DATA_PREFIX_OPCODE;
9110 break;
9111 case 2:
9112 ins->vex.prefix = REPE_PREFIX_OPCODE;
9113 break;
9114 case 3:
9115 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9116 break;
9117 }
9118
9119 /* The third byte after 0x62. */
9120 ins->codep++;
9121
9122 /* Remember the static rounding bits. */
9123 ins->vex.ll = (*ins->codep >> 5) & 3;
9124 ins->vex.b = *ins->codep & 0x10;
9125
9126 ins->vex.v = *ins->codep & 0x8;
9127 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9128 ins->vex.scc = *ins->codep & 0xf;
9129 ins->vex.zeroing = *ins->codep & 0x80;
9130 /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared
9131 when it's an evex_default one. */
9132 ins->vex.nf = *ins->codep & 0x4;
9133
9134 if (ins->address_mode != mode_64bit)
9135 {
9136 /* Report bad for !evex_default and when two fixed values of evex
9137 change. */
9138 if (ins->evex_type != evex_default || (ins->rex2 & REX_B)
9139 || ((ins->rex2 & REX_X) && (ins->modrm.mod != 3)))
9140 return &bad_opcode;
9141 /* In 16/32-bit mode silently ignore following bits. */
9142 ins->rex &= ~REX_B;
9143 ins->rex2 &= ~REX_R;
9144 }
9145
9146 ins->need_vex = 4;
9147
9148 ins->codep++;
9149 vindex = *ins->codep++;
9150 ins->condition_code = vindex & 0xf;
9151 if (vex_table_index != EVEX_MAP7)
9152 dp = &evex_table[vex_table_index][vindex];
9153 else if (vindex == 0xf8)
9154 dp = &map7_f8_opcode;
9155 else if (vindex == 0xf6)
9156 dp = &map7_f6_opcode;
9157 else
9158 dp = &bad_opcode;
9159 ins->end_codep = ins->codep;
9160 if (!fetch_modrm (ins))
9161 return &err_opcode;
9162
9163 /* When modrm.mod != 3, the U bit is used by APX for bit X4.
9164 When modrm.mod == 3, the U bit is used by AVX10. The U bit and
9165 the b bit should not be zero at the same time. */
9166 if (ins->modrm.mod == 3 && !ins->vex.u && !ins->vex.b)
9167 return &bad_opcode;
9168
9169 /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9170 which has the same encoding as vex.length == 128 and they can share
9171 the same processing with vex.length in OP_VEX. */
9172 if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9173 {
9174 if (ins->vex.u)
9175 ins->vex.length = 512;
9176 else
9177 ins->vex.length = 256;
9178 }
9179 else
9180 {
9181 switch (ins->vex.ll)
9182 {
9183 case 0x0:
9184 ins->vex.length = 128;
9185 break;
9186 case 0x1:
9187 ins->vex.length = 256;
9188 break;
9189 case 0x2:
9190 ins->vex.length = 512;
9191 break;
9192 default:
9193 return &bad_opcode;
9194 }
9195 }
9196 break;
9197
9198 case 0:
9199 dp = &bad_opcode;
9200 break;
9201
9202 default:
9203 abort ();
9204 }
9205
9206 if (dp->name != NULL)
9207 return dp;
9208 else
9209 return get_valid_dis386 (dp, ins);
9210 }
9211
9212 static bool
9213 get_sib (instr_info *ins, int sizeflag)
9214 {
9215 /* If modrm.mod == 3, operand must be register. */
9216 if (ins->need_modrm
9217 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9218 && ins->modrm.mod != 3
9219 && ins->modrm.rm == 4)
9220 {
9221 if (!fetch_code (ins->info, ins->codep + 2))
9222 return false;
9223 ins->sib.index = (ins->codep[1] >> 3) & 7;
9224 ins->sib.scale = (ins->codep[1] >> 6) & 3;
9225 ins->sib.base = ins->codep[1] & 7;
9226 ins->has_sib = true;
9227 }
9228 else
9229 ins->has_sib = false;
9230
9231 return true;
9232 }
9233
9234 /* Like oappend_with_style (below) but always with text style. */
9235
9236 static void
9237 oappend (instr_info *ins, const char *s)
9238 {
9239 oappend_with_style (ins, s, dis_style_text);
9240 }
9241
9242 /* Like oappend (above), but S is a string starting with '%'. In
9243 Intel syntax, the '%' is elided. */
9244
9245 static void
9246 oappend_register (instr_info *ins, const char *s)
9247 {
9248 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9249 }
9250
9251 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9252 STYLE is the default style to use in the fprintf_styled_func calls,
9253 however, FMT might include embedded style markers (see oappend_style),
9254 these embedded markers are not printed, but instead change the style
9255 used in the next fprintf_styled_func call. */
9256
9257 static void ATTRIBUTE_PRINTF_3
9258 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9259 const char *fmt, ...)
9260 {
9261 va_list ap;
9262 enum disassembler_style curr_style = style;
9263 const char *start, *curr;
9264 char staging_area[50];
9265
9266 va_start (ap, fmt);
9267 /* In particular print_insn()'s processing of op_txt[] can hand rather long
9268 strings here. Bypass vsnprintf() in such cases to avoid capacity issues
9269 with the staging area. */
9270 if (strcmp (fmt, "%s"))
9271 {
9272 int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9273
9274 va_end (ap);
9275
9276 if (res < 0)
9277 return;
9278
9279 if ((size_t) res >= sizeof (staging_area))
9280 abort ();
9281
9282 start = curr = staging_area;
9283 }
9284 else
9285 {
9286 start = curr = va_arg (ap, const char *);
9287 va_end (ap);
9288 }
9289
9290 do
9291 {
9292 if (*curr == '\0'
9293 || (*curr == STYLE_MARKER_CHAR
9294 && ISXDIGIT (*(curr + 1))
9295 && *(curr + 2) == STYLE_MARKER_CHAR))
9296 {
9297 /* Output content between our START position and CURR. */
9298 int len = curr - start;
9299 int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9300 "%.*s", len, start);
9301 if (n < 0)
9302 break;
9303
9304 if (*curr == '\0')
9305 break;
9306
9307 /* Skip over the initial STYLE_MARKER_CHAR. */
9308 ++curr;
9309
9310 /* Update the CURR_STYLE. As there are less than 16 styles, it
9311 is possible, that if the input is corrupted in some way, that
9312 we might set CURR_STYLE to an invalid value. Don't worry
9313 though, we check for this situation. */
9314 if (*curr >= '0' && *curr <= '9')
9315 curr_style = (enum disassembler_style) (*curr - '0');
9316 else if (*curr >= 'a' && *curr <= 'f')
9317 curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9318 else
9319 curr_style = dis_style_text;
9320
9321 /* Check for an invalid style having been selected. This should
9322 never happen, but it doesn't hurt to be a little paranoid. */
9323 if (curr_style > dis_style_comment_start)
9324 curr_style = dis_style_text;
9325
9326 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */
9327 curr += 2;
9328
9329 /* Reset the START to after the style marker. */
9330 start = curr;
9331 }
9332 else
9333 ++curr;
9334 }
9335 while (true);
9336 }
9337
9338 static int
9339 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9340 {
9341 const struct dis386 *dp;
9342 int i;
9343 int ret;
9344 char *op_txt[MAX_OPERANDS];
9345 int needcomma;
9346 bool intel_swap_2_3;
9347 int sizeflag, orig_sizeflag;
9348 const char *p;
9349 struct dis_private priv;
9350 int prefix_length;
9351 int op_count;
9352 instr_info ins = {
9353 .info = info,
9354 .intel_syntax = intel_syntax >= 0
9355 ? intel_syntax
9356 : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9357 .intel_mnemonic = !SYSV386_COMPAT,
9358 .op_index[0 ... MAX_OPERANDS - 1] = -1,
9359 .start_pc = pc,
9360 .start_codep = priv.the_buffer,
9361 .codep = priv.the_buffer,
9362 .obufp = ins.obuf,
9363 .last_lock_prefix = -1,
9364 .last_repz_prefix = -1,
9365 .last_repnz_prefix = -1,
9366 .last_data_prefix = -1,
9367 .last_addr_prefix = -1,
9368 .last_rex_prefix = -1,
9369 .last_rex2_prefix = -1,
9370 .last_seg_prefix = -1,
9371 .fwait_prefix = -1,
9372 };
9373 char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9374
9375 priv.orig_sizeflag = AFLAG | DFLAG;
9376 if ((info->mach & bfd_mach_i386_i386) != 0)
9377 ins.address_mode = mode_32bit;
9378 else if (info->mach == bfd_mach_i386_i8086)
9379 {
9380 ins.address_mode = mode_16bit;
9381 priv.orig_sizeflag = 0;
9382 }
9383 else
9384 ins.address_mode = mode_64bit;
9385
9386 for (p = info->disassembler_options; p != NULL;)
9387 {
9388 if (startswith (p, "amd64"))
9389 ins.isa64 = amd64;
9390 else if (startswith (p, "intel64"))
9391 ins.isa64 = intel64;
9392 else if (startswith (p, "x86-64"))
9393 {
9394 ins.address_mode = mode_64bit;
9395 priv.orig_sizeflag |= AFLAG | DFLAG;
9396 }
9397 else if (startswith (p, "i386"))
9398 {
9399 ins.address_mode = mode_32bit;
9400 priv.orig_sizeflag |= AFLAG | DFLAG;
9401 }
9402 else if (startswith (p, "i8086"))
9403 {
9404 ins.address_mode = mode_16bit;
9405 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9406 }
9407 else if (startswith (p, "intel"))
9408 {
9409 if (startswith (p + 5, "-mnemonic"))
9410 ins.intel_mnemonic = true;
9411 else
9412 ins.intel_syntax = 1;
9413 }
9414 else if (startswith (p, "att"))
9415 {
9416 ins.intel_syntax = 0;
9417 if (startswith (p + 3, "-mnemonic"))
9418 ins.intel_mnemonic = false;
9419 }
9420 else if (startswith (p, "addr"))
9421 {
9422 if (ins.address_mode == mode_64bit)
9423 {
9424 if (p[4] == '3' && p[5] == '2')
9425 priv.orig_sizeflag &= ~AFLAG;
9426 else if (p[4] == '6' && p[5] == '4')
9427 priv.orig_sizeflag |= AFLAG;
9428 }
9429 else
9430 {
9431 if (p[4] == '1' && p[5] == '6')
9432 priv.orig_sizeflag &= ~AFLAG;
9433 else if (p[4] == '3' && p[5] == '2')
9434 priv.orig_sizeflag |= AFLAG;
9435 }
9436 }
9437 else if (startswith (p, "data"))
9438 {
9439 if (p[4] == '1' && p[5] == '6')
9440 priv.orig_sizeflag &= ~DFLAG;
9441 else if (p[4] == '3' && p[5] == '2')
9442 priv.orig_sizeflag |= DFLAG;
9443 }
9444 else if (startswith (p, "suffix"))
9445 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9446
9447 p = strchr (p, ',');
9448 if (p != NULL)
9449 p++;
9450 }
9451
9452 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9453 {
9454 i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9455 return -1;
9456 }
9457
9458 if (ins.intel_syntax)
9459 {
9460 ins.open_char = '[';
9461 ins.close_char = ']';
9462 ins.separator_char = '+';
9463 ins.scale_char = '*';
9464 }
9465 else
9466 {
9467 ins.open_char = '(';
9468 ins.close_char = ')';
9469 ins.separator_char = ',';
9470 ins.scale_char = ',';
9471 }
9472
9473 /* The output looks better if we put 7 bytes on a line, since that
9474 puts most long word instructions on a single line. */
9475 info->bytes_per_line = 7;
9476
9477 info->private_data = &priv;
9478 priv.fetched = 0;
9479 priv.insn_start = pc;
9480
9481 for (i = 0; i < MAX_OPERANDS; ++i)
9482 {
9483 op_out[i][0] = 0;
9484 ins.op_out[i] = op_out[i];
9485 }
9486
9487 sizeflag = priv.orig_sizeflag;
9488
9489 switch (ckprefix (&ins))
9490 {
9491 case ckp_okay:
9492 break;
9493
9494 case ckp_bogus:
9495 /* Too many prefixes or unused REX prefixes. */
9496 for (i = 0;
9497 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9498 i++)
9499 i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9500 (i == 0 ? "" : " "),
9501 prefix_name (ins.address_mode, ins.all_prefixes[i],
9502 sizeflag));
9503 ret = i;
9504 goto out;
9505
9506 case ckp_fetch_error:
9507 goto fetch_error_out;
9508 }
9509
9510 ins.nr_prefixes = ins.codep - ins.start_codep;
9511
9512 if (!fetch_code (info, ins.codep + 1))
9513 {
9514 fetch_error_out:
9515 ret = fetch_error (&ins);
9516 goto out;
9517 }
9518
9519 ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9520
9521 if ((ins.prefixes & PREFIX_FWAIT)
9522 && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9523 {
9524 /* Handle ins.prefixes before fwait. */
9525 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9526 i++)
9527 i386_dis_printf (info, dis_style_mnemonic, "%s ",
9528 prefix_name (ins.address_mode, ins.all_prefixes[i],
9529 sizeflag));
9530 i386_dis_printf (info, dis_style_mnemonic, "fwait");
9531 ret = i + 1;
9532 goto out;
9533 }
9534
9535 /* REX2.M in rex2 prefix represents map0 or map1. */
9536 if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9537 {
9538 if (!ins.rex2)
9539 {
9540 ins.codep++;
9541 if (!fetch_code (info, ins.codep + 1))
9542 goto fetch_error_out;
9543 }
9544
9545 dp = &dis386_twobyte[*ins.codep];
9546 ins.need_modrm = twobyte_has_modrm[*ins.codep];
9547 }
9548 else
9549 {
9550 dp = &dis386[*ins.codep];
9551 ins.need_modrm = onebyte_has_modrm[*ins.codep];
9552 }
9553 ins.condition_code = *ins.codep & 0xf;
9554 ins.codep++;
9555
9556 /* Save sizeflag for printing the extra ins.prefixes later before updating
9557 it for mnemonic and operand processing. The prefix names depend
9558 only on the address mode. */
9559 orig_sizeflag = sizeflag;
9560 if (ins.prefixes & PREFIX_ADDR)
9561 sizeflag ^= AFLAG;
9562 if ((ins.prefixes & PREFIX_DATA))
9563 sizeflag ^= DFLAG;
9564
9565 ins.end_codep = ins.codep;
9566 if (ins.need_modrm && !fetch_modrm (&ins))
9567 goto fetch_error_out;
9568
9569 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9570 {
9571 if (!get_sib (&ins, sizeflag)
9572 || !dofloat (&ins, sizeflag))
9573 goto fetch_error_out;
9574 }
9575 else
9576 {
9577 dp = get_valid_dis386 (dp, &ins);
9578 if (dp == &err_opcode)
9579 goto fetch_error_out;
9580
9581 /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9582 is interpreted as the operand size override. */
9583 if (ins.evex_type == evex_from_legacy
9584 && ins.vex.prefix == DATA_PREFIX_OPCODE)
9585 sizeflag ^= DFLAG;
9586
9587 if(ins.evex_type == evex_default)
9588 ins.vex.nf = false;
9589 else
9590 /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest
9591 are cleared separately.) in mask_register_specifier and keep the low
9592 2 bits of mask_register_specifier to report errors for invalid cases
9593 . */
9594 ins.vex.mask_register_specifier &= 0x3;
9595
9596 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9597 {
9598 if (!get_sib (&ins, sizeflag))
9599 goto fetch_error_out;
9600 for (i = 0; i < MAX_OPERANDS; ++i)
9601 {
9602 ins.obufp = ins.op_out[i];
9603 ins.op_ad = MAX_OPERANDS - 1 - i;
9604 if (dp->op[i].rtn
9605 && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9606 goto fetch_error_out;
9607 /* For EVEX instruction after the last operand masking
9608 should be printed. */
9609 if (i == 0 && ins.vex.evex)
9610 {
9611 /* Don't print {%k0}. */
9612 if (ins.vex.mask_register_specifier)
9613 {
9614 const char *reg_name
9615 = att_names_mask[ins.vex.mask_register_specifier];
9616
9617 oappend (&ins, "{");
9618 oappend_register (&ins, reg_name);
9619 oappend (&ins, "}");
9620
9621 if (ins.vex.zeroing)
9622 oappend (&ins, "{z}");
9623 }
9624 else if (ins.vex.zeroing)
9625 {
9626 oappend (&ins, "{bad}");
9627 continue;
9628 }
9629
9630 /* Instructions with a mask register destination allow for
9631 zeroing-masking only (if any masking at all), which is
9632 _not_ expressed by EVEX.z. */
9633 if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9634 ins.illegal_masking = true;
9635
9636 /* S/G insns require a mask and don't allow
9637 zeroing-masking. */
9638 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9639 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9640 && (ins.vex.mask_register_specifier == 0
9641 || ins.vex.zeroing))
9642 ins.illegal_masking = true;
9643
9644 if (ins.illegal_masking)
9645 oappend (&ins, "/(bad)");
9646 }
9647 }
9648 /* vex.nf is cleared after being consumed. */
9649 if (ins.vex.nf)
9650 oappend (&ins, "{bad-nf}");
9651
9652 /* Check whether rounding control was enabled for an insn not
9653 supporting it, when evex.b is not treated as evex.nd. */
9654 if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9655 && !(ins.evex_used & EVEX_b_used))
9656 {
9657 for (i = 0; i < MAX_OPERANDS; ++i)
9658 {
9659 ins.obufp = ins.op_out[i];
9660 if (*ins.obufp)
9661 continue;
9662 oappend (&ins, names_rounding[ins.vex.ll]);
9663 oappend (&ins, "bad}");
9664 break;
9665 }
9666 }
9667 }
9668 }
9669
9670 /* Clear instruction information. */
9671 info->insn_info_valid = 0;
9672 info->branch_delay_insns = 0;
9673 info->data_size = 0;
9674 info->insn_type = dis_noninsn;
9675 info->target = 0;
9676 info->target2 = 0;
9677
9678 /* Reset jump operation indicator. */
9679 ins.op_is_jump = false;
9680 {
9681 int jump_detection = 0;
9682
9683 /* Extract flags. */
9684 for (i = 0; i < MAX_OPERANDS; ++i)
9685 {
9686 if ((dp->op[i].rtn == OP_J)
9687 || (dp->op[i].rtn == OP_indirE))
9688 jump_detection |= 1;
9689 else if ((dp->op[i].rtn == BND_Fixup)
9690 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9691 jump_detection |= 2;
9692 else if ((dp->op[i].bytemode == cond_jump_mode)
9693 || (dp->op[i].bytemode == loop_jcxz_mode))
9694 jump_detection |= 4;
9695 }
9696
9697 /* Determine if this is a jump or branch. */
9698 if ((jump_detection & 0x3) == 0x3)
9699 {
9700 ins.op_is_jump = true;
9701 if (jump_detection & 0x4)
9702 info->insn_type = dis_condbranch;
9703 else
9704 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9705 ? dis_jsr : dis_branch;
9706 }
9707 }
9708 /* The purpose of placing the check here is to wait for the EVEX prefix for
9709 conditional CMP and TEST to be consumed and cleared, and then make a
9710 unified judgment. Because they are both in map4, we can not distinguish
9711 EVEX prefix for conditional CMP and TEST from others during the
9712 EVEX prefix stage of parsing. */
9713 if (ins.evex_type == evex_from_legacy)
9714 {
9715 /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
9716 all bits of EVEX.vvvv and EVEX.V' must be 1. */
9717 if (!ins.vex.nd && (ins.vex.register_specifier || !ins.vex.v))
9718 {
9719 i386_dis_printf (info, dis_style_text, "(bad)");
9720 ret = ins.end_codep - priv.the_buffer;
9721 goto out;
9722 }
9723
9724 /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
9725 lower 2 bits of EVEX.aaa must be 0. */
9726 if ((ins.vex.mask_register_specifier & 0x3) != 0
9727 || ins.vex.ll != 0 || ins.vex.zeroing != 0)
9728 {
9729 i386_dis_printf (info, dis_style_text, "(bad)");
9730 ret = ins.end_codep - priv.the_buffer;
9731 goto out;
9732 }
9733 }
9734 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9735 are all 0s in inverted form. */
9736 if (ins.need_vex && ins.vex.register_specifier != 0)
9737 {
9738 i386_dis_printf (info, dis_style_text, "(bad)");
9739 ret = ins.end_codep - priv.the_buffer;
9740 goto out;
9741 }
9742
9743 if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
9744 && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
9745 {
9746 i386_dis_printf (info, dis_style_text, "(bad)");
9747 ret = ins.end_codep - priv.the_buffer;
9748 goto out;
9749 }
9750
9751 switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
9752 {
9753 case PREFIX_DATA:
9754 /* If only the data prefix is marked as mandatory, its absence renders
9755 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9756 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9757 {
9758 i386_dis_printf (info, dis_style_text, "(bad)");
9759 ret = ins.end_codep - priv.the_buffer;
9760 goto out;
9761 }
9762 ins.used_prefixes |= PREFIX_DATA;
9763 /* Fall through. */
9764 case PREFIX_OPCODE:
9765 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9766 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9767 used by putop and MMX/SSE operand and may be overridden by the
9768 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9769 separately. */
9770 if (((ins.need_vex
9771 ? ins.vex.prefix == REPE_PREFIX_OPCODE
9772 || ins.vex.prefix == REPNE_PREFIX_OPCODE
9773 : (ins.prefixes
9774 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9775 && (ins.used_prefixes
9776 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9777 || (((ins.need_vex
9778 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9779 : ((ins.prefixes
9780 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9781 == PREFIX_DATA))
9782 && (ins.used_prefixes & PREFIX_DATA) == 0))
9783 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9784 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9785 {
9786 i386_dis_printf (info, dis_style_text, "(bad)");
9787 ret = ins.end_codep - priv.the_buffer;
9788 goto out;
9789 }
9790 break;
9791
9792 case PREFIX_IGNORED:
9793 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9794 origins in all_prefixes. */
9795 ins.used_prefixes &= ~PREFIX_OPCODE;
9796 if (ins.last_data_prefix >= 0)
9797 ins.all_prefixes[ins.last_data_prefix] = 0x66;
9798 if (ins.last_repz_prefix >= 0)
9799 ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9800 if (ins.last_repnz_prefix >= 0)
9801 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9802 break;
9803
9804 case PREFIX_NP_OR_DATA:
9805 if (ins.vex.prefix == REPE_PREFIX_OPCODE
9806 || ins.vex.prefix == REPNE_PREFIX_OPCODE)
9807 {
9808 i386_dis_printf (info, dis_style_text, "(bad)");
9809 ret = ins.end_codep - priv.the_buffer;
9810 goto out;
9811 }
9812 break;
9813
9814 case NO_PREFIX:
9815 if (ins.vex.prefix)
9816 {
9817 i386_dis_printf (info, dis_style_text, "(bad)");
9818 ret = ins.end_codep - priv.the_buffer;
9819 goto out;
9820 }
9821 break;
9822 }
9823
9824 /* Check if the REX prefix is used. */
9825 if ((ins.rex ^ ins.rex_used) == 0
9826 && !ins.need_vex && ins.last_rex_prefix >= 0)
9827 ins.all_prefixes[ins.last_rex_prefix] = 0;
9828
9829 /* Check if the REX2 prefix is used. */
9830 if (ins.last_rex2_prefix >= 0
9831 && ((ins.rex2 & REX2_SPECIAL)
9832 || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
9833 && (ins.rex ^ ins.rex_used) == 0
9834 && (ins.rex2 & 7))))
9835 ins.all_prefixes[ins.last_rex2_prefix] = 0;
9836
9837 /* Check if the SEG prefix is used. */
9838 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9839 | PREFIX_FS | PREFIX_GS)) != 0
9840 && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9841 ins.all_prefixes[ins.last_seg_prefix] = 0;
9842
9843 /* Check if the ADDR prefix is used. */
9844 if ((ins.prefixes & PREFIX_ADDR) != 0
9845 && (ins.used_prefixes & PREFIX_ADDR) != 0)
9846 ins.all_prefixes[ins.last_addr_prefix] = 0;
9847
9848 /* Check if the DATA prefix is used. */
9849 if ((ins.prefixes & PREFIX_DATA) != 0
9850 && (ins.used_prefixes & PREFIX_DATA) != 0
9851 && !ins.need_vex)
9852 ins.all_prefixes[ins.last_data_prefix] = 0;
9853
9854 /* Print the extra ins.prefixes. */
9855 prefix_length = 0;
9856 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9857 if (ins.all_prefixes[i])
9858 {
9859 const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
9860 orig_sizeflag);
9861
9862 if (name == NULL)
9863 abort ();
9864 prefix_length += strlen (name) + 1;
9865 if (ins.all_prefixes[i] == REX2_OPCODE)
9866 i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
9867 (unsigned int) ins.rex2_payload);
9868 else
9869 i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
9870 }
9871
9872 /* Check maximum code length. */
9873 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9874 {
9875 i386_dis_printf (info, dis_style_text, "(bad)");
9876 ret = MAX_CODE_LENGTH;
9877 goto out;
9878 }
9879
9880 /* Calculate the number of operands this instruction has. */
9881 op_count = 0;
9882 for (i = 0; i < MAX_OPERANDS; ++i)
9883 if (*ins.op_out[i] != '\0')
9884 ++op_count;
9885
9886 /* Calculate the number of spaces to print after the mnemonic. */
9887 ins.obufp = ins.mnemonicendp;
9888 if (op_count > 0)
9889 {
9890 i = strlen (ins.obuf) + prefix_length;
9891 if (i < 7)
9892 i = 7 - i;
9893 else
9894 i = 1;
9895 }
9896 else
9897 i = 0;
9898
9899 /* Print the instruction mnemonic along with any trailing whitespace. */
9900 i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9901
9902 /* The enter and bound instructions are printed with operands in the same
9903 order as the intel book; everything else is printed in reverse order. */
9904 intel_swap_2_3 = false;
9905 if (ins.intel_syntax || ins.two_source_ops)
9906 {
9907 for (i = 0; i < MAX_OPERANDS; ++i)
9908 op_txt[i] = ins.op_out[i];
9909
9910 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9911 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9912 {
9913 op_txt[2] = ins.op_out[3];
9914 op_txt[3] = ins.op_out[2];
9915 intel_swap_2_3 = true;
9916 }
9917
9918 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9919 {
9920 bool riprel;
9921
9922 ins.op_ad = ins.op_index[i];
9923 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9924 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9925 riprel = ins.op_riprel[i];
9926 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9927 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9928 }
9929 }
9930 else
9931 {
9932 for (i = 0; i < MAX_OPERANDS; ++i)
9933 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9934 }
9935
9936 needcomma = 0;
9937 for (i = 0; i < MAX_OPERANDS; ++i)
9938 if (*op_txt[i])
9939 {
9940 /* In Intel syntax embedded rounding / SAE are not separate operands.
9941 Instead they're attached to the prior register operand. Simply
9942 suppress emission of the comma to achieve that effect. */
9943 switch (i & -(ins.intel_syntax && dp))
9944 {
9945 case 2:
9946 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9947 needcomma = 0;
9948 break;
9949 case 3:
9950 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9951 needcomma = 0;
9952 break;
9953 }
9954 if (needcomma)
9955 i386_dis_printf (info, dis_style_text, ",");
9956 if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9957 {
9958 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9959
9960 if (ins.op_is_jump)
9961 {
9962 info->insn_info_valid = 1;
9963 info->branch_delay_insns = 0;
9964 info->data_size = 0;
9965 info->target = target;
9966 info->target2 = 0;
9967 }
9968 (*info->print_address_func) (target, info);
9969 }
9970 else
9971 i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
9972 needcomma = 1;
9973 }
9974
9975 for (i = 0; i < MAX_OPERANDS; i++)
9976 if (ins.op_index[i] != -1 && ins.op_riprel[i])
9977 {
9978 i386_dis_printf (info, dis_style_comment_start, " # ");
9979 (*info->print_address_func)
9980 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9981 + ins.op_address[ins.op_index[i]]),
9982 info);
9983 break;
9984 }
9985 ret = ins.codep - priv.the_buffer;
9986 out:
9987 info->private_data = NULL;
9988 return ret;
9989 }
9990
9991 /* Here for backwards compatibility. When gdb stops using
9992 print_insn_i386_att and print_insn_i386_intel these functions can
9993 disappear, and print_insn_i386 be merged into print_insn. */
9994 int
9995 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9996 {
9997 return print_insn (pc, info, 0);
9998 }
9999
10000 int
10001 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10002 {
10003 return print_insn (pc, info, 1);
10004 }
10005
10006 int
10007 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10008 {
10009 return print_insn (pc, info, -1);
10010 }
10011
10012 static const char *float_mem[] = {
10013 /* d8 */
10014 "fadd{s|}",
10015 "fmul{s|}",
10016 "fcom{s|}",
10017 "fcomp{s|}",
10018 "fsub{s|}",
10019 "fsubr{s|}",
10020 "fdiv{s|}",
10021 "fdivr{s|}",
10022 /* d9 */
10023 "fld{s|}",
10024 "(bad)",
10025 "fst{s|}",
10026 "fstp{s|}",
10027 "fldenv{C|C}",
10028 "fldcw",
10029 "fNstenv{C|C}",
10030 "fNstcw",
10031 /* da */
10032 "fiadd{l|}",
10033 "fimul{l|}",
10034 "ficom{l|}",
10035 "ficomp{l|}",
10036 "fisub{l|}",
10037 "fisubr{l|}",
10038 "fidiv{l|}",
10039 "fidivr{l|}",
10040 /* db */
10041 "fild{l|}",
10042 "fisttp{l|}",
10043 "fist{l|}",
10044 "fistp{l|}",
10045 "(bad)",
10046 "fld{t|}",
10047 "(bad)",
10048 "fstp{t|}",
10049 /* dc */
10050 "fadd{l|}",
10051 "fmul{l|}",
10052 "fcom{l|}",
10053 "fcomp{l|}",
10054 "fsub{l|}",
10055 "fsubr{l|}",
10056 "fdiv{l|}",
10057 "fdivr{l|}",
10058 /* dd */
10059 "fld{l|}",
10060 "fisttp{ll|}",
10061 "fst{l||}",
10062 "fstp{l|}",
10063 "frstor{C|C}",
10064 "(bad)",
10065 "fNsave{C|C}",
10066 "fNstsw",
10067 /* de */
10068 "fiadd{s|}",
10069 "fimul{s|}",
10070 "ficom{s|}",
10071 "ficomp{s|}",
10072 "fisub{s|}",
10073 "fisubr{s|}",
10074 "fidiv{s|}",
10075 "fidivr{s|}",
10076 /* df */
10077 "fild{s|}",
10078 "fisttp{s|}",
10079 "fist{s|}",
10080 "fistp{s|}",
10081 "fbld",
10082 "fild{ll|}",
10083 "fbstp",
10084 "fistp{ll|}",
10085 };
10086
10087 static const unsigned char float_mem_mode[] = {
10088 /* d8 */
10089 d_mode,
10090 d_mode,
10091 d_mode,
10092 d_mode,
10093 d_mode,
10094 d_mode,
10095 d_mode,
10096 d_mode,
10097 /* d9 */
10098 d_mode,
10099 0,
10100 d_mode,
10101 d_mode,
10102 0,
10103 w_mode,
10104 0,
10105 w_mode,
10106 /* da */
10107 d_mode,
10108 d_mode,
10109 d_mode,
10110 d_mode,
10111 d_mode,
10112 d_mode,
10113 d_mode,
10114 d_mode,
10115 /* db */
10116 d_mode,
10117 d_mode,
10118 d_mode,
10119 d_mode,
10120 0,
10121 t_mode,
10122 0,
10123 t_mode,
10124 /* dc */
10125 q_mode,
10126 q_mode,
10127 q_mode,
10128 q_mode,
10129 q_mode,
10130 q_mode,
10131 q_mode,
10132 q_mode,
10133 /* dd */
10134 q_mode,
10135 q_mode,
10136 q_mode,
10137 q_mode,
10138 0,
10139 0,
10140 0,
10141 w_mode,
10142 /* de */
10143 w_mode,
10144 w_mode,
10145 w_mode,
10146 w_mode,
10147 w_mode,
10148 w_mode,
10149 w_mode,
10150 w_mode,
10151 /* df */
10152 w_mode,
10153 w_mode,
10154 w_mode,
10155 w_mode,
10156 t_mode,
10157 q_mode,
10158 t_mode,
10159 q_mode
10160 };
10161
10162 #define ST { OP_ST, 0 }
10163 #define STi { OP_STi, 0 }
10164
10165 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10166 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10167 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10168 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10169 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10170 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10171 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10172 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10173 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10174
10175 static const struct dis386 float_reg[][8] = {
10176 /* d8 */
10177 {
10178 { "fadd", { ST, STi }, 0 },
10179 { "fmul", { ST, STi }, 0 },
10180 { "fcom", { STi }, 0 },
10181 { "fcomp", { STi }, 0 },
10182 { "fsub", { ST, STi }, 0 },
10183 { "fsubr", { ST, STi }, 0 },
10184 { "fdiv", { ST, STi }, 0 },
10185 { "fdivr", { ST, STi }, 0 },
10186 },
10187 /* d9 */
10188 {
10189 { "fld", { STi }, 0 },
10190 { "fxch", { STi }, 0 },
10191 { FGRPd9_2 },
10192 { Bad_Opcode },
10193 { FGRPd9_4 },
10194 { FGRPd9_5 },
10195 { FGRPd9_6 },
10196 { FGRPd9_7 },
10197 },
10198 /* da */
10199 {
10200 { "fcmovb", { ST, STi }, 0 },
10201 { "fcmove", { ST, STi }, 0 },
10202 { "fcmovbe",{ ST, STi }, 0 },
10203 { "fcmovu", { ST, STi }, 0 },
10204 { Bad_Opcode },
10205 { FGRPda_5 },
10206 { Bad_Opcode },
10207 { Bad_Opcode },
10208 },
10209 /* db */
10210 {
10211 { "fcmovnb",{ ST, STi }, 0 },
10212 { "fcmovne",{ ST, STi }, 0 },
10213 { "fcmovnbe",{ ST, STi }, 0 },
10214 { "fcmovnu",{ ST, STi }, 0 },
10215 { FGRPdb_4 },
10216 { "fucomi", { ST, STi }, 0 },
10217 { "fcomi", { ST, STi }, 0 },
10218 { Bad_Opcode },
10219 },
10220 /* dc */
10221 {
10222 { "fadd", { STi, ST }, 0 },
10223 { "fmul", { STi, ST }, 0 },
10224 { Bad_Opcode },
10225 { Bad_Opcode },
10226 { "fsub{!M|r}", { STi, ST }, 0 },
10227 { "fsub{M|}", { STi, ST }, 0 },
10228 { "fdiv{!M|r}", { STi, ST }, 0 },
10229 { "fdiv{M|}", { STi, ST }, 0 },
10230 },
10231 /* dd */
10232 {
10233 { "ffree", { STi }, 0 },
10234 { Bad_Opcode },
10235 { "fst", { STi }, 0 },
10236 { "fstp", { STi }, 0 },
10237 { "fucom", { STi }, 0 },
10238 { "fucomp", { STi }, 0 },
10239 { Bad_Opcode },
10240 { Bad_Opcode },
10241 },
10242 /* de */
10243 {
10244 { "faddp", { STi, ST }, 0 },
10245 { "fmulp", { STi, ST }, 0 },
10246 { Bad_Opcode },
10247 { FGRPde_3 },
10248 { "fsub{!M|r}p", { STi, ST }, 0 },
10249 { "fsub{M|}p", { STi, ST }, 0 },
10250 { "fdiv{!M|r}p", { STi, ST }, 0 },
10251 { "fdiv{M|}p", { STi, ST }, 0 },
10252 },
10253 /* df */
10254 {
10255 { "ffreep", { STi }, 0 },
10256 { Bad_Opcode },
10257 { Bad_Opcode },
10258 { Bad_Opcode },
10259 { FGRPdf_4 },
10260 { "fucomip", { ST, STi }, 0 },
10261 { "fcomip", { ST, STi }, 0 },
10262 { Bad_Opcode },
10263 },
10264 };
10265
10266 static const char *const fgrps[][8] = {
10267 /* Bad opcode 0 */
10268 {
10269 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10270 },
10271
10272 /* d9_2 1 */
10273 {
10274 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10275 },
10276
10277 /* d9_4 2 */
10278 {
10279 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10280 },
10281
10282 /* d9_5 3 */
10283 {
10284 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10285 },
10286
10287 /* d9_6 4 */
10288 {
10289 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10290 },
10291
10292 /* d9_7 5 */
10293 {
10294 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10295 },
10296
10297 /* da_5 6 */
10298 {
10299 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10300 },
10301
10302 /* db_4 7 */
10303 {
10304 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10305 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10306 },
10307
10308 /* de_3 8 */
10309 {
10310 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10311 },
10312
10313 /* df_4 9 */
10314 {
10315 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10316 },
10317 };
10318
10319 static const char *const oszc_flags[16] = {
10320 " {dfv=}", " {dfv=cf}", " {dfv=zf}", " {dfv=zf, cf}", " {dfv=sf}",
10321 " {dfv=sf, cf}", " {dfv=sf, zf}", " {dfv=sf, zf, cf}", " {dfv=of}",
10322 " {dfv=of, cf}", " {dfv=of, zf}", " {dfv=of, zf, cf}", " {dfv=of, sf}",
10323 " {dfv=of, sf, cf}", " {dfv=of, sf, zf}", " {dfv=of, sf, zf, cf}"
10324 };
10325
10326 static const char *const scc_suffix[16] = {
10327 "o", "no", "b", "ae", "e", "ne", "be", "a", "s", "ns", "t", "f",
10328 "l", "ge", "le", "g"
10329 };
10330
10331 static void
10332 swap_operand (instr_info *ins)
10333 {
10334 char *p = ins->mnemonicendp;
10335
10336 if (p[-1] == '}')
10337 {
10338 while (*--p != '{')
10339 {
10340 if (p <= ins->obuf + 2)
10341 abort ();
10342 }
10343 if (p[-1] == ' ')
10344 --p;
10345 }
10346 memmove (p + 2, p, ins->mnemonicendp - p + 1);
10347 p[0] = '.';
10348 p[1] = 's';
10349 ins->mnemonicendp += 2;
10350 }
10351
10352 static bool
10353 dofloat (instr_info *ins, int sizeflag)
10354 {
10355 const struct dis386 *dp;
10356 unsigned char floatop = ins->codep[-1];
10357
10358 if (ins->modrm.mod != 3)
10359 {
10360 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10361
10362 putop (ins, float_mem[fp_indx], sizeflag);
10363 ins->obufp = ins->op_out[0];
10364 ins->op_ad = 2;
10365 return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10366 }
10367 /* Skip mod/rm byte. */
10368 MODRM_CHECK;
10369 ins->codep++;
10370
10371 dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10372 if (dp->name == NULL)
10373 {
10374 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10375
10376 /* Instruction fnstsw is only one with strange arg. */
10377 if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10378 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10379 }
10380 else
10381 {
10382 putop (ins, dp->name, sizeflag);
10383
10384 ins->obufp = ins->op_out[0];
10385 ins->op_ad = 2;
10386 if (dp->op[0].rtn
10387 && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10388 return false;
10389
10390 ins->obufp = ins->op_out[1];
10391 ins->op_ad = 1;
10392 if (dp->op[1].rtn
10393 && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10394 return false;
10395 }
10396 return true;
10397 }
10398
10399 static bool
10400 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10401 int sizeflag ATTRIBUTE_UNUSED)
10402 {
10403 oappend_register (ins, "%st");
10404 return true;
10405 }
10406
10407 static bool
10408 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10409 int sizeflag ATTRIBUTE_UNUSED)
10410 {
10411 char scratch[8];
10412 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10413
10414 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10415 abort ();
10416 oappend_register (ins, scratch);
10417 return true;
10418 }
10419
10420 /* Capital letters in template are macros. */
10421 static int
10422 putop (instr_info *ins, const char *in_template, int sizeflag)
10423 {
10424 const char *p;
10425 int alt = 0;
10426 int cond = 1;
10427 unsigned int l = 0, len = 0;
10428 char last[4];
10429 bool evex_printed = false;
10430
10431 /* We don't want to add any prefix or suffix to (bad), so return early. */
10432 if (!strncmp (in_template, "(bad)", 5))
10433 {
10434 oappend (ins, "(bad)");
10435 *ins->obufp = 0;
10436 ins->mnemonicendp = ins->obufp;
10437 return 0;
10438 }
10439
10440 for (p = in_template; *p; p++)
10441 {
10442 if (len > l)
10443 {
10444 if (l >= sizeof (last) || !ISUPPER (*p))
10445 abort ();
10446 last[l++] = *p;
10447 continue;
10448 }
10449 switch (*p)
10450 {
10451 default:
10452 if (ins->evex_type == evex_from_legacy && !ins->vex.nd
10453 && !(ins->rex2 & 7) && !evex_printed)
10454 {
10455 oappend (ins, "{evex} ");
10456 evex_printed = true;
10457 }
10458 *ins->obufp++ = *p;
10459 break;
10460 case '%':
10461 len++;
10462 break;
10463 case '!':
10464 cond = 0;
10465 break;
10466 case '{':
10467 if (ins->intel_syntax)
10468 {
10469 while (*++p != '|')
10470 if (*p == '}' || *p == '\0')
10471 abort ();
10472 alt = 1;
10473 }
10474 break;
10475 case '|':
10476 while (*++p != '}')
10477 {
10478 if (*p == '\0')
10479 abort ();
10480 }
10481 break;
10482 case '}':
10483 alt = 0;
10484 break;
10485 case 'A':
10486 if (ins->intel_syntax)
10487 break;
10488 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10489 || (sizeflag & SUFFIX_ALWAYS))
10490 *ins->obufp++ = 'b';
10491 break;
10492 case 'B':
10493 if (l == 0)
10494 {
10495 case_B:
10496 if (ins->intel_syntax)
10497 break;
10498 if (sizeflag & SUFFIX_ALWAYS)
10499 *ins->obufp++ = 'b';
10500 }
10501 else if (l == 1 && last[0] == 'L')
10502 {
10503 if (ins->address_mode == mode_64bit
10504 && !(ins->prefixes & PREFIX_ADDR))
10505 {
10506 *ins->obufp++ = 'a';
10507 *ins->obufp++ = 'b';
10508 *ins->obufp++ = 's';
10509 }
10510
10511 goto case_B;
10512 }
10513 else
10514 abort ();
10515 break;
10516 case 'C':
10517 if (l == 1 && last[0] == 'C')
10518 {
10519 /* Condition code (taken from the map-0 Jcc entries). */
10520 for (const char *q = dis386[0x70 | ins->condition_code].name + 1;
10521 ISLOWER(*q); ++q)
10522 *ins->obufp++ = *q;
10523 break;
10524 }
10525 else if (l == 1 && last[0] == 'S')
10526 {
10527 /* Add scc suffix. */
10528 oappend (ins, scc_suffix[ins->vex.scc]);
10529
10530 /* For SCC insns, the ND bit is required to be set to 0. */
10531 if (ins->vex.nd)
10532 oappend (ins, "(bad)");
10533
10534 /* These bits have been consumed and should be cleared or restored
10535 to default values. */
10536 ins->vex.v = 1;
10537 ins->vex.nf = false;
10538 ins->vex.mask_register_specifier = 0;
10539 break;
10540 }
10541
10542 if (l)
10543 abort ();
10544 if (ins->intel_syntax && !alt)
10545 break;
10546 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10547 {
10548 if (sizeflag & DFLAG)
10549 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10550 else
10551 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10552 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10553 }
10554 break;
10555 case 'D':
10556 if (l == 1)
10557 {
10558 switch (last[0])
10559 {
10560 case 'X':
10561 if (!ins->vex.evex || ins->vex.w)
10562 *ins->obufp++ = 'd';
10563 else
10564 oappend (ins, "{bad}");
10565 break;
10566 default:
10567 abort ();
10568 }
10569 break;
10570 }
10571 if (l)
10572 abort ();
10573 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10574 break;
10575 USED_REX (REX_W);
10576 if (ins->modrm.mod == 3)
10577 {
10578 if (ins->rex & REX_W)
10579 *ins->obufp++ = 'q';
10580 else
10581 {
10582 if (sizeflag & DFLAG)
10583 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10584 else
10585 *ins->obufp++ = 'w';
10586 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10587 }
10588 }
10589 else
10590 *ins->obufp++ = 'w';
10591 break;
10592 case 'E':
10593 if (l == 1)
10594 {
10595 switch (last[0])
10596 {
10597 case 'X':
10598 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10599 || (ins->rex2 & 7)
10600 || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10601 || !ins->vex.v || ins->vex.mask_register_specifier)
10602 break;
10603 /* AVX512 extends a number of V*D insns to also have V*Q variants,
10604 merely distinguished by EVEX.W. Look for a use of the
10605 respective macro. */
10606 if (ins->vex.w)
10607 {
10608 const char *pct = strchr (p + 1, '%');
10609
10610 if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10611 break;
10612 }
10613 *ins->obufp++ = '{';
10614 *ins->obufp++ = 'e';
10615 *ins->obufp++ = 'v';
10616 *ins->obufp++ = 'e';
10617 *ins->obufp++ = 'x';
10618 *ins->obufp++ = '}';
10619 *ins->obufp++ = ' ';
10620 break;
10621 case 'N':
10622 /* Skip printing {evex} for some special instructions in MAP4. */
10623 evex_printed = true;
10624 break;
10625 default:
10626 abort ();
10627 }
10628 break;
10629 }
10630 /* For jcxz/jecxz */
10631 if (ins->address_mode == mode_64bit)
10632 {
10633 if (sizeflag & AFLAG)
10634 *ins->obufp++ = 'r';
10635 else
10636 *ins->obufp++ = 'e';
10637 }
10638 else
10639 if (sizeflag & AFLAG)
10640 *ins->obufp++ = 'e';
10641 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10642 break;
10643 case 'F':
10644 if (l == 0)
10645 {
10646 if (ins->intel_syntax)
10647 break;
10648 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10649 {
10650 if (sizeflag & AFLAG)
10651 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10652 else
10653 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10654 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10655 }
10656 }
10657 else if (l == 1 && last[0] == 'C')
10658 {
10659 if (ins->vex.nd && !ins->vex.nf)
10660 break;
10661 *ins->obufp++ = 'c';
10662 *ins->obufp++ = 'f';
10663 /* Skip printing {evex} */
10664 evex_printed = true;
10665 }
10666 else if (l == 1 && last[0] == 'N')
10667 {
10668 if (ins->vex.nf)
10669 {
10670 oappend (ins, "{nf} ");
10671 /* This bit needs to be cleared after it is consumed. */
10672 ins->vex.nf = false;
10673 evex_printed = true;
10674 }
10675 else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7)
10676 && ins->vex.v)
10677 {
10678 oappend (ins, "{evex} ");
10679 evex_printed = true;
10680 }
10681 }
10682 else if (l == 1 && last[0] == 'D')
10683 {
10684 /* Get oszc flags value from register_specifier. */
10685 int oszc_value = ~ins->vex.register_specifier & 0xf;
10686
10687 /* Add {dfv=of, sf, zf, cf} flags. */
10688 oappend (ins, oszc_flags[oszc_value]);
10689
10690 /* These bits have been consumed and should be cleared. */
10691 ins->vex.register_specifier = 0;
10692 }
10693 else
10694 abort ();
10695 break;
10696 case 'G':
10697 if (ins->intel_syntax || (ins->obufp[-1] != 's'
10698 && !(sizeflag & SUFFIX_ALWAYS)))
10699 break;
10700 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10701 *ins->obufp++ = 'l';
10702 else
10703 *ins->obufp++ = 'w';
10704 if (!(ins->rex & REX_W))
10705 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10706 break;
10707 case 'H':
10708 if (l == 0)
10709 {
10710 if (ins->intel_syntax)
10711 break;
10712 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10713 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10714 {
10715 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10716 *ins->obufp++ = ',';
10717 *ins->obufp++ = 'p';
10718
10719 /* Set active_seg_prefix even if not set in 64-bit mode
10720 because here it is a valid branch hint. */
10721 if (ins->prefixes & PREFIX_DS)
10722 {
10723 ins->active_seg_prefix = PREFIX_DS;
10724 *ins->obufp++ = 't';
10725 }
10726 else
10727 {
10728 ins->active_seg_prefix = PREFIX_CS;
10729 *ins->obufp++ = 'n';
10730 }
10731 }
10732 }
10733 else if (l == 1 && last[0] == 'X')
10734 {
10735 if (!ins->vex.w)
10736 *ins->obufp++ = 'h';
10737 else
10738 oappend (ins, "{bad}");
10739 }
10740 else
10741 abort ();
10742 break;
10743 case 'K':
10744 USED_REX (REX_W);
10745 if (ins->rex & REX_W)
10746 *ins->obufp++ = 'q';
10747 else
10748 *ins->obufp++ = 'd';
10749 break;
10750 case 'L':
10751 if (ins->intel_syntax)
10752 break;
10753 if (sizeflag & SUFFIX_ALWAYS)
10754 {
10755 if (ins->rex & REX_W)
10756 *ins->obufp++ = 'q';
10757 else
10758 *ins->obufp++ = 'l';
10759 }
10760 break;
10761 case 'M':
10762 if (ins->intel_mnemonic != cond)
10763 *ins->obufp++ = 'r';
10764 break;
10765 case 'N':
10766 if ((ins->prefixes & PREFIX_FWAIT) == 0)
10767 *ins->obufp++ = 'n';
10768 else
10769 ins->used_prefixes |= PREFIX_FWAIT;
10770 break;
10771 case 'O':
10772 USED_REX (REX_W);
10773 if (ins->rex & REX_W)
10774 *ins->obufp++ = 'o';
10775 else if (ins->intel_syntax && (sizeflag & DFLAG))
10776 *ins->obufp++ = 'q';
10777 else
10778 *ins->obufp++ = 'd';
10779 if (!(ins->rex & REX_W))
10780 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10781 break;
10782 case '@':
10783 if (ins->address_mode == mode_64bit
10784 && (ins->isa64 == intel64 || (ins->rex & REX_W)
10785 || !(ins->prefixes & PREFIX_DATA)))
10786 {
10787 if (sizeflag & SUFFIX_ALWAYS)
10788 *ins->obufp++ = 'q';
10789 break;
10790 }
10791 /* Fall through. */
10792 case 'P':
10793 if (l == 0)
10794 {
10795 if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
10796 {
10797 /* For pushp and popp, p is printed and do not print {rex2}
10798 for them. */
10799 *ins->obufp++ = 'p';
10800 ins->rex2 |= REX2_SPECIAL;
10801 break;
10802 }
10803
10804 /* For "!P" print nothing else in Intel syntax. */
10805 if (!cond && ins->intel_syntax)
10806 break;
10807
10808 if ((ins->modrm.mod == 3 || !cond)
10809 && !(sizeflag & SUFFIX_ALWAYS))
10810 break;
10811 /* Fall through. */
10812 case 'T':
10813 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10814 || ((sizeflag & SUFFIX_ALWAYS)
10815 && ins->address_mode != mode_64bit))
10816 {
10817 *ins->obufp++ = (sizeflag & DFLAG)
10818 ? ins->intel_syntax ? 'd' : 'l' : 'w';
10819 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10820 }
10821 else if (sizeflag & SUFFIX_ALWAYS)
10822 *ins->obufp++ = 'q';
10823 }
10824 else if (l == 1 && last[0] == 'L')
10825 {
10826 if ((ins->prefixes & PREFIX_DATA)
10827 || (ins->rex & REX_W)
10828 || (sizeflag & SUFFIX_ALWAYS))
10829 {
10830 USED_REX (REX_W);
10831 if (ins->rex & REX_W)
10832 *ins->obufp++ = 'q';
10833 else
10834 {
10835 if (sizeflag & DFLAG)
10836 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10837 else
10838 *ins->obufp++ = 'w';
10839 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10840 }
10841 }
10842 }
10843 else
10844 abort ();
10845 break;
10846 case 'Q':
10847 if (l == 0)
10848 {
10849 if (ins->intel_syntax && !alt)
10850 break;
10851 USED_REX (REX_W);
10852 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10853 || (sizeflag & SUFFIX_ALWAYS))
10854 {
10855 if (ins->rex & REX_W)
10856 *ins->obufp++ = 'q';
10857 else
10858 {
10859 if (sizeflag & DFLAG)
10860 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10861 else
10862 *ins->obufp++ = 'w';
10863 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10864 }
10865 }
10866 }
10867 else if (l == 1 && last[0] == 'D')
10868 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10869 else if (l == 1 && last[0] == 'L')
10870 {
10871 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10872 : ins->address_mode != mode_64bit)
10873 break;
10874 if ((ins->rex & REX_W))
10875 {
10876 USED_REX (REX_W);
10877 *ins->obufp++ = 'q';
10878 }
10879 else if ((ins->address_mode == mode_64bit && cond)
10880 || (sizeflag & SUFFIX_ALWAYS))
10881 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10882 }
10883 else
10884 abort ();
10885 break;
10886 case 'R':
10887 USED_REX (REX_W);
10888 if (ins->rex & REX_W)
10889 *ins->obufp++ = 'q';
10890 else if (sizeflag & DFLAG)
10891 {
10892 if (ins->intel_syntax)
10893 *ins->obufp++ = 'd';
10894 else
10895 *ins->obufp++ = 'l';
10896 }
10897 else
10898 *ins->obufp++ = 'w';
10899 if (ins->intel_syntax && !p[1]
10900 && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10901 *ins->obufp++ = 'e';
10902 if (!(ins->rex & REX_W))
10903 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10904 break;
10905 case 'S':
10906 if (l == 0)
10907 {
10908 case_S:
10909 if (ins->intel_syntax)
10910 break;
10911 if (sizeflag & SUFFIX_ALWAYS)
10912 {
10913 if (ins->rex & REX_W)
10914 *ins->obufp++ = 'q';
10915 else
10916 {
10917 if (sizeflag & DFLAG)
10918 *ins->obufp++ = 'l';
10919 else
10920 *ins->obufp++ = 'w';
10921 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10922 }
10923 }
10924 break;
10925 }
10926 if (l != 1)
10927 abort ();
10928 switch (last[0])
10929 {
10930 case 'L':
10931 if (ins->address_mode == mode_64bit
10932 && !(ins->prefixes & PREFIX_ADDR))
10933 {
10934 *ins->obufp++ = 'a';
10935 *ins->obufp++ = 'b';
10936 *ins->obufp++ = 's';
10937 }
10938
10939 goto case_S;
10940 case 'X':
10941 if (!ins->vex.evex || !ins->vex.w)
10942 *ins->obufp++ = 's';
10943 else
10944 oappend (ins, "{bad}");
10945 break;
10946 default:
10947 abort ();
10948 }
10949 break;
10950 case 'U':
10951 if (l == 1 && (last[0] == 'Z'))
10952 {
10953 /* Although IMUL/SETcc does not support NDD, the EVEX.ND bit is
10954 used to control whether its destination register has its upper
10955 bits zeroed. */
10956 if (ins->vex.nd)
10957 oappend (ins, "zu");
10958 }
10959 else
10960 abort ();
10961 break;
10962 case 'V':
10963 if (l == 0)
10964 {
10965 if (ins->need_vex)
10966 *ins->obufp++ = 'v';
10967 }
10968 else if (l == 1)
10969 {
10970 switch (last[0])
10971 {
10972 case 'X':
10973 if (ins->vex.evex)
10974 break;
10975 *ins->obufp++ = '{';
10976 *ins->obufp++ = 'v';
10977 *ins->obufp++ = 'e';
10978 *ins->obufp++ = 'x';
10979 *ins->obufp++ = '}';
10980 *ins->obufp++ = ' ';
10981 break;
10982 case 'L':
10983 if (ins->rex & REX_W)
10984 {
10985 *ins->obufp++ = 'a';
10986 *ins->obufp++ = 'b';
10987 *ins->obufp++ = 's';
10988 }
10989 goto case_S;
10990 default:
10991 abort ();
10992 }
10993 }
10994 else
10995 abort ();
10996 break;
10997 case 'W':
10998 if (l == 0)
10999 {
11000 /* operand size flag for cwtl, cbtw */
11001 USED_REX (REX_W);
11002 if (ins->rex & REX_W)
11003 {
11004 if (ins->intel_syntax)
11005 *ins->obufp++ = 'd';
11006 else
11007 *ins->obufp++ = 'l';
11008 }
11009 else if (sizeflag & DFLAG)
11010 *ins->obufp++ = 'w';
11011 else
11012 *ins->obufp++ = 'b';
11013 if (!(ins->rex & REX_W))
11014 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11015 }
11016 else if (l == 1)
11017 {
11018 if (!ins->need_vex)
11019 abort ();
11020 if (last[0] == 'X')
11021 *ins->obufp++ = ins->vex.w ? 'd': 's';
11022 else if (last[0] == 'B')
11023 *ins->obufp++ = ins->vex.w ? 'w': 'b';
11024 else
11025 abort ();
11026 }
11027 else
11028 abort ();
11029 break;
11030 case 'X':
11031 if (l != 0)
11032 abort ();
11033 if (ins->need_vex
11034 ? ins->vex.prefix == DATA_PREFIX_OPCODE
11035 : ins->prefixes & PREFIX_DATA)
11036 {
11037 *ins->obufp++ = 'd';
11038 ins->used_prefixes |= PREFIX_DATA;
11039 }
11040 else
11041 *ins->obufp++ = 's';
11042 break;
11043 case 'Y':
11044 if (l == 0)
11045 {
11046 if (ins->vex.mask_register_specifier)
11047 ins->illegal_masking = true;
11048 }
11049 else if (l == 1 && last[0] == 'X')
11050 {
11051 if (!ins->need_vex)
11052 break;
11053 if (ins->intel_syntax
11054 || ((ins->modrm.mod == 3 || ins->vex.b)
11055 && !(sizeflag & SUFFIX_ALWAYS)))
11056 break;
11057 switch (ins->vex.length)
11058 {
11059 case 128:
11060 *ins->obufp++ = 'x';
11061 break;
11062 case 256:
11063 *ins->obufp++ = 'y';
11064 break;
11065 case 512:
11066 if (!ins->vex.evex)
11067 default:
11068 abort ();
11069 }
11070 }
11071 else
11072 abort ();
11073 break;
11074 case 'Z':
11075 if (l == 0)
11076 {
11077 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
11078 ins->modrm.mod = 3;
11079 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11080 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11081 }
11082 else if (l == 1 && last[0] == 'X')
11083 {
11084 if (!ins->vex.evex)
11085 abort ();
11086 if (ins->intel_syntax
11087 || ((ins->modrm.mod == 3 || ins->vex.b)
11088 && !(sizeflag & SUFFIX_ALWAYS)))
11089 break;
11090 switch (ins->vex.length)
11091 {
11092 case 128:
11093 *ins->obufp++ = 'x';
11094 break;
11095 case 256:
11096 *ins->obufp++ = 'y';
11097 break;
11098 case 512:
11099 *ins->obufp++ = 'z';
11100 break;
11101 default:
11102 abort ();
11103 }
11104 }
11105 else
11106 abort ();
11107 break;
11108 case '^':
11109 if (ins->intel_syntax)
11110 break;
11111 if (ins->isa64 == intel64 && (ins->rex & REX_W))
11112 {
11113 USED_REX (REX_W);
11114 *ins->obufp++ = 'q';
11115 break;
11116 }
11117 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11118 {
11119 if (sizeflag & DFLAG)
11120 *ins->obufp++ = 'l';
11121 else
11122 *ins->obufp++ = 'w';
11123 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11124 }
11125 break;
11126 }
11127
11128 if (len == l)
11129 len = l = 0;
11130 }
11131 *ins->obufp = 0;
11132 ins->mnemonicendp = ins->obufp;
11133 return 0;
11134 }
11135
11136 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that
11137 the buffer pointed to by INS->obufp has space. A style marker is made
11138 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11139 digit, followed by another STYLE_MARKER_CHAR. This function assumes
11140 that the number of styles is not greater than 16. */
11141
11142 static void
11143 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11144 {
11145 unsigned num = (unsigned) style;
11146
11147 /* We currently assume that STYLE can be encoded as a single hex
11148 character. If more styles are added then this might start to fail,
11149 and we'll need to expand this code. */
11150 if (num > 0xf)
11151 abort ();
11152
11153 *ins->obufp++ = STYLE_MARKER_CHAR;
11154 *ins->obufp++ = (num < 10 ? ('0' + num)
11155 : ((num < 16) ? ('a' + (num - 10)) : '0'));
11156 *ins->obufp++ = STYLE_MARKER_CHAR;
11157
11158 /* This final null character is not strictly necessary, after inserting a
11159 style marker we should always be inserting some additional content.
11160 However, having the buffer null terminated doesn't cost much, and make
11161 it easier to debug what's going on. Also, if we do ever forget to add
11162 any additional content after this style marker, then the buffer will
11163 still be well formed. */
11164 *ins->obufp = '\0';
11165 }
11166
11167 static void
11168 oappend_with_style (instr_info *ins, const char *s,
11169 enum disassembler_style style)
11170 {
11171 oappend_insert_style (ins, style);
11172 ins->obufp = stpcpy (ins->obufp, s);
11173 }
11174
11175 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11176 the style for the character as STYLE. */
11177
11178 static void
11179 oappend_char_with_style (instr_info *ins, const char c,
11180 enum disassembler_style style)
11181 {
11182 oappend_insert_style (ins, style);
11183 *ins->obufp++ = c;
11184 *ins->obufp = '\0';
11185 }
11186
11187 /* Like oappend_char_with_style, but always uses dis_style_text. */
11188
11189 static void
11190 oappend_char (instr_info *ins, const char c)
11191 {
11192 oappend_char_with_style (ins, c, dis_style_text);
11193 }
11194
11195 static void
11196 append_seg (instr_info *ins)
11197 {
11198 /* Only print the active segment register. */
11199 if (!ins->active_seg_prefix)
11200 return;
11201
11202 ins->used_prefixes |= ins->active_seg_prefix;
11203 switch (ins->active_seg_prefix)
11204 {
11205 case PREFIX_CS:
11206 oappend_register (ins, att_names_seg[1]);
11207 break;
11208 case PREFIX_DS:
11209 oappend_register (ins, att_names_seg[3]);
11210 break;
11211 case PREFIX_SS:
11212 oappend_register (ins, att_names_seg[2]);
11213 break;
11214 case PREFIX_ES:
11215 oappend_register (ins, att_names_seg[0]);
11216 break;
11217 case PREFIX_FS:
11218 oappend_register (ins, att_names_seg[4]);
11219 break;
11220 case PREFIX_GS:
11221 oappend_register (ins, att_names_seg[5]);
11222 break;
11223 default:
11224 break;
11225 }
11226 oappend_char (ins, ':');
11227 }
11228
11229 static void
11230 print_operand_value (instr_info *ins, bfd_vma disp,
11231 enum disassembler_style style)
11232 {
11233 char tmp[30];
11234
11235 if (ins->address_mode != mode_64bit)
11236 disp &= 0xffffffff;
11237 sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11238 oappend_with_style (ins, tmp, style);
11239 }
11240
11241 /* Like oappend, but called for immediate operands. */
11242
11243 static void
11244 oappend_immediate (instr_info *ins, bfd_vma imm)
11245 {
11246 if (!ins->intel_syntax)
11247 oappend_char_with_style (ins, '$', dis_style_immediate);
11248 print_operand_value (ins, imm, dis_style_immediate);
11249 }
11250
11251 /* Put DISP in BUF as signed hex number. */
11252
11253 static void
11254 print_displacement (instr_info *ins, bfd_signed_vma val)
11255 {
11256 char tmp[30];
11257
11258 if (val < 0)
11259 {
11260 oappend_char_with_style (ins, '-', dis_style_address_offset);
11261 val = (bfd_vma) 0 - val;
11262
11263 /* Check for possible overflow. */
11264 if (val < 0)
11265 {
11266 switch (ins->address_mode)
11267 {
11268 case mode_64bit:
11269 oappend_with_style (ins, "0x8000000000000000",
11270 dis_style_address_offset);
11271 break;
11272 case mode_32bit:
11273 oappend_with_style (ins, "0x80000000",
11274 dis_style_address_offset);
11275 break;
11276 case mode_16bit:
11277 oappend_with_style (ins, "0x8000",
11278 dis_style_address_offset);
11279 break;
11280 }
11281 return;
11282 }
11283 }
11284
11285 sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11286 oappend_with_style (ins, tmp, dis_style_address_offset);
11287 }
11288
11289 static void
11290 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11291 {
11292 /* Check if there is a broadcast, when evex.b is not treated as evex.nd. */
11293 if (ins->vex.b && ins->evex_type == evex_default)
11294 {
11295 if (!ins->vex.no_broadcast)
11296 switch (bytemode)
11297 {
11298 case x_mode:
11299 case evex_half_bcst_xmmq_mode:
11300 if (ins->vex.w)
11301 oappend (ins, "QWORD BCST ");
11302 else
11303 oappend (ins, "DWORD BCST ");
11304 break;
11305 case xh_mode:
11306 case evex_half_bcst_xmmqh_mode:
11307 case evex_half_bcst_xmmqdh_mode:
11308 oappend (ins, "WORD BCST ");
11309 break;
11310 default:
11311 ins->vex.no_broadcast = true;
11312 break;
11313 }
11314 return;
11315 }
11316 switch (bytemode)
11317 {
11318 case b_mode:
11319 case b_swap_mode:
11320 case db_mode:
11321 oappend (ins, "BYTE PTR ");
11322 break;
11323 case w_mode:
11324 case w_swap_mode:
11325 case dw_mode:
11326 oappend (ins, "WORD PTR ");
11327 break;
11328 case indir_v_mode:
11329 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11330 {
11331 oappend (ins, "QWORD PTR ");
11332 break;
11333 }
11334 /* Fall through. */
11335 case stack_v_mode:
11336 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11337 || (ins->rex & REX_W)))
11338 {
11339 oappend (ins, "QWORD PTR ");
11340 break;
11341 }
11342 /* Fall through. */
11343 case v_mode:
11344 case v_swap_mode:
11345 case dq_mode:
11346 USED_REX (REX_W);
11347 if (ins->rex & REX_W)
11348 oappend (ins, "QWORD PTR ");
11349 else if (bytemode == dq_mode)
11350 oappend (ins, "DWORD PTR ");
11351 else
11352 {
11353 if (sizeflag & DFLAG)
11354 oappend (ins, "DWORD PTR ");
11355 else
11356 oappend (ins, "WORD PTR ");
11357 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11358 }
11359 break;
11360 case z_mode:
11361 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11362 *ins->obufp++ = 'D';
11363 oappend (ins, "WORD PTR ");
11364 if (!(ins->rex & REX_W))
11365 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11366 break;
11367 case a_mode:
11368 if (sizeflag & DFLAG)
11369 oappend (ins, "QWORD PTR ");
11370 else
11371 oappend (ins, "DWORD PTR ");
11372 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11373 break;
11374 case movsxd_mode:
11375 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11376 oappend (ins, "WORD PTR ");
11377 else
11378 oappend (ins, "DWORD PTR ");
11379 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11380 break;
11381 case d_mode:
11382 case d_swap_mode:
11383 oappend (ins, "DWORD PTR ");
11384 break;
11385 case q_mode:
11386 case q_swap_mode:
11387 oappend (ins, "QWORD PTR ");
11388 break;
11389 case m_mode:
11390 if (ins->address_mode == mode_64bit)
11391 oappend (ins, "QWORD PTR ");
11392 else
11393 oappend (ins, "DWORD PTR ");
11394 break;
11395 case f_mode:
11396 if (sizeflag & DFLAG)
11397 oappend (ins, "FWORD PTR ");
11398 else
11399 oappend (ins, "DWORD PTR ");
11400 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11401 break;
11402 case t_mode:
11403 oappend (ins, "TBYTE PTR ");
11404 break;
11405 case x_mode:
11406 case xh_mode:
11407 case x_swap_mode:
11408 case evex_x_gscat_mode:
11409 case evex_x_nobcst_mode:
11410 case bw_unit_mode:
11411 if (ins->need_vex)
11412 {
11413 switch (ins->vex.length)
11414 {
11415 case 128:
11416 oappend (ins, "XMMWORD PTR ");
11417 break;
11418 case 256:
11419 oappend (ins, "YMMWORD PTR ");
11420 break;
11421 case 512:
11422 oappend (ins, "ZMMWORD PTR ");
11423 break;
11424 default:
11425 abort ();
11426 }
11427 }
11428 else
11429 oappend (ins, "XMMWORD PTR ");
11430 break;
11431 case xmm_mode:
11432 oappend (ins, "XMMWORD PTR ");
11433 break;
11434 case ymm_mode:
11435 oappend (ins, "YMMWORD PTR ");
11436 break;
11437 case xmmq_mode:
11438 case evex_half_bcst_xmmqh_mode:
11439 case evex_half_bcst_xmmq_mode:
11440 switch (ins->vex.length)
11441 {
11442 case 0:
11443 case 128:
11444 oappend (ins, "QWORD PTR ");
11445 break;
11446 case 256:
11447 oappend (ins, "XMMWORD PTR ");
11448 break;
11449 case 512:
11450 oappend (ins, "YMMWORD PTR ");
11451 break;
11452 default:
11453 abort ();
11454 }
11455 break;
11456 case xmmdw_mode:
11457 if (!ins->need_vex)
11458 abort ();
11459
11460 switch (ins->vex.length)
11461 {
11462 case 128:
11463 oappend (ins, "WORD PTR ");
11464 break;
11465 case 256:
11466 oappend (ins, "DWORD PTR ");
11467 break;
11468 case 512:
11469 oappend (ins, "QWORD PTR ");
11470 break;
11471 default:
11472 abort ();
11473 }
11474 break;
11475 case xmmqd_mode:
11476 case evex_half_bcst_xmmqdh_mode:
11477 if (!ins->need_vex)
11478 abort ();
11479
11480 switch (ins->vex.length)
11481 {
11482 case 128:
11483 oappend (ins, "DWORD PTR ");
11484 break;
11485 case 256:
11486 oappend (ins, "QWORD PTR ");
11487 break;
11488 case 512:
11489 oappend (ins, "XMMWORD PTR ");
11490 break;
11491 default:
11492 abort ();
11493 }
11494 break;
11495 case ymmq_mode:
11496 if (!ins->need_vex)
11497 abort ();
11498
11499 switch (ins->vex.length)
11500 {
11501 case 128:
11502 oappend (ins, "QWORD PTR ");
11503 break;
11504 case 256:
11505 oappend (ins, "YMMWORD PTR ");
11506 break;
11507 case 512:
11508 oappend (ins, "ZMMWORD PTR ");
11509 break;
11510 default:
11511 abort ();
11512 }
11513 break;
11514 case o_mode:
11515 oappend (ins, "OWORD PTR ");
11516 break;
11517 case vex_vsib_d_w_dq_mode:
11518 case vex_vsib_q_w_dq_mode:
11519 if (!ins->need_vex)
11520 abort ();
11521 if (ins->vex.w)
11522 oappend (ins, "QWORD PTR ");
11523 else
11524 oappend (ins, "DWORD PTR ");
11525 break;
11526 case mask_bd_mode:
11527 if (!ins->need_vex || ins->vex.length != 128)
11528 abort ();
11529 if (ins->vex.w)
11530 oappend (ins, "DWORD PTR ");
11531 else
11532 oappend (ins, "BYTE PTR ");
11533 break;
11534 case mask_mode:
11535 if (!ins->need_vex)
11536 abort ();
11537 if (ins->vex.w)
11538 oappend (ins, "QWORD PTR ");
11539 else
11540 oappend (ins, "WORD PTR ");
11541 break;
11542 case v_bnd_mode:
11543 case v_bndmk_mode:
11544 default:
11545 break;
11546 }
11547 }
11548
11549 static void
11550 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11551 int bytemode, int sizeflag)
11552 {
11553 const char (*names)[8];
11554
11555 /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11556 as the consumer will inspect it only for the destination operand. */
11557 if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11558 ins->illegal_masking = true;
11559
11560 USED_REX (rexmask);
11561 if (ins->rex & rexmask)
11562 reg += 8;
11563 if (ins->rex2 & rexmask)
11564 reg += 16;
11565
11566 switch (bytemode)
11567 {
11568 case b_mode:
11569 case b_swap_mode:
11570 if (reg & 4)
11571 USED_REX (0);
11572 if (ins->rex || ins->rex2)
11573 names = att_names8rex;
11574 else
11575 names = att_names8;
11576 break;
11577 case w_mode:
11578 names = att_names16;
11579 break;
11580 case d_mode:
11581 case dw_mode:
11582 case db_mode:
11583 names = att_names32;
11584 break;
11585 case q_mode:
11586 names = att_names64;
11587 break;
11588 case m_mode:
11589 case v_bnd_mode:
11590 names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11591 break;
11592 case bnd_mode:
11593 case bnd_swap_mode:
11594 if (reg > 0x3)
11595 {
11596 oappend (ins, "(bad)");
11597 return;
11598 }
11599 names = att_names_bnd;
11600 break;
11601 case indir_v_mode:
11602 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11603 {
11604 names = att_names64;
11605 break;
11606 }
11607 /* Fall through. */
11608 case stack_v_mode:
11609 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11610 || (ins->rex & REX_W)))
11611 {
11612 names = att_names64;
11613 break;
11614 }
11615 bytemode = v_mode;
11616 /* Fall through. */
11617 case v_mode:
11618 case v_swap_mode:
11619 case dq_mode:
11620 USED_REX (REX_W);
11621 if (ins->rex & REX_W)
11622 names = att_names64;
11623 else if (bytemode != v_mode && bytemode != v_swap_mode)
11624 names = att_names32;
11625 else
11626 {
11627 if (sizeflag & DFLAG)
11628 names = att_names32;
11629 else
11630 names = att_names16;
11631 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11632 }
11633 break;
11634 case movsxd_mode:
11635 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11636 names = att_names16;
11637 else
11638 names = att_names32;
11639 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11640 break;
11641 case va_mode:
11642 names = (ins->address_mode == mode_64bit
11643 ? att_names64 : att_names32);
11644 if (!(ins->prefixes & PREFIX_ADDR))
11645 names = (ins->address_mode == mode_16bit
11646 ? att_names16 : names);
11647 else
11648 {
11649 /* Remove "addr16/addr32". */
11650 ins->all_prefixes[ins->last_addr_prefix] = 0;
11651 names = (ins->address_mode != mode_32bit
11652 ? att_names32 : att_names16);
11653 ins->used_prefixes |= PREFIX_ADDR;
11654 }
11655 break;
11656 case mask_bd_mode:
11657 case mask_mode:
11658 if (reg > 0x7)
11659 {
11660 oappend (ins, "(bad)");
11661 return;
11662 }
11663 names = att_names_mask;
11664 break;
11665 case 0:
11666 return;
11667 default:
11668 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11669 return;
11670 }
11671 oappend_register (ins, names[reg]);
11672 }
11673
11674 static bool
11675 get8s (instr_info *ins, bfd_vma *res)
11676 {
11677 if (!fetch_code (ins->info, ins->codep + 1))
11678 return false;
11679 *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11680 return true;
11681 }
11682
11683 static bool
11684 get16 (instr_info *ins, bfd_vma *res)
11685 {
11686 if (!fetch_code (ins->info, ins->codep + 2))
11687 return false;
11688 *res = *ins->codep++;
11689 *res |= (bfd_vma) *ins->codep++ << 8;
11690 return true;
11691 }
11692
11693 static bool
11694 get16s (instr_info *ins, bfd_vma *res)
11695 {
11696 if (!get16 (ins, res))
11697 return false;
11698 *res = (*res ^ 0x8000) - 0x8000;
11699 return true;
11700 }
11701
11702 static bool
11703 get32 (instr_info *ins, bfd_vma *res)
11704 {
11705 if (!fetch_code (ins->info, ins->codep + 4))
11706 return false;
11707 *res = *ins->codep++;
11708 *res |= (bfd_vma) *ins->codep++ << 8;
11709 *res |= (bfd_vma) *ins->codep++ << 16;
11710 *res |= (bfd_vma) *ins->codep++ << 24;
11711 return true;
11712 }
11713
11714 static bool
11715 get32s (instr_info *ins, bfd_vma *res)
11716 {
11717 if (!get32 (ins, res))
11718 return false;
11719
11720 *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11721
11722 return true;
11723 }
11724
11725 static bool
11726 get64 (instr_info *ins, uint64_t *res)
11727 {
11728 unsigned int a;
11729 unsigned int b;
11730
11731 if (!fetch_code (ins->info, ins->codep + 8))
11732 return false;
11733 a = *ins->codep++;
11734 a |= (unsigned int) *ins->codep++ << 8;
11735 a |= (unsigned int) *ins->codep++ << 16;
11736 a |= (unsigned int) *ins->codep++ << 24;
11737 b = *ins->codep++;
11738 b |= (unsigned int) *ins->codep++ << 8;
11739 b |= (unsigned int) *ins->codep++ << 16;
11740 b |= (unsigned int) *ins->codep++ << 24;
11741 *res = a + ((uint64_t) b << 32);
11742 return true;
11743 }
11744
11745 static void
11746 set_op (instr_info *ins, bfd_vma op, bool riprel)
11747 {
11748 ins->op_index[ins->op_ad] = ins->op_ad;
11749 if (ins->address_mode == mode_64bit)
11750 ins->op_address[ins->op_ad] = op;
11751 else /* Mask to get a 32-bit address. */
11752 ins->op_address[ins->op_ad] = op & 0xffffffff;
11753 ins->op_riprel[ins->op_ad] = riprel;
11754 }
11755
11756 static bool
11757 BadOp (instr_info *ins)
11758 {
11759 /* Throw away prefixes and 1st. opcode byte. */
11760 struct dis_private *priv = ins->info->private_data;
11761
11762 ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
11763 ins->obufp = stpcpy (ins->obufp, "(bad)");
11764 return true;
11765 }
11766
11767 static bool
11768 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
11769 int sizeflag ATTRIBUTE_UNUSED)
11770 {
11771 if (ins->modrm.mod != 3)
11772 return BadOp (ins);
11773
11774 /* Skip mod/rm byte. */
11775 MODRM_CHECK;
11776 ins->codep++;
11777 ins->has_skipped_modrm = true;
11778 return true;
11779 }
11780
11781 static bool
11782 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11783 {
11784 int add = (ins->rex & REX_B) ? 8 : 0;
11785 int riprel = 0;
11786 int shift;
11787
11788 add += (ins->rex2 & REX_B) ? 16 : 0;
11789
11790 /* Handles EVEX other than APX EVEX-promoted instructions. */
11791 if (ins->vex.evex && ins->evex_type == evex_default)
11792 {
11793
11794 /* Zeroing-masking is invalid for memory destinations. Set the flag
11795 uniformly, as the consumer will inspect it only for the destination
11796 operand. */
11797 if (ins->vex.zeroing)
11798 ins->illegal_masking = true;
11799
11800 switch (bytemode)
11801 {
11802 case dw_mode:
11803 case w_mode:
11804 case w_swap_mode:
11805 shift = 1;
11806 break;
11807 case db_mode:
11808 case b_mode:
11809 shift = 0;
11810 break;
11811 case dq_mode:
11812 if (ins->address_mode != mode_64bit)
11813 {
11814 case d_mode:
11815 case d_swap_mode:
11816 shift = 2;
11817 break;
11818 }
11819 /* fall through */
11820 case vex_vsib_d_w_dq_mode:
11821 case vex_vsib_q_w_dq_mode:
11822 case evex_x_gscat_mode:
11823 shift = ins->vex.w ? 3 : 2;
11824 break;
11825 case xh_mode:
11826 case evex_half_bcst_xmmqh_mode:
11827 case evex_half_bcst_xmmqdh_mode:
11828 if (ins->vex.b)
11829 {
11830 shift = ins->vex.w ? 2 : 1;
11831 break;
11832 }
11833 /* Fall through. */
11834 case x_mode:
11835 case evex_half_bcst_xmmq_mode:
11836 if (ins->vex.b)
11837 {
11838 shift = ins->vex.w ? 3 : 2;
11839 break;
11840 }
11841 /* Fall through. */
11842 case xmmqd_mode:
11843 case xmmdw_mode:
11844 case xmmq_mode:
11845 case ymmq_mode:
11846 case evex_x_nobcst_mode:
11847 case x_swap_mode:
11848 switch (ins->vex.length)
11849 {
11850 case 128:
11851 shift = 4;
11852 break;
11853 case 256:
11854 shift = 5;
11855 break;
11856 case 512:
11857 shift = 6;
11858 break;
11859 default:
11860 abort ();
11861 }
11862 /* Make necessary corrections to shift for modes that need it. */
11863 if (bytemode == xmmq_mode
11864 || bytemode == evex_half_bcst_xmmqh_mode
11865 || bytemode == evex_half_bcst_xmmq_mode
11866 || (bytemode == ymmq_mode && ins->vex.length == 128))
11867 shift -= 1;
11868 else if (bytemode == xmmqd_mode
11869 || bytemode == evex_half_bcst_xmmqdh_mode)
11870 shift -= 2;
11871 else if (bytemode == xmmdw_mode)
11872 shift -= 3;
11873 break;
11874 case ymm_mode:
11875 shift = 5;
11876 break;
11877 case xmm_mode:
11878 shift = 4;
11879 break;
11880 case q_mode:
11881 case q_swap_mode:
11882 shift = 3;
11883 break;
11884 case bw_unit_mode:
11885 shift = ins->vex.w ? 1 : 0;
11886 break;
11887 default:
11888 abort ();
11889 }
11890 }
11891 else
11892 shift = 0;
11893
11894 USED_REX (REX_B);
11895 if (ins->intel_syntax)
11896 intel_operand_size (ins, bytemode, sizeflag);
11897 append_seg (ins);
11898
11899 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11900 {
11901 /* 32/64 bit address mode */
11902 bfd_vma disp = 0;
11903 int havedisp;
11904 int havebase;
11905 int needindex;
11906 int needaddr32;
11907 int base, rbase;
11908 int vindex = 0;
11909 int scale = 0;
11910 int addr32flag = !((sizeflag & AFLAG)
11911 || bytemode == v_bnd_mode
11912 || bytemode == v_bndmk_mode
11913 || bytemode == bnd_mode
11914 || bytemode == bnd_swap_mode);
11915 bool check_gather = false;
11916 const char (*indexes)[8] = NULL;
11917
11918 havebase = 1;
11919 base = ins->modrm.rm;
11920
11921 if (base == 4)
11922 {
11923 vindex = ins->sib.index;
11924 USED_REX (REX_X);
11925 if (ins->rex & REX_X)
11926 vindex += 8;
11927 switch (bytemode)
11928 {
11929 case vex_vsib_d_w_dq_mode:
11930 case vex_vsib_q_w_dq_mode:
11931 if (!ins->need_vex)
11932 abort ();
11933 if (ins->vex.evex)
11934 {
11935 /* S/G EVEX insns require EVEX.X4 not to be set. */
11936 if (ins->rex2 & REX_X)
11937 {
11938 oappend (ins, "(bad)");
11939 return true;
11940 }
11941
11942 if (!ins->vex.v)
11943 vindex += 16;
11944 check_gather = ins->obufp == ins->op_out[1];
11945 }
11946
11947 switch (ins->vex.length)
11948 {
11949 case 128:
11950 indexes = att_names_xmm;
11951 break;
11952 case 256:
11953 if (!ins->vex.w
11954 || bytemode == vex_vsib_q_w_dq_mode)
11955 indexes = att_names_ymm;
11956 else
11957 indexes = att_names_xmm;
11958 break;
11959 case 512:
11960 if (!ins->vex.w
11961 || bytemode == vex_vsib_q_w_dq_mode)
11962 indexes = att_names_zmm;
11963 else
11964 indexes = att_names_ymm;
11965 break;
11966 default:
11967 abort ();
11968 }
11969 break;
11970 default:
11971 if (ins->rex2 & REX_X)
11972 vindex += 16;
11973
11974 if (vindex != 4)
11975 indexes = ins->address_mode == mode_64bit && !addr32flag
11976 ? att_names64 : att_names32;
11977 break;
11978 }
11979 scale = ins->sib.scale;
11980 base = ins->sib.base;
11981 ins->codep++;
11982 }
11983 else
11984 {
11985 /* Check for mandatory SIB. */
11986 if (bytemode == vex_vsib_d_w_dq_mode
11987 || bytemode == vex_vsib_q_w_dq_mode
11988 || bytemode == vex_sibmem_mode)
11989 {
11990 oappend (ins, "(bad)");
11991 return true;
11992 }
11993 }
11994 rbase = base + add;
11995
11996 switch (ins->modrm.mod)
11997 {
11998 case 0:
11999 if (base == 5)
12000 {
12001 havebase = 0;
12002 if (ins->address_mode == mode_64bit && !ins->has_sib)
12003 riprel = 1;
12004 if (!get32s (ins, &disp))
12005 return false;
12006 if (riprel && bytemode == v_bndmk_mode)
12007 {
12008 oappend (ins, "(bad)");
12009 return true;
12010 }
12011 }
12012 break;
12013 case 1:
12014 if (!get8s (ins, &disp))
12015 return false;
12016 if (ins->vex.evex && shift > 0)
12017 disp <<= shift;
12018 break;
12019 case 2:
12020 if (!get32s (ins, &disp))
12021 return false;
12022 break;
12023 }
12024
12025 needindex = 0;
12026 needaddr32 = 0;
12027 if (ins->has_sib
12028 && !havebase
12029 && !indexes
12030 && ins->address_mode != mode_16bit)
12031 {
12032 if (ins->address_mode == mode_64bit)
12033 {
12034 if (addr32flag)
12035 {
12036 /* Without base nor index registers, zero-extend the
12037 lower 32-bit displacement to 64 bits. */
12038 disp &= 0xffffffff;
12039 needindex = 1;
12040 }
12041 needaddr32 = 1;
12042 }
12043 else
12044 {
12045 /* In 32-bit mode, we need index register to tell [offset]
12046 from [eiz*1 + offset]. */
12047 needindex = 1;
12048 }
12049 }
12050
12051 havedisp = (havebase
12052 || needindex
12053 || (ins->has_sib && (indexes || scale != 0)));
12054
12055 if (!ins->intel_syntax)
12056 if (ins->modrm.mod != 0 || base == 5)
12057 {
12058 if (havedisp || riprel)
12059 print_displacement (ins, disp);
12060 else
12061 print_operand_value (ins, disp, dis_style_address_offset);
12062 if (riprel)
12063 {
12064 set_op (ins, disp, true);
12065 oappend_char (ins, '(');
12066 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
12067 dis_style_register);
12068 oappend_char (ins, ')');
12069 }
12070 }
12071
12072 if ((havebase || indexes || needindex || needaddr32 || riprel)
12073 && (ins->address_mode != mode_64bit
12074 || ((bytemode != v_bnd_mode)
12075 && (bytemode != v_bndmk_mode)
12076 && (bytemode != bnd_mode)
12077 && (bytemode != bnd_swap_mode))))
12078 ins->used_prefixes |= PREFIX_ADDR;
12079
12080 if (havedisp || (ins->intel_syntax && riprel))
12081 {
12082 oappend_char (ins, ins->open_char);
12083 if (ins->intel_syntax && riprel)
12084 {
12085 set_op (ins, disp, true);
12086 oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12087 dis_style_register);
12088 }
12089 if (havebase)
12090 oappend_register
12091 (ins,
12092 (ins->address_mode == mode_64bit && !addr32flag
12093 ? att_names64 : att_names32)[rbase]);
12094 if (ins->has_sib)
12095 {
12096 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12097 print index to tell base + index from base. */
12098 if (scale != 0
12099 || needindex
12100 || indexes
12101 || (havebase && base != ESP_REG_NUM))
12102 {
12103 if (!ins->intel_syntax || havebase)
12104 oappend_char (ins, ins->separator_char);
12105 if (indexes)
12106 {
12107 if (ins->address_mode == mode_64bit || vindex < 16)
12108 oappend_register (ins, indexes[vindex]);
12109 else
12110 oappend (ins, "(bad)");
12111 }
12112 else
12113 oappend_register (ins,
12114 ins->address_mode == mode_64bit
12115 && !addr32flag
12116 ? att_index64
12117 : att_index32);
12118
12119 oappend_char (ins, ins->scale_char);
12120 oappend_char_with_style (ins, '0' + (1 << scale),
12121 dis_style_immediate);
12122 }
12123 }
12124 if (ins->intel_syntax
12125 && (disp || ins->modrm.mod != 0 || base == 5))
12126 {
12127 if (!havedisp || (bfd_signed_vma) disp >= 0)
12128 oappend_char (ins, '+');
12129 if (havedisp)
12130 print_displacement (ins, disp);
12131 else
12132 print_operand_value (ins, disp, dis_style_address_offset);
12133 }
12134
12135 oappend_char (ins, ins->close_char);
12136
12137 if (check_gather)
12138 {
12139 /* Both XMM/YMM/ZMM registers must be distinct. */
12140 int modrm_reg = ins->modrm.reg;
12141
12142 if (ins->rex & REX_R)
12143 modrm_reg += 8;
12144 if (ins->rex2 & REX_R)
12145 modrm_reg += 16;
12146 if (vindex == modrm_reg)
12147 oappend (ins, "/(bad)");
12148 }
12149 }
12150 else if (ins->intel_syntax)
12151 {
12152 if (ins->modrm.mod != 0 || base == 5)
12153 {
12154 if (!ins->active_seg_prefix)
12155 {
12156 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12157 oappend (ins, ":");
12158 }
12159 print_operand_value (ins, disp, dis_style_text);
12160 }
12161 }
12162 }
12163 else if (bytemode == v_bnd_mode
12164 || bytemode == v_bndmk_mode
12165 || bytemode == bnd_mode
12166 || bytemode == bnd_swap_mode
12167 || bytemode == vex_vsib_d_w_dq_mode
12168 || bytemode == vex_vsib_q_w_dq_mode)
12169 {
12170 oappend (ins, "(bad)");
12171 return true;
12172 }
12173 else
12174 {
12175 /* 16 bit address mode */
12176 bfd_vma disp = 0;
12177
12178 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12179 switch (ins->modrm.mod)
12180 {
12181 case 0:
12182 if (ins->modrm.rm == 6)
12183 {
12184 case 2:
12185 if (!get16s (ins, &disp))
12186 return false;
12187 }
12188 break;
12189 case 1:
12190 if (!get8s (ins, &disp))
12191 return false;
12192 if (ins->vex.evex && shift > 0)
12193 disp <<= shift;
12194 break;
12195 }
12196
12197 if (!ins->intel_syntax)
12198 if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12199 print_displacement (ins, disp);
12200
12201 if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12202 {
12203 oappend_char (ins, ins->open_char);
12204 oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12205 : att_index16[ins->modrm.rm]);
12206 if (ins->intel_syntax
12207 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12208 {
12209 if ((bfd_signed_vma) disp >= 0)
12210 oappend_char (ins, '+');
12211 print_displacement (ins, disp);
12212 }
12213
12214 oappend_char (ins, ins->close_char);
12215 }
12216 else if (ins->intel_syntax)
12217 {
12218 if (!ins->active_seg_prefix)
12219 {
12220 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12221 oappend (ins, ":");
12222 }
12223 print_operand_value (ins, disp & 0xffff, dis_style_text);
12224 }
12225 }
12226 if (ins->vex.b && ins->evex_type == evex_default)
12227 {
12228 ins->evex_used |= EVEX_b_used;
12229
12230 /* Broadcast can only ever be valid for memory sources. */
12231 if (ins->obufp == ins->op_out[0])
12232 ins->vex.no_broadcast = true;
12233
12234 if (!ins->vex.no_broadcast
12235 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12236 {
12237 if (bytemode == xh_mode)
12238 {
12239 switch (ins->vex.length)
12240 {
12241 case 128:
12242 oappend (ins, "{1to8}");
12243 break;
12244 case 256:
12245 oappend (ins, "{1to16}");
12246 break;
12247 case 512:
12248 oappend (ins, "{1to32}");
12249 break;
12250 default:
12251 abort ();
12252 }
12253 }
12254 else if (bytemode == q_mode
12255 || bytemode == ymmq_mode)
12256 ins->vex.no_broadcast = true;
12257 else if (ins->vex.w
12258 || bytemode == evex_half_bcst_xmmqdh_mode
12259 || bytemode == evex_half_bcst_xmmq_mode)
12260 {
12261 switch (ins->vex.length)
12262 {
12263 case 128:
12264 oappend (ins, "{1to2}");
12265 break;
12266 case 256:
12267 oappend (ins, "{1to4}");
12268 break;
12269 case 512:
12270 oappend (ins, "{1to8}");
12271 break;
12272 default:
12273 abort ();
12274 }
12275 }
12276 else if (bytemode == x_mode
12277 || bytemode == evex_half_bcst_xmmqh_mode)
12278 {
12279 switch (ins->vex.length)
12280 {
12281 case 128:
12282 oappend (ins, "{1to4}");
12283 break;
12284 case 256:
12285 oappend (ins, "{1to8}");
12286 break;
12287 case 512:
12288 oappend (ins, "{1to16}");
12289 break;
12290 default:
12291 abort ();
12292 }
12293 }
12294 else
12295 ins->vex.no_broadcast = true;
12296 }
12297 if (ins->vex.no_broadcast)
12298 oappend (ins, "{bad}");
12299 }
12300
12301 return true;
12302 }
12303
12304 static bool
12305 OP_E (instr_info *ins, int bytemode, int sizeflag)
12306 {
12307 /* Skip mod/rm byte. */
12308 MODRM_CHECK;
12309 if (!ins->has_skipped_modrm)
12310 {
12311 ins->codep++;
12312 ins->has_skipped_modrm = true;
12313 }
12314
12315 if (ins->modrm.mod == 3)
12316 {
12317 if ((sizeflag & SUFFIX_ALWAYS)
12318 && (bytemode == b_swap_mode
12319 || bytemode == bnd_swap_mode
12320 || bytemode == v_swap_mode))
12321 swap_operand (ins);
12322
12323 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12324 return true;
12325 }
12326
12327 /* Masking is invalid for insns with GPR-like memory destination. Set the
12328 flag uniformly, as the consumer will inspect it only for the destination
12329 operand. */
12330 if (ins->vex.mask_register_specifier)
12331 ins->illegal_masking = true;
12332
12333 return OP_E_memory (ins, bytemode, sizeflag);
12334 }
12335
12336 static bool
12337 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12338 {
12339 if (ins->modrm.mod == 3 && bytemode == f_mode)
12340 /* bad lcall/ljmp */
12341 return BadOp (ins);
12342 if (!ins->intel_syntax)
12343 oappend (ins, "*");
12344 return OP_E (ins, bytemode, sizeflag);
12345 }
12346
12347 static bool
12348 OP_G (instr_info *ins, int bytemode, int sizeflag)
12349 {
12350 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12351 return true;
12352 }
12353
12354 static bool
12355 OP_REG (instr_info *ins, int code, int sizeflag)
12356 {
12357 const char *s;
12358 int add = 0;
12359
12360 switch (code)
12361 {
12362 case es_reg: case ss_reg: case cs_reg:
12363 case ds_reg: case fs_reg: case gs_reg:
12364 oappend_register (ins, att_names_seg[code - es_reg]);
12365 return true;
12366 }
12367
12368 USED_REX (REX_B);
12369 if (ins->rex & REX_B)
12370 add = 8;
12371 if (ins->rex2 & REX_B)
12372 add += 16;
12373
12374 switch (code)
12375 {
12376 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12377 case sp_reg: case bp_reg: case si_reg: case di_reg:
12378 s = att_names16[code - ax_reg + add];
12379 break;
12380 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12381 USED_REX (0);
12382 /* Fall through. */
12383 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12384 if (ins->rex)
12385 s = att_names8rex[code - al_reg + add];
12386 else
12387 s = att_names8[code - al_reg];
12388 break;
12389 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12390 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12391 if (ins->address_mode == mode_64bit
12392 && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12393 {
12394 s = att_names64[code - rAX_reg + add];
12395 break;
12396 }
12397 code += eAX_reg - rAX_reg;
12398 /* Fall through. */
12399 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12400 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12401 USED_REX (REX_W);
12402 if (ins->rex & REX_W)
12403 s = att_names64[code - eAX_reg + add];
12404 else
12405 {
12406 if (sizeflag & DFLAG)
12407 s = att_names32[code - eAX_reg + add];
12408 else
12409 s = att_names16[code - eAX_reg + add];
12410 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12411 }
12412 break;
12413 default:
12414 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12415 return true;
12416 }
12417 oappend_register (ins, s);
12418 return true;
12419 }
12420
12421 static bool
12422 OP_IMREG (instr_info *ins, int code, int sizeflag)
12423 {
12424 const char *s;
12425
12426 switch (code)
12427 {
12428 case indir_dx_reg:
12429 if (!ins->intel_syntax)
12430 {
12431 oappend (ins, "(%dx)");
12432 return true;
12433 }
12434 s = att_names16[dx_reg - ax_reg];
12435 break;
12436 case al_reg: case cl_reg:
12437 s = att_names8[code - al_reg];
12438 break;
12439 case eAX_reg:
12440 USED_REX (REX_W);
12441 if (ins->rex & REX_W)
12442 {
12443 s = *att_names64;
12444 break;
12445 }
12446 /* Fall through. */
12447 case z_mode_ax_reg:
12448 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12449 s = *att_names32;
12450 else
12451 s = *att_names16;
12452 if (!(ins->rex & REX_W))
12453 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12454 break;
12455 default:
12456 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12457 return true;
12458 }
12459 oappend_register (ins, s);
12460 return true;
12461 }
12462
12463 static bool
12464 OP_I (instr_info *ins, int bytemode, int sizeflag)
12465 {
12466 bfd_vma op;
12467
12468 switch (bytemode)
12469 {
12470 case b_mode:
12471 if (!fetch_code (ins->info, ins->codep + 1))
12472 return false;
12473 op = *ins->codep++;
12474 break;
12475 case v_mode:
12476 USED_REX (REX_W);
12477 if (ins->rex & REX_W)
12478 {
12479 if (!get32s (ins, &op))
12480 return false;
12481 }
12482 else
12483 {
12484 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12485 if (sizeflag & DFLAG)
12486 {
12487 case d_mode:
12488 if (!get32 (ins, &op))
12489 return false;
12490 }
12491 else
12492 {
12493 /* Fall through. */
12494 case w_mode:
12495 if (!get16 (ins, &op))
12496 return false;
12497 }
12498 }
12499 break;
12500 case const_1_mode:
12501 if (ins->intel_syntax)
12502 oappend_with_style (ins, "1", dis_style_immediate);
12503 else
12504 oappend_with_style (ins, "$1", dis_style_immediate);
12505 return true;
12506 default:
12507 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12508 return true;
12509 }
12510
12511 oappend_immediate (ins, op);
12512 return true;
12513 }
12514
12515 static bool
12516 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12517 {
12518 uint64_t op;
12519
12520 if (bytemode != v_mode || ins->address_mode != mode_64bit
12521 || !(ins->rex & REX_W))
12522 return OP_I (ins, bytemode, sizeflag);
12523
12524 USED_REX (REX_W);
12525
12526 if (!get64 (ins, &op))
12527 return false;
12528
12529 oappend_immediate (ins, op);
12530 return true;
12531 }
12532
12533 static bool
12534 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12535 {
12536 bfd_vma op;
12537
12538 switch (bytemode)
12539 {
12540 case b_mode:
12541 case b_T_mode:
12542 if (!get8s (ins, &op))
12543 return false;
12544 if (bytemode == b_T_mode)
12545 {
12546 if (ins->address_mode != mode_64bit
12547 || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12548 {
12549 /* The operand-size prefix is overridden by a REX prefix. */
12550 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12551 op &= 0xffffffff;
12552 else
12553 op &= 0xffff;
12554 }
12555 }
12556 else
12557 {
12558 if (!(ins->rex & REX_W))
12559 {
12560 if (sizeflag & DFLAG)
12561 op &= 0xffffffff;
12562 else
12563 op &= 0xffff;
12564 }
12565 }
12566 break;
12567 case v_mode:
12568 /* The operand-size prefix is overridden by a REX prefix. */
12569 if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12570 {
12571 if (!get16 (ins, &op))
12572 return false;
12573 }
12574 else if (!get32s (ins, &op))
12575 return false;
12576 break;
12577 default:
12578 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12579 return true;
12580 }
12581
12582 oappend_immediate (ins, op);
12583 return true;
12584 }
12585
12586 static bool
12587 OP_J (instr_info *ins, int bytemode, int sizeflag)
12588 {
12589 bfd_vma disp;
12590 bfd_vma mask = -1;
12591 bfd_vma segment = 0;
12592
12593 switch (bytemode)
12594 {
12595 case b_mode:
12596 if (!get8s (ins, &disp))
12597 return false;
12598 break;
12599 case v_mode:
12600 case dqw_mode:
12601 if ((sizeflag & DFLAG)
12602 || (ins->address_mode == mode_64bit
12603 && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12604 || (ins->rex & REX_W))))
12605 {
12606 if (!get32s (ins, &disp))
12607 return false;
12608 }
12609 else
12610 {
12611 if (!get16s (ins, &disp))
12612 return false;
12613 /* In 16bit mode, address is wrapped around at 64k within
12614 the same segment. Otherwise, a data16 prefix on a jump
12615 instruction means that the pc is masked to 16 bits after
12616 the displacement is added! */
12617 mask = 0xffff;
12618 if ((ins->prefixes & PREFIX_DATA) == 0)
12619 segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12620 & ~((bfd_vma) 0xffff));
12621 }
12622 if (ins->address_mode != mode_64bit
12623 || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12624 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12625 break;
12626 default:
12627 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12628 return true;
12629 }
12630 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12631 | segment;
12632 set_op (ins, disp, false);
12633 print_operand_value (ins, disp, dis_style_text);
12634 return true;
12635 }
12636
12637 static bool
12638 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12639 {
12640 if (bytemode == w_mode)
12641 {
12642 oappend_register (ins, att_names_seg[ins->modrm.reg]);
12643 return true;
12644 }
12645 return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12646 }
12647
12648 static bool
12649 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12650 {
12651 bfd_vma seg, offset;
12652 int res;
12653 char scratch[24];
12654
12655 if (sizeflag & DFLAG)
12656 {
12657 if (!get32 (ins, &offset))
12658 return false;;
12659 }
12660 else if (!get16 (ins, &offset))
12661 return false;
12662 if (!get16 (ins, &seg))
12663 return false;;
12664 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12665
12666 res = snprintf (scratch, ARRAY_SIZE (scratch),
12667 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12668 (unsigned) seg, (unsigned) offset);
12669 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12670 abort ();
12671 oappend (ins, scratch);
12672 return true;
12673 }
12674
12675 static bool
12676 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12677 {
12678 bfd_vma off;
12679
12680 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12681 intel_operand_size (ins, bytemode, sizeflag);
12682 append_seg (ins);
12683
12684 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12685 {
12686 if (!get32 (ins, &off))
12687 return false;
12688 }
12689 else
12690 {
12691 if (!get16 (ins, &off))
12692 return false;
12693 }
12694
12695 if (ins->intel_syntax)
12696 {
12697 if (!ins->active_seg_prefix)
12698 {
12699 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12700 oappend (ins, ":");
12701 }
12702 }
12703 print_operand_value (ins, off, dis_style_address_offset);
12704 return true;
12705 }
12706
12707 static bool
12708 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12709 {
12710 uint64_t off;
12711
12712 if (ins->address_mode != mode_64bit
12713 || (ins->prefixes & PREFIX_ADDR))
12714 return OP_OFF (ins, bytemode, sizeflag);
12715
12716 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12717 intel_operand_size (ins, bytemode, sizeflag);
12718 append_seg (ins);
12719
12720 if (!get64 (ins, &off))
12721 return false;
12722
12723 if (ins->intel_syntax)
12724 {
12725 if (!ins->active_seg_prefix)
12726 {
12727 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12728 oappend (ins, ":");
12729 }
12730 }
12731 print_operand_value (ins, off, dis_style_address_offset);
12732 return true;
12733 }
12734
12735 static void
12736 ptr_reg (instr_info *ins, int code, int sizeflag)
12737 {
12738 const char *s;
12739
12740 *ins->obufp++ = ins->open_char;
12741 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12742 if (ins->address_mode == mode_64bit)
12743 {
12744 if (!(sizeflag & AFLAG))
12745 s = att_names32[code - eAX_reg];
12746 else
12747 s = att_names64[code - eAX_reg];
12748 }
12749 else if (sizeflag & AFLAG)
12750 s = att_names32[code - eAX_reg];
12751 else
12752 s = att_names16[code - eAX_reg];
12753 oappend_register (ins, s);
12754 oappend_char (ins, ins->close_char);
12755 }
12756
12757 static bool
12758 OP_ESreg (instr_info *ins, int code, int sizeflag)
12759 {
12760 if (ins->intel_syntax)
12761 {
12762 switch (ins->codep[-1])
12763 {
12764 case 0x6d: /* insw/insl */
12765 intel_operand_size (ins, z_mode, sizeflag);
12766 break;
12767 case 0xa5: /* movsw/movsl/movsq */
12768 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12769 case 0xab: /* stosw/stosl */
12770 case 0xaf: /* scasw/scasl */
12771 intel_operand_size (ins, v_mode, sizeflag);
12772 break;
12773 default:
12774 intel_operand_size (ins, b_mode, sizeflag);
12775 }
12776 }
12777 oappend_register (ins, att_names_seg[0]);
12778 oappend_char (ins, ':');
12779 ptr_reg (ins, code, sizeflag);
12780 return true;
12781 }
12782
12783 static bool
12784 OP_DSreg (instr_info *ins, int code, int sizeflag)
12785 {
12786 if (ins->intel_syntax)
12787 {
12788 switch (ins->codep[-1])
12789 {
12790 case 0x6f: /* outsw/outsl */
12791 intel_operand_size (ins, z_mode, sizeflag);
12792 break;
12793 case 0xa5: /* movsw/movsl/movsq */
12794 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12795 case 0xad: /* lodsw/lodsl/lodsq */
12796 intel_operand_size (ins, v_mode, sizeflag);
12797 break;
12798 default:
12799 intel_operand_size (ins, b_mode, sizeflag);
12800 }
12801 }
12802 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12803 default segment register DS is printed. */
12804 if (!ins->active_seg_prefix)
12805 ins->active_seg_prefix = PREFIX_DS;
12806 append_seg (ins);
12807 ptr_reg (ins, code, sizeflag);
12808 return true;
12809 }
12810
12811 static bool
12812 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12813 int sizeflag ATTRIBUTE_UNUSED)
12814 {
12815 int add, res;
12816 char scratch[8];
12817
12818 if (ins->rex & REX_R)
12819 {
12820 USED_REX (REX_R);
12821 add = 8;
12822 }
12823 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12824 {
12825 ins->all_prefixes[ins->last_lock_prefix] = 0;
12826 ins->used_prefixes |= PREFIX_LOCK;
12827 add = 8;
12828 }
12829 else
12830 add = 0;
12831 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12832 ins->modrm.reg + add);
12833 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12834 abort ();
12835 oappend_register (ins, scratch);
12836 return true;
12837 }
12838
12839 static bool
12840 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12841 int sizeflag ATTRIBUTE_UNUSED)
12842 {
12843 int add, res;
12844 char scratch[8];
12845
12846 USED_REX (REX_R);
12847 if (ins->rex & REX_R)
12848 add = 8;
12849 else
12850 add = 0;
12851 res = snprintf (scratch, ARRAY_SIZE (scratch),
12852 ins->intel_syntax ? "dr%d" : "%%db%d",
12853 ins->modrm.reg + add);
12854 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12855 abort ();
12856 oappend (ins, scratch);
12857 return true;
12858 }
12859
12860 static bool
12861 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12862 int sizeflag ATTRIBUTE_UNUSED)
12863 {
12864 int res;
12865 char scratch[8];
12866
12867 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12868 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12869 abort ();
12870 oappend_register (ins, scratch);
12871 return true;
12872 }
12873
12874 static bool
12875 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12876 int sizeflag ATTRIBUTE_UNUSED)
12877 {
12878 int reg = ins->modrm.reg;
12879 const char (*names)[8];
12880
12881 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12882 if (ins->prefixes & PREFIX_DATA)
12883 {
12884 names = att_names_xmm;
12885 USED_REX (REX_R);
12886 if (ins->rex & REX_R)
12887 reg += 8;
12888 }
12889 else
12890 names = att_names_mm;
12891 oappend_register (ins, names[reg]);
12892 return true;
12893 }
12894
12895 static void
12896 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12897 {
12898 const char (*names)[8];
12899
12900 if (bytemode == xmmq_mode
12901 || bytemode == evex_half_bcst_xmmqh_mode
12902 || bytemode == evex_half_bcst_xmmq_mode)
12903 {
12904 switch (ins->vex.length)
12905 {
12906 case 0:
12907 case 128:
12908 case 256:
12909 names = att_names_xmm;
12910 break;
12911 case 512:
12912 names = att_names_ymm;
12913 ins->evex_used |= EVEX_len_used;
12914 break;
12915 default:
12916 abort ();
12917 }
12918 }
12919 else if (bytemode == ymm_mode)
12920 names = att_names_ymm;
12921 else if (bytemode == tmm_mode)
12922 {
12923 if (reg >= 8)
12924 {
12925 oappend (ins, "(bad)");
12926 return;
12927 }
12928 names = att_names_tmm;
12929 }
12930 else if (ins->need_vex
12931 && bytemode != xmm_mode
12932 && bytemode != scalar_mode
12933 && bytemode != xmmdw_mode
12934 && bytemode != xmmqd_mode
12935 && bytemode != evex_half_bcst_xmmqdh_mode
12936 && bytemode != w_swap_mode
12937 && bytemode != b_mode
12938 && bytemode != w_mode
12939 && bytemode != d_mode
12940 && bytemode != q_mode)
12941 {
12942 ins->evex_used |= EVEX_len_used;
12943 switch (ins->vex.length)
12944 {
12945 case 128:
12946 names = att_names_xmm;
12947 break;
12948 case 256:
12949 if (ins->vex.w
12950 || bytemode != vex_vsib_q_w_dq_mode)
12951 names = att_names_ymm;
12952 else
12953 names = att_names_xmm;
12954 break;
12955 case 512:
12956 if (ins->vex.w
12957 || bytemode != vex_vsib_q_w_dq_mode)
12958 names = att_names_zmm;
12959 else
12960 names = att_names_ymm;
12961 break;
12962 default:
12963 abort ();
12964 }
12965 }
12966 else
12967 names = att_names_xmm;
12968 oappend_register (ins, names[reg]);
12969 }
12970
12971 static bool
12972 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12973 {
12974 unsigned int reg = ins->modrm.reg;
12975
12976 USED_REX (REX_R);
12977 if (ins->rex & REX_R)
12978 reg += 8;
12979 if (ins->vex.evex)
12980 {
12981 if (ins->rex2 & REX_R)
12982 reg += 16;
12983 }
12984
12985 if (bytemode == tmm_mode)
12986 ins->modrm.reg = reg;
12987 else if (bytemode == scalar_mode)
12988 ins->vex.no_broadcast = true;
12989
12990 print_vector_reg (ins, reg, bytemode);
12991 return true;
12992 }
12993
12994 static bool
12995 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12996 {
12997 int reg;
12998 const char (*names)[8];
12999
13000 if (ins->modrm.mod != 3)
13001 {
13002 if (ins->intel_syntax
13003 && (bytemode == v_mode || bytemode == v_swap_mode))
13004 {
13005 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13006 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13007 }
13008 return OP_E (ins, bytemode, sizeflag);
13009 }
13010
13011 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13012 swap_operand (ins);
13013
13014 /* Skip mod/rm byte. */
13015 MODRM_CHECK;
13016 ins->codep++;
13017 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13018 reg = ins->modrm.rm;
13019 if (ins->prefixes & PREFIX_DATA)
13020 {
13021 names = att_names_xmm;
13022 USED_REX (REX_B);
13023 if (ins->rex & REX_B)
13024 reg += 8;
13025 }
13026 else
13027 names = att_names_mm;
13028 oappend_register (ins, names[reg]);
13029 return true;
13030 }
13031
13032 /* cvt* are the only instructions in sse2 which have
13033 both SSE and MMX operands and also have 0x66 prefix
13034 in their opcode. 0x66 was originally used to differentiate
13035 between SSE and MMX instruction(operands). So we have to handle the
13036 cvt* separately using OP_EMC and OP_MXC */
13037 static bool
13038 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
13039 {
13040 if (ins->modrm.mod != 3)
13041 {
13042 if (ins->intel_syntax && bytemode == v_mode)
13043 {
13044 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13045 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13046 }
13047 return OP_E (ins, bytemode, sizeflag);
13048 }
13049
13050 /* Skip mod/rm byte. */
13051 MODRM_CHECK;
13052 ins->codep++;
13053 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13054 oappend_register (ins, att_names_mm[ins->modrm.rm]);
13055 return true;
13056 }
13057
13058 static bool
13059 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13060 int sizeflag ATTRIBUTE_UNUSED)
13061 {
13062 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13063 oappend_register (ins, att_names_mm[ins->modrm.reg]);
13064 return true;
13065 }
13066
13067 static bool
13068 OP_EX (instr_info *ins, int bytemode, int sizeflag)
13069 {
13070 int reg;
13071
13072 /* Skip mod/rm byte. */
13073 MODRM_CHECK;
13074 ins->codep++;
13075
13076 if (bytemode == dq_mode)
13077 bytemode = ins->vex.w ? q_mode : d_mode;
13078
13079 if (ins->modrm.mod != 3)
13080 return OP_E_memory (ins, bytemode, sizeflag);
13081
13082 reg = ins->modrm.rm;
13083 USED_REX (REX_B);
13084 if (ins->rex & REX_B)
13085 reg += 8;
13086 if (ins->vex.evex)
13087 {
13088 USED_REX (REX_X);
13089 if ((ins->rex & REX_X))
13090 reg += 16;
13091 ins->rex2_used &= ~REX_B;
13092 }
13093 else if (ins->rex2 & REX_B)
13094 reg += 16;
13095
13096 if ((sizeflag & SUFFIX_ALWAYS)
13097 && (bytemode == x_swap_mode
13098 || bytemode == w_swap_mode
13099 || bytemode == d_swap_mode
13100 || bytemode == q_swap_mode))
13101 swap_operand (ins);
13102
13103 if (bytemode == tmm_mode)
13104 ins->modrm.rm = reg;
13105
13106 print_vector_reg (ins, reg, bytemode);
13107 return true;
13108 }
13109
13110 static bool
13111 OP_R (instr_info *ins, int bytemode, int sizeflag)
13112 {
13113 if (ins->modrm.mod != 3)
13114 return BadOp (ins);
13115
13116 switch (bytemode)
13117 {
13118 case d_mode:
13119 case dq_mode:
13120 case q_mode:
13121 case mask_mode:
13122 return OP_E (ins, bytemode, sizeflag);
13123 case q_mm_mode:
13124 return OP_EM (ins, x_mode, sizeflag);
13125 case xmm_mode:
13126 if (ins->vex.length <= 128)
13127 break;
13128 return BadOp (ins);
13129 }
13130
13131 return OP_EX (ins, bytemode, sizeflag);
13132 }
13133
13134 static bool
13135 OP_M (instr_info *ins, int bytemode, int sizeflag)
13136 {
13137 /* Skip mod/rm byte. */
13138 MODRM_CHECK;
13139 ins->codep++;
13140
13141 if (ins->modrm.mod == 3)
13142 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13143 return BadOp (ins);
13144
13145 if (bytemode == x_mode)
13146 ins->vex.no_broadcast = true;
13147
13148 return OP_E_memory (ins, bytemode, sizeflag);
13149 }
13150
13151 static bool
13152 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13153 {
13154 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13155 return BadOp (ins);
13156 return OP_E (ins, bytemode, sizeflag);
13157 }
13158
13159 /* montmul instruction need display repz and skip modrm */
13160
13161 static bool
13162 MONTMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13163 {
13164 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13165 return BadOp (ins);
13166
13167 /* The 0xf3 prefix should be displayed as "repz" for montmul. */
13168 if (ins->prefixes & PREFIX_REPZ)
13169 ins->all_prefixes[ins->last_repz_prefix] = 0xf3;
13170
13171 /* Skip mod/rm byte. */
13172 MODRM_CHECK;
13173 ins->codep++;
13174 return true;
13175 }
13176
13177 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13178 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13179
13180 static bool
13181 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13182 {
13183 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13184 {
13185 ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13186 return true;
13187 }
13188 if (opnd == 0)
13189 return OP_REG (ins, eAX_reg, sizeflag);
13190 return OP_IMREG (ins, eAX_reg, sizeflag);
13191 }
13192
13193 static const char *const Suffix3DNow[] = {
13194 /* 00 */ NULL, NULL, NULL, NULL,
13195 /* 04 */ NULL, NULL, NULL, NULL,
13196 /* 08 */ NULL, NULL, NULL, NULL,
13197 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13198 /* 10 */ NULL, NULL, NULL, NULL,
13199 /* 14 */ NULL, NULL, NULL, NULL,
13200 /* 18 */ NULL, NULL, NULL, NULL,
13201 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13202 /* 20 */ NULL, NULL, NULL, NULL,
13203 /* 24 */ NULL, NULL, NULL, NULL,
13204 /* 28 */ NULL, NULL, NULL, NULL,
13205 /* 2C */ NULL, NULL, NULL, NULL,
13206 /* 30 */ NULL, NULL, NULL, NULL,
13207 /* 34 */ NULL, NULL, NULL, NULL,
13208 /* 38 */ NULL, NULL, NULL, NULL,
13209 /* 3C */ NULL, NULL, NULL, NULL,
13210 /* 40 */ NULL, NULL, NULL, NULL,
13211 /* 44 */ NULL, NULL, NULL, NULL,
13212 /* 48 */ NULL, NULL, NULL, NULL,
13213 /* 4C */ NULL, NULL, NULL, NULL,
13214 /* 50 */ NULL, NULL, NULL, NULL,
13215 /* 54 */ NULL, NULL, NULL, NULL,
13216 /* 58 */ NULL, NULL, NULL, NULL,
13217 /* 5C */ NULL, NULL, NULL, NULL,
13218 /* 60 */ NULL, NULL, NULL, NULL,
13219 /* 64 */ NULL, NULL, NULL, NULL,
13220 /* 68 */ NULL, NULL, NULL, NULL,
13221 /* 6C */ NULL, NULL, NULL, NULL,
13222 /* 70 */ NULL, NULL, NULL, NULL,
13223 /* 74 */ NULL, NULL, NULL, NULL,
13224 /* 78 */ NULL, NULL, NULL, NULL,
13225 /* 7C */ NULL, NULL, NULL, NULL,
13226 /* 80 */ NULL, NULL, NULL, NULL,
13227 /* 84 */ NULL, NULL, NULL, NULL,
13228 /* 88 */ NULL, NULL, "pfnacc", NULL,
13229 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13230 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13231 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13232 /* 98 */ NULL, NULL, "pfsub", NULL,
13233 /* 9C */ NULL, NULL, "pfadd", NULL,
13234 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13235 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13236 /* A8 */ NULL, NULL, "pfsubr", NULL,
13237 /* AC */ NULL, NULL, "pfacc", NULL,
13238 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13239 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13240 /* B8 */ NULL, NULL, NULL, "pswapd",
13241 /* BC */ NULL, NULL, NULL, "pavgusb",
13242 /* C0 */ NULL, NULL, NULL, NULL,
13243 /* C4 */ NULL, NULL, NULL, NULL,
13244 /* C8 */ NULL, NULL, NULL, NULL,
13245 /* CC */ NULL, NULL, NULL, NULL,
13246 /* D0 */ NULL, NULL, NULL, NULL,
13247 /* D4 */ NULL, NULL, NULL, NULL,
13248 /* D8 */ NULL, NULL, NULL, NULL,
13249 /* DC */ NULL, NULL, NULL, NULL,
13250 /* E0 */ NULL, NULL, NULL, NULL,
13251 /* E4 */ NULL, NULL, NULL, NULL,
13252 /* E8 */ NULL, NULL, NULL, NULL,
13253 /* EC */ NULL, NULL, NULL, NULL,
13254 /* F0 */ NULL, NULL, NULL, NULL,
13255 /* F4 */ NULL, NULL, NULL, NULL,
13256 /* F8 */ NULL, NULL, NULL, NULL,
13257 /* FC */ NULL, NULL, NULL, NULL,
13258 };
13259
13260 static bool
13261 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13262 int sizeflag ATTRIBUTE_UNUSED)
13263 {
13264 const char *mnemonic;
13265
13266 if (!fetch_code (ins->info, ins->codep + 1))
13267 return false;
13268 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13269 place where an 8-bit immediate would normally go. ie. the last
13270 byte of the instruction. */
13271 ins->obufp = ins->mnemonicendp;
13272 mnemonic = Suffix3DNow[*ins->codep++];
13273 if (mnemonic)
13274 ins->obufp = stpcpy (ins->obufp, mnemonic);
13275 else
13276 {
13277 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13278 of the opcode (0x0f0f) and the opcode suffix, we need to do
13279 all the ins->modrm processing first, and don't know until now that
13280 we have a bad opcode. This necessitates some cleaning up. */
13281 ins->op_out[0][0] = '\0';
13282 ins->op_out[1][0] = '\0';
13283 BadOp (ins);
13284 }
13285 ins->mnemonicendp = ins->obufp;
13286 return true;
13287 }
13288
13289 static const struct op simd_cmp_op[] =
13290 {
13291 { STRING_COMMA_LEN ("eq") },
13292 { STRING_COMMA_LEN ("lt") },
13293 { STRING_COMMA_LEN ("le") },
13294 { STRING_COMMA_LEN ("unord") },
13295 { STRING_COMMA_LEN ("neq") },
13296 { STRING_COMMA_LEN ("nlt") },
13297 { STRING_COMMA_LEN ("nle") },
13298 { STRING_COMMA_LEN ("ord") }
13299 };
13300
13301 static const struct op vex_cmp_op[] =
13302 {
13303 { STRING_COMMA_LEN ("eq_uq") },
13304 { STRING_COMMA_LEN ("nge") },
13305 { STRING_COMMA_LEN ("ngt") },
13306 { STRING_COMMA_LEN ("false") },
13307 { STRING_COMMA_LEN ("neq_oq") },
13308 { STRING_COMMA_LEN ("ge") },
13309 { STRING_COMMA_LEN ("gt") },
13310 { STRING_COMMA_LEN ("true") },
13311 { STRING_COMMA_LEN ("eq_os") },
13312 { STRING_COMMA_LEN ("lt_oq") },
13313 { STRING_COMMA_LEN ("le_oq") },
13314 { STRING_COMMA_LEN ("unord_s") },
13315 { STRING_COMMA_LEN ("neq_us") },
13316 { STRING_COMMA_LEN ("nlt_uq") },
13317 { STRING_COMMA_LEN ("nle_uq") },
13318 { STRING_COMMA_LEN ("ord_s") },
13319 { STRING_COMMA_LEN ("eq_us") },
13320 { STRING_COMMA_LEN ("nge_uq") },
13321 { STRING_COMMA_LEN ("ngt_uq") },
13322 { STRING_COMMA_LEN ("false_os") },
13323 { STRING_COMMA_LEN ("neq_os") },
13324 { STRING_COMMA_LEN ("ge_oq") },
13325 { STRING_COMMA_LEN ("gt_oq") },
13326 { STRING_COMMA_LEN ("true_us") },
13327 };
13328
13329 static bool
13330 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13331 int sizeflag ATTRIBUTE_UNUSED)
13332 {
13333 unsigned int cmp_type;
13334
13335 if (!fetch_code (ins->info, ins->codep + 1))
13336 return false;
13337 cmp_type = *ins->codep++;
13338 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13339 {
13340 char suffix[3];
13341 char *p = ins->mnemonicendp - 2;
13342 suffix[0] = p[0];
13343 suffix[1] = p[1];
13344 suffix[2] = '\0';
13345 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13346 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13347 }
13348 else if (ins->need_vex
13349 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13350 {
13351 char suffix[3];
13352 char *p = ins->mnemonicendp - 2;
13353 suffix[0] = p[0];
13354 suffix[1] = p[1];
13355 suffix[2] = '\0';
13356 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13357 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13358 ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13359 }
13360 else
13361 {
13362 /* We have a reserved extension byte. Output it directly. */
13363 oappend_immediate (ins, cmp_type);
13364 }
13365 return true;
13366 }
13367
13368 static bool
13369 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13370 {
13371 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13372 if (!ins->intel_syntax)
13373 {
13374 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13375 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13376 if (bytemode == eBX_reg)
13377 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13378 ins->two_source_ops = true;
13379 }
13380 /* Skip mod/rm byte. */
13381 MODRM_CHECK;
13382 ins->codep++;
13383 return true;
13384 }
13385
13386 static bool
13387 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13388 int sizeflag ATTRIBUTE_UNUSED)
13389 {
13390 /* monitor %{e,r,}ax,%ecx,%edx" */
13391 if (!ins->intel_syntax)
13392 {
13393 const char (*names)[8] = (ins->address_mode == mode_64bit
13394 ? att_names64 : att_names32);
13395
13396 if (ins->prefixes & PREFIX_ADDR)
13397 {
13398 /* Remove "addr16/addr32". */
13399 ins->all_prefixes[ins->last_addr_prefix] = 0;
13400 names = (ins->address_mode != mode_32bit
13401 ? att_names32 : att_names16);
13402 ins->used_prefixes |= PREFIX_ADDR;
13403 }
13404 else if (ins->address_mode == mode_16bit)
13405 names = att_names16;
13406 strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13407 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13408 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13409 ins->two_source_ops = true;
13410 }
13411 /* Skip mod/rm byte. */
13412 MODRM_CHECK;
13413 ins->codep++;
13414 return true;
13415 }
13416
13417 static bool
13418 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13419 {
13420 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13421 lods and stos. */
13422 if (ins->prefixes & PREFIX_REPZ)
13423 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13424
13425 switch (bytemode)
13426 {
13427 case al_reg:
13428 case eAX_reg:
13429 case indir_dx_reg:
13430 return OP_IMREG (ins, bytemode, sizeflag);
13431 case eDI_reg:
13432 return OP_ESreg (ins, bytemode, sizeflag);
13433 case eSI_reg:
13434 return OP_DSreg (ins, bytemode, sizeflag);
13435 default:
13436 abort ();
13437 break;
13438 }
13439 return true;
13440 }
13441
13442 static bool
13443 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13444 int sizeflag ATTRIBUTE_UNUSED)
13445 {
13446 if (ins->isa64 != amd64)
13447 return true;
13448
13449 ins->obufp = ins->obuf;
13450 BadOp (ins);
13451 ins->mnemonicendp = ins->obufp;
13452 ++ins->codep;
13453 return true;
13454 }
13455
13456 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13457 "bnd". */
13458
13459 static bool
13460 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13461 int sizeflag ATTRIBUTE_UNUSED)
13462 {
13463 if (ins->prefixes & PREFIX_REPNZ)
13464 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13465 return true;
13466 }
13467
13468 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13469 "notrack". */
13470
13471 static bool
13472 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13473 int sizeflag ATTRIBUTE_UNUSED)
13474 {
13475 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13476 we've seen a PREFIX_DS. */
13477 if ((ins->prefixes & PREFIX_DS) != 0
13478 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13479 {
13480 /* NOTRACK prefix is only valid on indirect branch instructions.
13481 NB: DATA prefix is unsupported for Intel64. */
13482 ins->active_seg_prefix = 0;
13483 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13484 }
13485 return true;
13486 }
13487
13488 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13489 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13490 */
13491
13492 static bool
13493 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13494 {
13495 if (ins->modrm.mod != 3
13496 && (ins->prefixes & PREFIX_LOCK) != 0)
13497 {
13498 if (ins->prefixes & PREFIX_REPZ)
13499 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13500 if (ins->prefixes & PREFIX_REPNZ)
13501 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13502 }
13503
13504 return OP_E (ins, bytemode, sizeflag);
13505 }
13506
13507 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13508 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13509 */
13510
13511 static bool
13512 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13513 {
13514 if (ins->modrm.mod != 3)
13515 {
13516 if (ins->prefixes & PREFIX_REPZ)
13517 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13518 if (ins->prefixes & PREFIX_REPNZ)
13519 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13520 }
13521
13522 return OP_E (ins, bytemode, sizeflag);
13523 }
13524
13525 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13526 "xrelease" for memory operand. No check for LOCK prefix. */
13527
13528 static bool
13529 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13530 {
13531 if (ins->modrm.mod != 3
13532 && ins->last_repz_prefix > ins->last_repnz_prefix
13533 && (ins->prefixes & PREFIX_REPZ) != 0)
13534 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13535
13536 return OP_E (ins, bytemode, sizeflag);
13537 }
13538
13539 static bool
13540 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13541 {
13542 USED_REX (REX_W);
13543 if (ins->rex & REX_W)
13544 {
13545 /* Change cmpxchg8b to cmpxchg16b. */
13546 char *p = ins->mnemonicendp - 2;
13547 ins->mnemonicendp = stpcpy (p, "16b");
13548 bytemode = o_mode;
13549 }
13550 else if ((ins->prefixes & PREFIX_LOCK) != 0)
13551 {
13552 if (ins->prefixes & PREFIX_REPZ)
13553 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13554 if (ins->prefixes & PREFIX_REPNZ)
13555 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13556 }
13557
13558 return OP_M (ins, bytemode, sizeflag);
13559 }
13560
13561 static bool
13562 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13563 {
13564 const char (*names)[8] = att_names_xmm;
13565
13566 if (ins->need_vex)
13567 {
13568 switch (ins->vex.length)
13569 {
13570 case 128:
13571 break;
13572 case 256:
13573 names = att_names_ymm;
13574 break;
13575 default:
13576 abort ();
13577 }
13578 }
13579 oappend_register (ins, names[reg]);
13580 return true;
13581 }
13582
13583 static bool
13584 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13585 {
13586 /* Add proper suffix to "fxsave" and "fxrstor". */
13587 USED_REX (REX_W);
13588 if (ins->rex & REX_W)
13589 {
13590 char *p = ins->mnemonicendp;
13591 *p++ = '6';
13592 *p++ = '4';
13593 *p = '\0';
13594 ins->mnemonicendp = p;
13595 }
13596 return OP_M (ins, bytemode, sizeflag);
13597 }
13598
13599 /* Display the destination register operand for instructions with
13600 VEX. */
13601
13602 static bool
13603 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13604 {
13605 int reg, modrm_reg, sib_index = -1;
13606 const char (*names)[8];
13607
13608 if (!ins->need_vex)
13609 return true;
13610
13611 if (ins->evex_type == evex_from_legacy)
13612 {
13613 ins->evex_used |= EVEX_b_used;
13614 if (!ins->vex.nd)
13615 return true;
13616 }
13617
13618 reg = ins->vex.register_specifier;
13619 ins->vex.register_specifier = 0;
13620 if (ins->address_mode != mode_64bit)
13621 {
13622 if (ins->vex.evex && !ins->vex.v)
13623 {
13624 oappend (ins, "(bad)");
13625 return true;
13626 }
13627
13628 reg &= 7;
13629 }
13630 else if (ins->vex.evex && !ins->vex.v)
13631 reg += 16;
13632
13633 switch (bytemode)
13634 {
13635 case scalar_mode:
13636 oappend_register (ins, att_names_xmm[reg]);
13637 return true;
13638
13639 case vex_vsib_d_w_dq_mode:
13640 case vex_vsib_q_w_dq_mode:
13641 /* This must be the 3rd operand. */
13642 if (ins->obufp != ins->op_out[2])
13643 abort ();
13644 if (ins->vex.length == 128
13645 || (bytemode != vex_vsib_d_w_dq_mode
13646 && !ins->vex.w))
13647 oappend_register (ins, att_names_xmm[reg]);
13648 else
13649 oappend_register (ins, att_names_ymm[reg]);
13650
13651 /* All 3 XMM/YMM registers must be distinct. */
13652 modrm_reg = ins->modrm.reg;
13653 if (ins->rex & REX_R)
13654 modrm_reg += 8;
13655
13656 if (ins->has_sib && ins->modrm.rm == 4)
13657 {
13658 sib_index = ins->sib.index;
13659 if (ins->rex & REX_X)
13660 sib_index += 8;
13661 }
13662
13663 if (reg == modrm_reg || reg == sib_index)
13664 strcpy (ins->obufp, "/(bad)");
13665 if (modrm_reg == sib_index || modrm_reg == reg)
13666 strcat (ins->op_out[0], "/(bad)");
13667 if (sib_index == modrm_reg || sib_index == reg)
13668 strcat (ins->op_out[1], "/(bad)");
13669
13670 return true;
13671
13672 case tmm_mode:
13673 /* All 3 TMM registers must be distinct. */
13674 if (reg >= 8)
13675 oappend (ins, "(bad)");
13676 else
13677 {
13678 /* This must be the 3rd operand. */
13679 if (ins->obufp != ins->op_out[2])
13680 abort ();
13681 oappend_register (ins, att_names_tmm[reg]);
13682 if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13683 strcpy (ins->obufp, "/(bad)");
13684 }
13685
13686 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13687 || ins->modrm.rm == reg)
13688 {
13689 if (ins->modrm.reg <= 8
13690 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13691 strcat (ins->op_out[0], "/(bad)");
13692 if (ins->modrm.rm <= 8
13693 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13694 strcat (ins->op_out[1], "/(bad)");
13695 }
13696
13697 return true;
13698 }
13699
13700 switch (ins->vex.length)
13701 {
13702 case 128:
13703 switch (bytemode)
13704 {
13705 case x_mode:
13706 names = att_names_xmm;
13707 ins->evex_used |= EVEX_len_used;
13708 break;
13709 case v_mode:
13710 case dq_mode:
13711 if (ins->rex & REX_W)
13712 names = att_names64;
13713 else if (bytemode == v_mode
13714 && !(sizeflag & DFLAG))
13715 names = att_names16;
13716 else
13717 names = att_names32;
13718 break;
13719 case b_mode:
13720 names = att_names8rex;
13721 break;
13722 case q_mode:
13723 names = att_names64;
13724 break;
13725 case mask_bd_mode:
13726 case mask_mode:
13727 if (reg > 0x7)
13728 {
13729 oappend (ins, "(bad)");
13730 return true;
13731 }
13732 names = att_names_mask;
13733 break;
13734 default:
13735 abort ();
13736 return true;
13737 }
13738 break;
13739 case 256:
13740 switch (bytemode)
13741 {
13742 case x_mode:
13743 names = att_names_ymm;
13744 ins->evex_used |= EVEX_len_used;
13745 break;
13746 case mask_bd_mode:
13747 case mask_mode:
13748 if (reg <= 0x7)
13749 {
13750 names = att_names_mask;
13751 break;
13752 }
13753 /* Fall through. */
13754 default:
13755 /* See PR binutils/20893 for a reproducer. */
13756 oappend (ins, "(bad)");
13757 return true;
13758 }
13759 break;
13760 case 512:
13761 names = att_names_zmm;
13762 ins->evex_used |= EVEX_len_used;
13763 break;
13764 default:
13765 abort ();
13766 break;
13767 }
13768 oappend_register (ins, names[reg]);
13769 return true;
13770 }
13771
13772 static bool
13773 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13774 {
13775 if (ins->modrm.mod == 3)
13776 return OP_VEX (ins, bytemode, sizeflag);
13777 return true;
13778 }
13779
13780 static bool
13781 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13782 {
13783 OP_VEX (ins, bytemode, sizeflag);
13784
13785 if (ins->vex.w)
13786 {
13787 /* Swap 2nd and 3rd operands. */
13788 char *tmp = ins->op_out[2];
13789
13790 ins->op_out[2] = ins->op_out[1];
13791 ins->op_out[1] = tmp;
13792 }
13793 return true;
13794 }
13795
13796 static bool
13797 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13798 {
13799 int reg;
13800 const char (*names)[8] = att_names_xmm;
13801
13802 if (!fetch_code (ins->info, ins->codep + 1))
13803 return false;
13804 reg = *ins->codep++;
13805
13806 if (bytemode != x_mode && bytemode != scalar_mode)
13807 abort ();
13808
13809 reg >>= 4;
13810 if (ins->address_mode != mode_64bit)
13811 reg &= 7;
13812
13813 if (bytemode == x_mode && ins->vex.length == 256)
13814 names = att_names_ymm;
13815
13816 oappend_register (ins, names[reg]);
13817
13818 if (ins->vex.w)
13819 {
13820 /* Swap 3rd and 4th operands. */
13821 char *tmp = ins->op_out[3];
13822
13823 ins->op_out[3] = ins->op_out[2];
13824 ins->op_out[2] = tmp;
13825 }
13826 return true;
13827 }
13828
13829 static bool
13830 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13831 int sizeflag ATTRIBUTE_UNUSED)
13832 {
13833 oappend_immediate (ins, ins->codep[-1] & 0xf);
13834 return true;
13835 }
13836
13837 static bool
13838 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13839 int sizeflag ATTRIBUTE_UNUSED)
13840 {
13841 unsigned int cmp_type;
13842
13843 if (!ins->vex.evex)
13844 abort ();
13845
13846 if (!fetch_code (ins->info, ins->codep + 1))
13847 return false;
13848 cmp_type = *ins->codep++;
13849 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13850 If it's the case, print suffix, otherwise - print the immediate. */
13851 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13852 && cmp_type != 3
13853 && cmp_type != 7)
13854 {
13855 char suffix[3];
13856 char *p = ins->mnemonicendp - 2;
13857
13858 /* vpcmp* can have both one- and two-lettered suffix. */
13859 if (p[0] == 'p')
13860 {
13861 p++;
13862 suffix[0] = p[0];
13863 suffix[1] = '\0';
13864 }
13865 else
13866 {
13867 suffix[0] = p[0];
13868 suffix[1] = p[1];
13869 suffix[2] = '\0';
13870 }
13871
13872 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13873 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13874 }
13875 else
13876 {
13877 /* We have a reserved extension byte. Output it directly. */
13878 oappend_immediate (ins, cmp_type);
13879 }
13880 return true;
13881 }
13882
13883 static const struct op xop_cmp_op[] =
13884 {
13885 { STRING_COMMA_LEN ("lt") },
13886 { STRING_COMMA_LEN ("le") },
13887 { STRING_COMMA_LEN ("gt") },
13888 { STRING_COMMA_LEN ("ge") },
13889 { STRING_COMMA_LEN ("eq") },
13890 { STRING_COMMA_LEN ("neq") },
13891 { STRING_COMMA_LEN ("false") },
13892 { STRING_COMMA_LEN ("true") }
13893 };
13894
13895 static bool
13896 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13897 int sizeflag ATTRIBUTE_UNUSED)
13898 {
13899 unsigned int cmp_type;
13900
13901 if (!fetch_code (ins->info, ins->codep + 1))
13902 return false;
13903 cmp_type = *ins->codep++;
13904 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13905 {
13906 char suffix[3];
13907 char *p = ins->mnemonicendp - 2;
13908
13909 /* vpcom* can have both one- and two-lettered suffix. */
13910 if (p[0] == 'm')
13911 {
13912 p++;
13913 suffix[0] = p[0];
13914 suffix[1] = '\0';
13915 }
13916 else
13917 {
13918 suffix[0] = p[0];
13919 suffix[1] = p[1];
13920 suffix[2] = '\0';
13921 }
13922
13923 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13924 ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13925 }
13926 else
13927 {
13928 /* We have a reserved extension byte. Output it directly. */
13929 oappend_immediate (ins, cmp_type);
13930 }
13931 return true;
13932 }
13933
13934 static const struct op pclmul_op[] =
13935 {
13936 { STRING_COMMA_LEN ("lql") },
13937 { STRING_COMMA_LEN ("hql") },
13938 { STRING_COMMA_LEN ("lqh") },
13939 { STRING_COMMA_LEN ("hqh") }
13940 };
13941
13942 static bool
13943 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13944 int sizeflag ATTRIBUTE_UNUSED)
13945 {
13946 unsigned int pclmul_type;
13947
13948 if (!fetch_code (ins->info, ins->codep + 1))
13949 return false;
13950 pclmul_type = *ins->codep++;
13951 switch (pclmul_type)
13952 {
13953 case 0x10:
13954 pclmul_type = 2;
13955 break;
13956 case 0x11:
13957 pclmul_type = 3;
13958 break;
13959 default:
13960 break;
13961 }
13962 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13963 {
13964 char suffix[4];
13965 char *p = ins->mnemonicendp - 3;
13966 suffix[0] = p[0];
13967 suffix[1] = p[1];
13968 suffix[2] = p[2];
13969 suffix[3] = '\0';
13970 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13971 ins->mnemonicendp += pclmul_op[pclmul_type].len;
13972 }
13973 else
13974 {
13975 /* We have a reserved extension byte. Output it directly. */
13976 oappend_immediate (ins, pclmul_type);
13977 }
13978 return true;
13979 }
13980
13981 static bool
13982 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13983 {
13984 /* Add proper suffix to "movsxd". */
13985 char *p = ins->mnemonicendp;
13986
13987 switch (bytemode)
13988 {
13989 case movsxd_mode:
13990 if (!ins->intel_syntax)
13991 {
13992 USED_REX (REX_W);
13993 if (ins->rex & REX_W)
13994 {
13995 *p++ = 'l';
13996 *p++ = 'q';
13997 break;
13998 }
13999 }
14000
14001 *p++ = 'x';
14002 *p++ = 'd';
14003 break;
14004 default:
14005 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
14006 break;
14007 }
14008
14009 ins->mnemonicendp = p;
14010 *p = '\0';
14011 return OP_E (ins, bytemode, sizeflag);
14012 }
14013
14014 static bool
14015 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
14016 {
14017 unsigned int reg = ins->vex.register_specifier;
14018 unsigned int modrm_reg = ins->modrm.reg;
14019 unsigned int modrm_rm = ins->modrm.rm;
14020
14021 /* Calc destination register number. */
14022 if (ins->rex & REX_R)
14023 modrm_reg += 8;
14024 if (ins->rex2 & REX_R)
14025 modrm_reg += 16;
14026
14027 /* Calc src1 register number. */
14028 if (ins->address_mode != mode_64bit)
14029 reg &= 7;
14030 else if (ins->vex.evex && !ins->vex.v)
14031 reg += 16;
14032
14033 /* Calc src2 register number. */
14034 if (ins->modrm.mod == 3)
14035 {
14036 if (ins->rex & REX_B)
14037 modrm_rm += 8;
14038 if (ins->rex & REX_X)
14039 modrm_rm += 16;
14040 }
14041
14042 /* Destination and source registers must be distinct, output bad if
14043 dest == src1 or dest == src2. */
14044 if (modrm_reg == reg
14045 || (ins->modrm.mod == 3
14046 && modrm_reg == modrm_rm))
14047 {
14048 oappend (ins, "(bad)");
14049 return true;
14050 }
14051 return OP_XMM (ins, bytemode, sizeflag);
14052 }
14053
14054 static bool
14055 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14056 {
14057 if (ins->modrm.mod != 3 || !ins->vex.b)
14058 return true;
14059
14060 switch (bytemode)
14061 {
14062 case evex_rounding_64_mode:
14063 if (ins->address_mode != mode_64bit || !ins->vex.w)
14064 return true;
14065 /* Fall through. */
14066 case evex_rounding_mode:
14067 ins->evex_used |= EVEX_b_used;
14068 oappend (ins, names_rounding[ins->vex.ll]);
14069 break;
14070 case evex_sae_mode:
14071 ins->evex_used |= EVEX_b_used;
14072 oappend (ins, "{");
14073 break;
14074 default:
14075 abort ();
14076 }
14077 oappend (ins, "sae}");
14078 return true;
14079 }
14080
14081 static bool
14082 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14083 {
14084 if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14085 {
14086 if (ins->intel_syntax)
14087 {
14088 ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
14089 }
14090 else
14091 {
14092 USED_REX (REX_W);
14093 if (ins->rex & REX_W)
14094 ins->mnemonicendp = stpcpy (ins->obuf, "nopq ");
14095 else
14096 {
14097 if (sizeflag & DFLAG)
14098 ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
14099 else
14100 ins->mnemonicendp = stpcpy (ins->obuf, "nopw ");
14101 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14102 }
14103 }
14104 bytemode = v_mode;
14105 }
14106
14107 return OP_M (ins, bytemode, sizeflag);
14108 }
14109
14110 static bool
14111 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
14112 {
14113 if (ins->modrm.mod != 3)
14114 return true;
14115
14116 unsigned int vvvv_reg = ins->vex.register_specifier
14117 | (!ins->vex.v << 4);
14118 unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
14119 + (ins->rex2 & REX_B ? 16 : 0);
14120
14121 /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */
14122 if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
14123 || (!ins->modrm.reg
14124 && vvvv_reg == rm_reg))
14125 {
14126 oappend (ins, "(bad)");
14127 return true;
14128 }
14129
14130 return OP_VEX (ins, bytemode, sizeflag);
14131 }
14132
14133 static bool
14134 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
14135 {
14136 if (ins->last_rex2_prefix >= 0)
14137 {
14138 uint64_t op;
14139
14140 if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
14141 || (ins->rex & REX_W) != 0x0)
14142 {
14143 oappend (ins, "(bad)");
14144 return true;
14145 }
14146
14147 if (bytemode == eAX_reg)
14148 return true;
14149
14150 if (!get64 (ins, &op))
14151 return false;
14152
14153 ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
14154 ins->rex2 |= REX2_SPECIAL;
14155 oappend_immediate (ins, op);
14156
14157 return true;
14158 }
14159
14160 if (bytemode == eAX_reg)
14161 return OP_IMREG (ins, bytemode, sizeflag);
14162 return OP_OFF64 (ins, bytemode, sizeflag);
14163 }
14164
14165 static bool
14166 CFCMOV_Fixup (instr_info *ins, int opnd, int sizeflag)
14167 {
14168 /* EVEX.NF is used as a direction bit in the 2-operand case to reverse the
14169 source and destination operands. */
14170 bool dstmem = !ins->vex.nd && ins->vex.nf;
14171
14172 if (opnd == 0)
14173 {
14174 if (dstmem)
14175 return OP_E (ins, v_swap_mode, sizeflag);
14176 return OP_G (ins, v_mode, sizeflag);
14177 }
14178
14179 /* These bits have been consumed and should be cleared. */
14180 ins->vex.nf = false;
14181 ins->vex.mask_register_specifier = 0;
14182
14183 if (dstmem)
14184 return OP_G (ins, v_mode, sizeflag);
14185 return OP_E (ins, v_mode, sizeflag);
14186 }
The GNU Binutils are a collection of binary tools.