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2007-01-04 Paolo Bonzini <bonzini@gnu.org>
[binutils.git] / gas / config / tc-m32c.c
blob87ccd6978017399f846a3e3c08766a553b17ac66
1 /* tc-m32c.c -- Assembler for the Renesas M32C.
2 Copyright (C) 2005, 2006 Free Software Foundation.
3 Contributed by RedHat.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "as.h"
23 #include "subsegs.h"
24 #include "symcat.h"
25 #include "opcodes/m32c-desc.h"
26 #include "opcodes/m32c-opc.h"
27 #include "cgen.h"
28 #include "elf/common.h"
29 #include "elf/m32c.h"
30 #include "libbfd.h"
31 #include "safe-ctype.h"
32
33 /* Structure to hold all of the different components
34 describing an individual instruction. */
35 typedef struct
36 {
37 const CGEN_INSN * insn;
38 const CGEN_INSN * orig_insn;
39 CGEN_FIELDS fields;
40 #if CGEN_INT_INSN_P
41 CGEN_INSN_INT buffer [1];
42 #define INSN_VALUE(buf) (*(buf))
43 #else
44 unsigned char buffer [CGEN_MAX_INSN_SIZE];
45 #define INSN_VALUE(buf) (buf)
46 #endif
47 char * addr;
48 fragS * frag;
49 int num_fixups;
50 fixS * fixups [GAS_CGEN_MAX_FIXUPS];
51 int indices [MAX_OPERAND_INSTANCES];
52 }
53 m32c_insn;
54
55 #define rl_for(insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&(insn.insn->base->attrs)))
56 #define relaxable(insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&(insn.insn->base->attrs)))
57
58 const char comment_chars[] = ";";
59 const char line_comment_chars[] = "#";
60 const char line_separator_chars[] = "|";
61 const char EXP_CHARS[] = "eE";
62 const char FLT_CHARS[] = "dD";
63 \f
64 #define M32C_SHORTOPTS ""
65 const char * md_shortopts = M32C_SHORTOPTS;
66
67 /* assembler options */
68 #define OPTION_CPU_M16C (OPTION_MD_BASE)
69 #define OPTION_CPU_M32C (OPTION_MD_BASE + 1)
70 #define OPTION_LINKRELAX (OPTION_MD_BASE + 2)
71
72 struct option md_longopts[] =
73 {
74 { "m16c", no_argument, NULL, OPTION_CPU_M16C },
75 { "m32c", no_argument, NULL, OPTION_CPU_M32C },
76 { "relax", no_argument, NULL, OPTION_LINKRELAX },
77 {NULL, no_argument, NULL, 0}
78 };
79 size_t md_longopts_size = sizeof (md_longopts);
80
81 /* Default machine */
82
83 #define DEFAULT_MACHINE bfd_mach_m16c
84 #define DEFAULT_FLAGS EF_M32C_CPU_M16C
85
86 static unsigned long m32c_mach = bfd_mach_m16c;
87 static int cpu_mach = (1 << MACH_M16C);
88 static int insn_size;
89 static int m32c_relax = 0;
90
91 /* Flags to set in the elf header */
92 static flagword m32c_flags = DEFAULT_FLAGS;
93
94 static char default_isa = 1 << (7 - ISA_M16C);
95 static CGEN_BITSET m32c_isa = {1, & default_isa};
96
97 static void
98 set_isa (enum isa_attr isa_num)
99 {
100 cgen_bitset_set (& m32c_isa, isa_num);
101 }
102
103 static void s_bss (int);
104
105 int
106 md_parse_option (int c, char * arg ATTRIBUTE_UNUSED)
107 {
108 switch (c)
109 {
110 case OPTION_CPU_M16C:
111 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C;
112 m32c_mach = bfd_mach_m16c;
113 cpu_mach = (1 << MACH_M16C);
114 set_isa (ISA_M16C);
115 break;
116
117 case OPTION_CPU_M32C:
118 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C;
119 m32c_mach = bfd_mach_m32c;
120 cpu_mach = (1 << MACH_M32C);
121 set_isa (ISA_M32C);
122 break;
123
124 case OPTION_LINKRELAX:
125 m32c_relax = 1;
126 break;
127
128 default:
129 return 0;
130 }
131 return 1;
132 }
133
134 void
135 md_show_usage (FILE * stream)
136 {
137 fprintf (stream, _(" M32C specific command line options:\n"));
138 }
139
140 static void
141 s_bss (int ignore ATTRIBUTE_UNUSED)
142 {
143 int temp;
144
145 temp = get_absolute_expression ();
146 subseg_set (bss_section, (subsegT) temp);
147 demand_empty_rest_of_line ();
148 }
149
150 /* The target specific pseudo-ops which we support. */
151 const pseudo_typeS md_pseudo_table[] =
152 {
153 { "bss", s_bss, 0},
154 { "word", cons, 4 },
155 { NULL, NULL, 0 }
156 };
157
158 \f
159 void
160 md_begin (void)
161 {
162 /* Initialize the `cgen' interface. */
163
164 /* Set the machine number and endian. */
165 gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
166 CGEN_CPU_OPEN_ENDIAN,
167 CGEN_ENDIAN_BIG,
168 CGEN_CPU_OPEN_ISAS, & m32c_isa,
169 CGEN_CPU_OPEN_END);
170
171 m32c_cgen_init_asm (gas_cgen_cpu_desc);
172
173 /* This is a callback from cgen to gas to parse operands. */
174 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
175
176 /* Set the ELF flags if desired. */
177 if (m32c_flags)
178 bfd_set_private_flags (stdoutput, m32c_flags);
179
180 /* Set the machine type */
181 bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach);
182
183 insn_size = 0;
184 }
185
186 void
187 m32c_md_end (void)
188 {
189 int i, n_nops;
190
191 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
192 {
193 /* Pad with nops for objdump. */
194 n_nops = (32 - ((insn_size) % 32)) / 8;
195 for (i = 1; i <= n_nops; i++)
196 md_assemble ("nop");
197 }
198 }
199
200 void
201 m32c_start_line_hook (void)
202 {
203 #if 0 /* not necessary....handled in the .cpu file */
204 char *s = input_line_pointer;
205 char *sg;
206
207 for (s = input_line_pointer ; s && s[0] != '\n'; s++)
208 {
209 if (s[0] == ':')
210 {
211 /* Remove :g suffix. Squeeze out blanks. */
212 if (s[1] == 'g')
213 {
214 for (sg = s - 1; sg && sg >= input_line_pointer; sg--)
215 {
216 sg[2] = sg[0];
217 }
218 sg[1] = ' ';
219 sg[2] = ' ';
220 input_line_pointer += 2;
221 }
222 }
223 }
224 #endif
225 }
226
227 /* Process [[indirect-operands]] in instruction str. */
228
229 static bfd_boolean
230 m32c_indirect_operand (char *str)
231 {
232 char *new_str;
233 char *s;
234 char *ns;
235 int ns_len;
236 char *ns_end;
237 enum indirect_type {none, relative, absolute} ;
238 enum indirect_type indirection [3] = { none, none, none };
239 int brace_n [3] = { 0, 0, 0 };
240 int operand;
241
242 s = str;
243 operand = 1;
244 for (s = str; *s; s++)
245 {
246 if (s[0] == ',')
247 operand = 2;
248 /* [abs] where abs is not a0 or a1 */
249 if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1'))
250 && (ISBLANK (s[0]) || s[0] == ','))
251 indirection[operand] = absolute;
252 if (s[0] == ']' && s[1] == ']')
253 indirection[operand] = relative;
254 if (s[0] == '[' && s[1] == '[')
255 indirection[operand] = relative;
256 }
257
258 if (indirection[1] == none && indirection[2] == none)
259 return FALSE;
260
261 operand = 1;
262 ns_len = strlen (str);
263 new_str = (char*) xmalloc (ns_len);
264 ns = new_str;
265 ns_end = ns + ns_len;
266
267 for (s = str; *s; s++)
268 {
269 if (s[0] == ',')
270 operand = 2;
271
272 if (s[0] == '[' && ! brace_n[operand])
273 {
274 brace_n[operand] += 1;
275 /* Squeeze [[ to [ if this is an indirect operand. */
276 if (indirection[operand] != none)
277 continue;
278 }
279
280 else if (s[0] == '[' && brace_n[operand])
281 {
282 brace_n[operand] += 1;
283 }
284 else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative)
285 {
286 s += 1; /* skip one ]. */
287 brace_n[operand] -= 2; /* allow for 2 [. */
288 }
289 else if (s[0] == ']' && indirection[operand] == absolute)
290 {
291 brace_n[operand] -= 1;
292 continue; /* skip closing ]. */
293 }
294 else if (s[0] == ']')
295 {
296 brace_n[operand] -= 1;
297 }
298 *ns = s[0];
299 ns += 1;
300 if (ns >= ns_end)
301 return FALSE;
302 if (s[0] == 0)
303 break;
304 }
305 *ns = '\0';
306 for (operand = 1; operand <= 2; operand++)
307 if (brace_n[operand])
308 {
309 fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]);
310 }
311
312 if (indirection[1] != none && indirection[2] != none)
313 md_assemble ("src-dest-indirect");
314 else if (indirection[1] != none)
315 md_assemble ("src-indirect");
316 else if (indirection[2] != none)
317 md_assemble ("dest-indirect");
318
319 md_assemble (new_str);
320 free (new_str);
321 return TRUE;
322 }
323
324 void
325 md_assemble (char * str)
326 {
327 static int last_insn_had_delay_slot = 0;
328 m32c_insn insn;
329 char * errmsg;
330 finished_insnS results;
331 int rl_type;
332
333 if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str))
334 return;
335
336 /* Initialize GAS's cgen interface for a new instruction. */
337 gas_cgen_init_parse ();
338
339 insn.insn = m32c_cgen_assemble_insn
340 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
341
342 if (!insn.insn)
343 {
344 as_bad ("%s", errmsg);
345 return;
346 }
347
348 results.num_fixups = 0;
349 /* Doesn't really matter what we pass for RELAX_P here. */
350 gas_cgen_finish_insn (insn.insn, insn.buffer,
351 CGEN_FIELDS_BITSIZE (& insn.fields), 1, &results);
352
353 last_insn_had_delay_slot
354 = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
355 insn_size = CGEN_INSN_BITSIZE(insn.insn);
356
357 rl_type = rl_for (insn);
358
359 /* We have to mark all the jumps, because we need to adjust them
360 when we delete bytes, but we only need to mark the displacements
361 if they're symbolic - if they're not, we've already picked the
362 shortest opcode by now. The linker, however, will still have to
363 check any operands to see if they're the displacement type, since
364 we don't know (nor record) *which* operands are relaxable. */
365 if (m32c_relax
366 && rl_type != RL_TYPE_NONE
367 && (rl_type == RL_TYPE_JUMP || results.num_fixups)
368 && !relaxable (insn))
369 {
370 int reloc = 0;
371 int addend = results.num_fixups + 16 * insn_size/8;
372
373 switch (rl_for (insn))
374 {
375 case RL_TYPE_JUMP: reloc = BFD_RELOC_M32C_RL_JUMP; break;
376 case RL_TYPE_1ADDR: reloc = BFD_RELOC_M32C_RL_1ADDR; break;
377 case RL_TYPE_2ADDR: reloc = BFD_RELOC_M32C_RL_2ADDR; break;
378 }
379 if (insn.insn->base->num == M32C_INSN_JMP16_S
380 || insn.insn->base->num == M32C_INSN_JMP32_S)
381 addend = 0x10;
382
383 fix_new (results.frag,
384 results.addr - results.frag->fr_literal,
385 0, abs_section_sym, addend, 0,
386 reloc);
387 }
388 }
389
390 /* The syntax in the manual says constants begin with '#'.
391 We just ignore it. */
392
393 void
394 md_operand (expressionS * exp)
395 {
396 /* In case of a syntax error, escape back to try next syntax combo. */
397 if (exp->X_op == O_absent)
398 gas_cgen_md_operand (exp);
399 }
400
401 valueT
402 md_section_align (segT segment, valueT size)
403 {
404 int align = bfd_get_section_alignment (stdoutput, segment);
405 return ((size + (1 << align) - 1) & (-1 << align));
406 }
407
408 symbolS *
409 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
410 {
411 return 0;
412 }
413 \f
414 const relax_typeS md_relax_table[] =
415 {
416 /* The fields are:
417 1) most positive reach of this state,
418 2) most negative reach of this state,
419 3) how many bytes this mode will have in the variable part of the frag
420 4) which index into the table to try if we can't fit into this one. */
421
422 /* 0 */ { 0, 0, 0, 0 }, /* unused */
423 /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
424
425 /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */
426 /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */
427 /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */
428
429 /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */
430 /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */
431 /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */
432
433 /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */
434 /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */
435 /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */
436 /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */
437
438 /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */
439 /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */
440 /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */
441
442 /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */
443 /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */
444 /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */
445 /* 18 */ { 0, 0, 4, 0 }, /* jmp32.a */
446
447 /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */
448 /* 20 */ { 0, 0, 4, 0 }, /* jsr16.a */
449 /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */
450 /* 22 */ { 0, 0, 4, 0 } /* jsr32.a */
451 };
452
453 enum {
454 M32C_MACRO_JCND16_5_W,
455 M32C_MACRO_JCND16_5_A,
456 M32C_MACRO_JCND16_W,
457 M32C_MACRO_JCND16_A,
458 M32C_MACRO_JCND32_W,
459 M32C_MACRO_JCND32_A,
460 } M32C_Macros;
461
462 static struct {
463 int insn;
464 int bytes;
465 int insn_for_extern;
466 int pcrel_aim_offset;
467 } subtype_mappings[] = {
468 /* 0 */ { 0, 0, 0, 0 },
469 /* 1 */ { 0, 0, 0, 0 },
470
471 /* 2 */ { M32C_INSN_JCND16_5, 2, -M32C_MACRO_JCND16_5_A, 1 },
472 /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 },
473 /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 },
474
475 /* 5 */ { M32C_INSN_JCND16, 3, -M32C_MACRO_JCND16_A, 1 },
476 /* 6 */ { -M32C_MACRO_JCND16_W, 6, -M32C_MACRO_JCND16_A, 4 },
477 /* 7 */ { -M32C_MACRO_JCND16_A, 7, -M32C_MACRO_JCND16_A, 0 },
478
479 /* 8 */ { M32C_INSN_JMP16_S, 1, M32C_INSN_JMP16_A, 0 },
480 /* 9 */ { M32C_INSN_JMP16_B, 2, M32C_INSN_JMP16_A, 1 },
481 /* 10 */ { M32C_INSN_JMP16_W, 3, M32C_INSN_JMP16_A, 2 },
482 /* 11 */ { M32C_INSN_JMP16_A, 4, M32C_INSN_JMP16_A, 0 },
483
484 /* 12 */ { M32C_INSN_JCND32, 2, -M32C_MACRO_JCND32_A, 1 },
485 /* 13 */ { -M32C_MACRO_JCND32_W, 5, -M32C_MACRO_JCND32_A, 4 },
486 /* 14 */ { -M32C_MACRO_JCND32_A, 6, -M32C_MACRO_JCND32_A, 0 },
487
488 /* 15 */ { M32C_INSN_JMP32_S, 1, M32C_INSN_JMP32_A, 0 },
489 /* 16 */ { M32C_INSN_JMP32_B, 2, M32C_INSN_JMP32_A, 1 },
490 /* 17 */ { M32C_INSN_JMP32_W, 3, M32C_INSN_JMP32_A, 2 },
491 /* 18 */ { M32C_INSN_JMP32_A, 4, M32C_INSN_JMP32_A, 0 },
492
493 /* 19 */ { M32C_INSN_JSR16_W, 3, M32C_INSN_JSR16_A, 2 },
494 /* 20 */ { M32C_INSN_JSR16_A, 4, M32C_INSN_JSR16_A, 0 },
495 /* 21 */ { M32C_INSN_JSR32_W, 3, M32C_INSN_JSR32_A, 2 },
496 /* 22 */ { M32C_INSN_JSR32_A, 4, M32C_INSN_JSR32_A, 0 }
497 };
498 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
499
500 void
501 m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
502 {
503 symbolS *symbolP = fragP->fr_symbol;
504 if (symbolP && !S_IS_DEFINED (symbolP))
505 *aim = 0;
506 /* Adjust for m32c pcrel not being relative to the next opcode. */
507 *aim += subtype_mappings[this_state].pcrel_aim_offset;
508 }
509
510 static int
511 insn_to_subtype (int insn)
512 {
513 unsigned int i;
514 for (i=0; i<NUM_MAPPINGS; i++)
515 if (insn == subtype_mappings[i].insn)
516 {
517 /*printf("mapping %d used\n", i);*/
518 return i;
519 }
520 abort ();
521 }
522
523 /* Return an initial guess of the length by which a fragment must grow to
524 hold a branch to reach its destination.
525 Also updates fr_type/fr_subtype as necessary.
526
527 Called just before doing relaxation.
528 Any symbol that is now undefined will not become defined.
529 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
530 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
531 Although it may not be explicit in the frag, pretend fr_var starts with a
532 0 value. */
533
534 int
535 md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED)
536 {
537 int where = fragP->fr_opcode - fragP->fr_literal;
538
539 if (fragP->fr_subtype == 1)
540 fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
541
542 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
543 {
544 int new_insn;
545
546 new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
547 fragP->fr_subtype = insn_to_subtype (new_insn);
548 }
549
550 if (fragP->fr_cgen.insn->base
551 && fragP->fr_cgen.insn->base->num
552 != subtype_mappings[fragP->fr_subtype].insn
553 && subtype_mappings[fragP->fr_subtype].insn > 0)
554 {
555 int new_insn= subtype_mappings[fragP->fr_subtype].insn;
556 if (new_insn >= 0)
557 {
558 fragP->fr_cgen.insn = (fragP->fr_cgen.insn
559 - fragP->fr_cgen.insn->base->num
560 + new_insn);
561 }
562 }
563
564 return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where);
565 }
566
567 /* *fragP has been relaxed to its final size, and now needs to have
568 the bytes inside it modified to conform to the new size.
569
570 Called after relaxation is finished.
571 fragP->fr_type == rs_machine_dependent.
572 fragP->fr_subtype is the subtype of what the address relaxed to. */
573
574 static int
575 target_address_for (fragS *frag)
576 {
577 int rv = frag->fr_offset;
578 symbolS *sym = frag->fr_symbol;
579
580 if (sym)
581 rv += S_GET_VALUE (sym);
582
583 /*printf("target_address_for returns %d\n", rv);*/
584 return rv;
585 }
586
587 void
588 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
589 segT sec ATTRIBUTE_UNUSED,
590 fragS * fragP ATTRIBUTE_UNUSED)
591 {
592 int addend;
593 int operand;
594 int new_insn;
595 int where = fragP->fr_opcode - fragP->fr_literal;
596 int rl_where = fragP->fr_opcode - fragP->fr_literal;
597 unsigned char *op = (unsigned char *)fragP->fr_opcode;
598 int op_base = 0;
599 int op_op = 0;
600 int rl_addend = 0;
601
602 addend = target_address_for (fragP) - (fragP->fr_address + where);
603 new_insn = subtype_mappings[fragP->fr_subtype].insn;
604
605 fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes;
606
607 op_base = 0;
608
609 switch (subtype_mappings[fragP->fr_subtype].insn)
610 {
611 case M32C_INSN_JCND16_5:
612 op[1] = addend - 1;
613 operand = M32C_OPERAND_LAB_8_8;
614 op_op = 1;
615 rl_addend = 0x21;
616 break;
617
618 case -M32C_MACRO_JCND16_5_W:
619 op[0] ^= 0x04;
620 op[1] = 4;
621 op[2] = 0xf4;
622 op[3] = addend - 3;
623 op[4] = (addend - 3) >> 8;
624 operand = M32C_OPERAND_LAB_8_16;
625 where += 2;
626 new_insn = M32C_INSN_JMP16_W;
627 op_base = 2;
628 op_op = 3;
629 rl_addend = 0x51;
630 break;
631
632 case -M32C_MACRO_JCND16_5_A:
633 op[0] ^= 0x04;
634 op[1] = 5;
635 op[2] = 0xfc;
636 operand = M32C_OPERAND_LAB_8_24;
637 where += 2;
638 new_insn = M32C_INSN_JMP16_A;
639 op_base = 2;
640 op_op = 3;
641 rl_addend = 0x61;
642 break;
643
644
645 case M32C_INSN_JCND16:
646 op[2] = addend - 2;
647 operand = M32C_OPERAND_LAB_16_8;
648 op_base = 0;
649 op_op = 2;
650 rl_addend = 0x31;
651 break;
652
653 case -M32C_MACRO_JCND16_W:
654 op[1] ^= 0x04;
655 op[2] = 4;
656 op[3] = 0xf4;
657 op[4] = addend - 4;
658 op[5] = (addend - 4) >> 8;
659 operand = M32C_OPERAND_LAB_8_16;
660 where += 3;
661 new_insn = M32C_INSN_JMP16_W;
662 op_base = 3;
663 op_op = 4;
664 rl_addend = 0x61;
665 break;
666
667 case -M32C_MACRO_JCND16_A:
668 op[1] ^= 0x04;
669 op[2] = 5;
670 op[3] = 0xfc;
671 operand = M32C_OPERAND_LAB_8_24;
672 where += 3;
673 new_insn = M32C_INSN_JMP16_A;
674 op_base = 3;
675 op_op = 4;
676 rl_addend = 0x71;
677 break;
678
679 case M32C_INSN_JMP16_S:
680 op[0] = 0x60 | ((addend-2) & 0x07);
681 operand = M32C_OPERAND_LAB_5_3;
682 op_base = 0;
683 op_op = 0;
684 rl_addend = 0x10;
685 break;
686
687 case M32C_INSN_JMP16_B:
688 op[0] = 0xfe;
689 op[1] = addend - 1;
690 operand = M32C_OPERAND_LAB_8_8;
691 op_base = 0;
692 op_op = 1;
693 rl_addend = 0x21;
694 break;
695
696 case M32C_INSN_JMP16_W:
697 op[0] = 0xf4;
698 op[1] = addend - 1;
699 op[2] = (addend - 1) >> 8;
700 operand = M32C_OPERAND_LAB_8_16;
701 op_base = 0;
702 op_op = 1;
703 rl_addend = 0x31;
704 break;
705
706 case M32C_INSN_JMP16_A:
707 op[0] = 0xfc;
708 op[1] = 0;
709 op[2] = 0;
710 op[3] = 0;
711 operand = M32C_OPERAND_LAB_8_24;
712 op_base = 0;
713 op_op = 1;
714 rl_addend = 0x41;
715 break;
716
717 case M32C_INSN_JCND32:
718 op[1] = addend - 1;
719 operand = M32C_OPERAND_LAB_8_8;
720 op_base = 0;
721 op_op = 1;
722 rl_addend = 0x21;
723 break;
724
725 case -M32C_MACRO_JCND32_W:
726 op[0] ^= 0x40;
727 op[1] = 4;
728 op[2] = 0xce;
729 op[3] = addend - 3;
730 op[4] = (addend - 3) >> 8;
731 operand = M32C_OPERAND_LAB_8_16;
732 where += 2;
733 new_insn = M32C_INSN_JMP32_W;
734 op_base = 2;
735 op_op = 3;
736 rl_addend = 0x51;
737 break;
738
739 case -M32C_MACRO_JCND32_A:
740 op[0] ^= 0x40;
741 op[1] = 5;
742 op[2] = 0xcc;
743 operand = M32C_OPERAND_LAB_8_24;
744 where += 2;
745 new_insn = M32C_INSN_JMP32_A;
746 op_base = 2;
747 op_op = 3;
748 rl_addend = 0x61;
749 break;
750
751
752
753 case M32C_INSN_JMP32_S:
754 addend = ((addend-2) & 0x07);
755 op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30);
756 operand = M32C_OPERAND_LAB32_JMP_S;
757 op_base = 0;
758 op_op = 0;
759 rl_addend = 0x10;
760 break;
761
762 case M32C_INSN_JMP32_B:
763 op[0] = 0xbb;
764 op[1] = addend - 1;
765 operand = M32C_OPERAND_LAB_8_8;
766 op_base = 0;
767 op_op = 1;
768 rl_addend = 0x21;
769 break;
770
771 case M32C_INSN_JMP32_W:
772 op[0] = 0xce;
773 op[1] = addend - 1;
774 op[2] = (addend - 1) >> 8;
775 operand = M32C_OPERAND_LAB_8_16;
776 op_base = 0;
777 op_op = 1;
778 rl_addend = 0x31;
779 break;
780
781 case M32C_INSN_JMP32_A:
782 op[0] = 0xcc;
783 op[1] = 0;
784 op[2] = 0;
785 op[3] = 0;
786 operand = M32C_OPERAND_LAB_8_24;
787 op_base = 0;
788 op_op = 1;
789 rl_addend = 0x41;
790 break;
791
792
793 case M32C_INSN_JSR16_W:
794 op[0] = 0xf5;
795 op[1] = addend - 1;
796 op[2] = (addend - 1) >> 8;
797 operand = M32C_OPERAND_LAB_8_16;
798 op_base = 0;
799 op_op = 1;
800 rl_addend = 0x31;
801 break;
802
803 case M32C_INSN_JSR16_A:
804 op[0] = 0xfd;
805 op[1] = 0;
806 op[2] = 0;
807 op[3] = 0;
808 operand = M32C_OPERAND_LAB_8_24;
809 op_base = 0;
810 op_op = 1;
811 rl_addend = 0x41;
812 break;
813
814 case M32C_INSN_JSR32_W:
815 op[0] = 0xcf;
816 op[1] = addend - 1;
817 op[2] = (addend - 1) >> 8;
818 operand = M32C_OPERAND_LAB_8_16;
819 op_base = 0;
820 op_op = 1;
821 rl_addend = 0x31;
822 break;
823
824 case M32C_INSN_JSR32_A:
825 op[0] = 0xcd;
826 op[1] = 0;
827 op[2] = 0;
828 op[3] = 0;
829 operand = M32C_OPERAND_LAB_8_24;
830 op_base = 0;
831 op_op = 1;
832 rl_addend = 0x41;
833 break;
834
835
836
837 default:
838 printf("\nHey! Need more opcode converters! missing: %d %s\n\n",
839 fragP->fr_subtype,
840 fragP->fr_cgen.insn->base->name);
841 abort();
842 }
843
844 if (m32c_relax)
845 {
846 if (operand != M32C_OPERAND_LAB_8_24)
847 fragP->fr_offset = (fragP->fr_address + where);
848
849 fix_new (fragP,
850 rl_where,
851 0, abs_section_sym, rl_addend, 0,
852 BFD_RELOC_M32C_RL_JUMP);
853 }
854
855 if (S_GET_SEGMENT (fragP->fr_symbol) != sec
856 || operand == M32C_OPERAND_LAB_8_24
857 || (m32c_relax && (operand != M32C_OPERAND_LAB_5_3
858 && operand != M32C_OPERAND_LAB32_JMP_S)))
859 {
860 assert (fragP->fr_cgen.insn != 0);
861 gas_cgen_record_fixup (fragP,
862 where,
863 fragP->fr_cgen.insn,
864 (fragP->fr_fix - where) * 8,
865 cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
866 operand),
867 fragP->fr_cgen.opinfo,
868 fragP->fr_symbol, fragP->fr_offset);
869 }
870 }
871 \f
872 /* Functions concerning relocs. */
873
874 /* The location from which a PC relative jump should be calculated,
875 given a PC relative reloc. */
876
877 long
878 md_pcrel_from_section (fixS * fixP, segT sec)
879 {
880 if (fixP->fx_addsy != (symbolS *) NULL
881 && (! S_IS_DEFINED (fixP->fx_addsy)
882 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
883 /* The symbol is undefined (or is defined but not in this section).
884 Let the linker figure it out. */
885 return 0;
886
887 return (fixP->fx_frag->fr_address + fixP->fx_where);
888 }
889
890 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
891 Returns BFD_RELOC_NONE if no reloc type can be found.
892 *FIXP may be modified if desired. */
893
894 bfd_reloc_code_real_type
895 md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
896 const CGEN_OPERAND * operand,
897 fixS * fixP ATTRIBUTE_UNUSED)
898 {
899 static const struct op_reloc {
900 /* A CGEN operand type that can be a relocatable expression. */
901 CGEN_OPERAND_TYPE operand;
902
903 /* The appropriate BFD reloc type to use for that. */
904 bfd_reloc_code_real_type reloc;
905
906 /* The offset from the start of the instruction to the field to be
907 relocated, in bytes. */
908 int offset;
909 } op_reloc_table[] = {
910
911 /* PC-REL relocs for 8-bit fields. */
912 { M32C_OPERAND_LAB_8_8, BFD_RELOC_8_PCREL, 1 },
913 { M32C_OPERAND_LAB_16_8, BFD_RELOC_8_PCREL, 2 },
914 { M32C_OPERAND_LAB_24_8, BFD_RELOC_8_PCREL, 3 },
915 { M32C_OPERAND_LAB_32_8, BFD_RELOC_8_PCREL, 4 },
916 { M32C_OPERAND_LAB_40_8, BFD_RELOC_8_PCREL, 5 },
917
918 /* PC-REL relocs for 16-bit fields. */
919 { M32C_OPERAND_LAB_8_16, BFD_RELOC_16_PCREL, 1 },
920
921 /* Absolute relocs for 8-bit fields. */
922 { M32C_OPERAND_IMM_8_QI, BFD_RELOC_8, 1 },
923 { M32C_OPERAND_IMM_16_QI, BFD_RELOC_8, 2 },
924 { M32C_OPERAND_IMM_24_QI, BFD_RELOC_8, 3 },
925 { M32C_OPERAND_IMM_32_QI, BFD_RELOC_8, 4 },
926 { M32C_OPERAND_IMM_40_QI, BFD_RELOC_8, 5 },
927 { M32C_OPERAND_IMM_48_QI, BFD_RELOC_8, 6 },
928 { M32C_OPERAND_IMM_56_QI, BFD_RELOC_8, 7 },
929 { M32C_OPERAND_DSP_8_S8, BFD_RELOC_8, 1 },
930 { M32C_OPERAND_DSP_16_S8, BFD_RELOC_8, 2 },
931 { M32C_OPERAND_DSP_24_S8, BFD_RELOC_8, 3 },
932 { M32C_OPERAND_DSP_32_S8, BFD_RELOC_8, 4 },
933 { M32C_OPERAND_DSP_40_S8, BFD_RELOC_8, 5 },
934 { M32C_OPERAND_DSP_48_S8, BFD_RELOC_8, 6 },
935 { M32C_OPERAND_DSP_8_U8, BFD_RELOC_8, 1 },
936 { M32C_OPERAND_DSP_16_U8, BFD_RELOC_8, 2 },
937 { M32C_OPERAND_DSP_24_U8, BFD_RELOC_8, 3 },
938 { M32C_OPERAND_DSP_32_U8, BFD_RELOC_8, 4 },
939 { M32C_OPERAND_DSP_40_U8, BFD_RELOC_8, 5 },
940 { M32C_OPERAND_DSP_48_U8, BFD_RELOC_8, 6 },
941 { M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, BFD_RELOC_8, 2 },
942 { M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, BFD_RELOC_8, 2 },
943 { M32C_OPERAND_BITBASE32_24_S11_PREFIXED, BFD_RELOC_8, 3 },
944 { M32C_OPERAND_BITBASE32_24_U11_PREFIXED, BFD_RELOC_8, 3 },
945
946 /* Absolute relocs for 16-bit fields. */
947 { M32C_OPERAND_IMM_8_HI, BFD_RELOC_16, 1 },
948 { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 },
949 { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 },
950 { M32C_OPERAND_IMM_32_HI, BFD_RELOC_16, 4 },
951 { M32C_OPERAND_IMM_40_HI, BFD_RELOC_16, 5 },
952 { M32C_OPERAND_IMM_48_HI, BFD_RELOC_16, 6 },
953 { M32C_OPERAND_IMM_56_HI, BFD_RELOC_16, 7 },
954 { M32C_OPERAND_IMM_64_HI, BFD_RELOC_16, 8 },
955 { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 },
956 { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 },
957 { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 },
958 { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 },
959 { M32C_OPERAND_DSP_8_U16, BFD_RELOC_16, 1 },
960 { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 },
961 { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 },
962 { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 },
963 { M32C_OPERAND_DSP_40_U16, BFD_RELOC_16, 5 },
964 { M32C_OPERAND_DSP_48_U16, BFD_RELOC_16, 6 },
965 { M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, BFD_RELOC_16, 2 },
966 { M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, BFD_RELOC_16, 2 },
967 { M32C_OPERAND_BITBASE32_24_S19_PREFIXED, BFD_RELOC_16, 3 },
968 { M32C_OPERAND_BITBASE32_24_U19_PREFIXED, BFD_RELOC_16, 3 },
969
970 /* Absolute relocs for 24-bit fields. */
971 { M32C_OPERAND_LAB_8_24, BFD_RELOC_24, 1 },
972 { M32C_OPERAND_DSP_8_S24, BFD_RELOC_24, 1 },
973 { M32C_OPERAND_DSP_8_U24, BFD_RELOC_24, 1 },
974 { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 },
975 { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 },
976 { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 },
977 { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 },
978 { M32C_OPERAND_DSP_48_U24, BFD_RELOC_24, 6 },
979 { M32C_OPERAND_DSP_16_U20, BFD_RELOC_24, 2 },
980 { M32C_OPERAND_DSP_24_U20, BFD_RELOC_24, 3 },
981 { M32C_OPERAND_DSP_32_U20, BFD_RELOC_24, 4 },
982 { M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, BFD_RELOC_24, 2 },
983 { M32C_OPERAND_BITBASE32_24_U27_PREFIXED, BFD_RELOC_24, 3 },
984
985 /* Absolute relocs for 32-bit fields. */
986 { M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 },
987 { M32C_OPERAND_IMM_24_SI, BFD_RELOC_32, 3 },
988 { M32C_OPERAND_IMM_32_SI, BFD_RELOC_32, 4 },
989 { M32C_OPERAND_IMM_40_SI, BFD_RELOC_32, 5 },
990
991 };
992
993 int i;
994
995 for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; )
996 {
997 const struct op_reloc *or = &op_reloc_table[i];
998
999 if (or->operand == operand->type)
1000 {
1001 fixP->fx_where += or->offset;
1002 fixP->fx_size -= or->offset;
1003
1004 if (fixP->fx_cgen.opinfo
1005 && fixP->fx_cgen.opinfo != BFD_RELOC_NONE)
1006 return fixP->fx_cgen.opinfo;
1007
1008 return or->reloc;
1009 }
1010 }
1011
1012 fprintf
1013 (stderr,
1014 "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %s\n",
1015 operand->name);
1016
1017 return BFD_RELOC_NONE;
1018 }
1019
1020 void
1021 m32c_apply_fix (struct fix *f, valueT *t, segT s)
1022 {
1023 if (f->fx_r_type == BFD_RELOC_M32C_RL_JUMP
1024 || f->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
1025 || f->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
1026 return;
1027 gas_cgen_md_apply_fix (f, t, s);
1028 }
1029
1030 arelent *
1031 tc_gen_reloc (asection *sec, fixS *fx)
1032 {
1033 if (fx->fx_r_type == BFD_RELOC_M32C_RL_JUMP
1034 || fx->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
1035 || fx->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
1036 {
1037 arelent * reloc;
1038
1039 reloc = xmalloc (sizeof (* reloc));
1040
1041 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1042 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy);
1043 reloc->address = fx->fx_frag->fr_address + fx->fx_where;
1044 reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type);
1045 reloc->addend = fx->fx_offset;
1046 return reloc;
1047
1048 }
1049 return gas_cgen_tc_gen_reloc (sec, fx);
1050 }
1051
1052 /* See whether we need to force a relocation into the output file.
1053 This is used to force out switch and PC relative relocations when
1054 relaxing. */
1055
1056 int
1057 m32c_force_relocation (fixS * fixp)
1058 {
1059 int reloc = fixp->fx_r_type;
1060
1061 if (reloc > (int)BFD_RELOC_UNUSED)
1062 {
1063 reloc -= (int)BFD_RELOC_UNUSED;
1064 switch (reloc)
1065 {
1066 case M32C_OPERAND_DSP_32_S16:
1067 case M32C_OPERAND_DSP_32_U16:
1068 case M32C_OPERAND_IMM_32_HI:
1069 case M32C_OPERAND_DSP_16_S16:
1070 case M32C_OPERAND_DSP_16_U16:
1071 case M32C_OPERAND_IMM_16_HI:
1072 case M32C_OPERAND_DSP_24_S16:
1073 case M32C_OPERAND_DSP_24_U16:
1074 case M32C_OPERAND_IMM_24_HI:
1075 return 1;
1076
1077 /* If we're doing linker relaxing, we need to keep all the
1078 pc-relative jumps in case we need to fix them due to
1079 deleted bytes between the jump and its destination. */
1080 case M32C_OPERAND_LAB_8_8:
1081 case M32C_OPERAND_LAB_8_16:
1082 case M32C_OPERAND_LAB_8_24:
1083 case M32C_OPERAND_LAB_16_8:
1084 case M32C_OPERAND_LAB_24_8:
1085 case M32C_OPERAND_LAB_32_8:
1086 case M32C_OPERAND_LAB_40_8:
1087 if (m32c_relax)
1088 return 1;
1089 default:
1090 break;
1091 }
1092 }
1093 else
1094 {
1095 switch (fixp->fx_r_type)
1096 {
1097 case BFD_RELOC_16:
1098 return 1;
1099
1100 case BFD_RELOC_M32C_RL_JUMP:
1101 case BFD_RELOC_M32C_RL_1ADDR:
1102 case BFD_RELOC_M32C_RL_2ADDR:
1103 case BFD_RELOC_8_PCREL:
1104 case BFD_RELOC_16_PCREL:
1105 if (m32c_relax)
1106 return 1;
1107 default:
1108 break;
1109 }
1110 }
1111
1112 return generic_force_reloc (fixp);
1113 }
1114 \f
1115 /* Write a value out to the object file, using the appropriate endianness. */
1116
1117 void
1118 md_number_to_chars (char * buf, valueT val, int n)
1119 {
1120 number_to_chars_littleendian (buf, val, n);
1121 }
1122
1123 /* Turn a string in input_line_pointer into a floating point constant of type
1124 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1125 emitted is stored in *sizeP . An error message is returned, or NULL on OK. */
1126
1127 /* Equal to MAX_PRECISION in atof-ieee.c. */
1128 #define MAX_LITTLENUMS 6
1129
1130 char *
1131 md_atof (int type, char * litP, int * sizeP)
1132 {
1133 int i;
1134 int prec;
1135 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1136 char * t;
1137
1138 switch (type)
1139 {
1140 case 'f':
1141 case 'F':
1142 case 's':
1143 case 'S':
1144 prec = 2;
1145 break;
1146
1147 case 'd':
1148 case 'D':
1149 case 'r':
1150 case 'R':
1151 prec = 4;
1152 break;
1153
1154 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1155
1156 default:
1157 * sizeP = 0;
1158 return _("Bad call to md_atof()");
1159 }
1160
1161 t = atof_ieee (input_line_pointer, type, words);
1162 if (t)
1163 input_line_pointer = t;
1164 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1165
1166 for (i = 0; i < prec; i++)
1167 {
1168 md_number_to_chars (litP, (valueT) words[i],
1169 sizeof (LITTLENUM_TYPE));
1170 litP += sizeof (LITTLENUM_TYPE);
1171 }
1172
1173 return 0;
1174 }
1175
1176 bfd_boolean
1177 m32c_fix_adjustable (fixS * fixP)
1178 {
1179 int reloc;
1180 if (fixP->fx_addsy == NULL)
1181 return 1;
1182
1183 /* We need the symbol name for the VTABLE entries. */
1184 reloc = fixP->fx_r_type;
1185 if (reloc > (int)BFD_RELOC_UNUSED)
1186 {
1187 reloc -= (int)BFD_RELOC_UNUSED;
1188 switch (reloc)
1189 {
1190 case M32C_OPERAND_DSP_32_S16:
1191 case M32C_OPERAND_DSP_32_U16:
1192 case M32C_OPERAND_IMM_32_HI:
1193 case M32C_OPERAND_DSP_16_S16:
1194 case M32C_OPERAND_DSP_16_U16:
1195 case M32C_OPERAND_IMM_16_HI:
1196 case M32C_OPERAND_DSP_24_S16:
1197 case M32C_OPERAND_DSP_24_U16:
1198 case M32C_OPERAND_IMM_24_HI:
1199 return 0;
1200 }
1201 }
1202 else
1203 {
1204 if (fixP->fx_r_type == BFD_RELOC_16)
1205 return 0;
1206 }
1207
1208 /* Do not adjust relocations involving symbols in merged sections.
1209
1210 A reloc patching in the value of some symbol S plus some addend A
1211 can be produced in different ways:
1212
1213 1) It might simply be a reference to the data at S + A. Clearly,
1214 if linker merging shift that data around, the value patched in
1215 by the reloc needs to be adjusted accordingly.
1216
1217 2) Or, it might be a reference to S, with A added in as a constant
1218 bias. For example, given code like this:
1219
1220 static int S[100];
1221
1222 ... S[i - 8] ...
1223
1224 it would be reasonable for the compiler to rearrange the array
1225 reference to something like:
1226
1227 ... (S-8)[i] ...
1228
1229 and emit assembly code that refers to S - (8 * sizeof (int)),
1230 so the subtraction is done entirely at compile-time. In this
1231 case, the reloc's addend A would be -(8 * sizeof (int)), and
1232 shifting around code or data at S + A should not affect the
1233 reloc: the reloc isn't referring to that code or data at all.
1234
1235 The linker has no way of knowing which case it has in hand. So,
1236 to disambiguate, we have the linker always treat reloc addends as
1237 in case 2): they're constants that should be simply added to the
1238 symbol value, just like the reloc says. And we express case 1)
1239 in different way: we have the compiler place a label at the real
1240 target, and reference that label with an addend of zero. (The
1241 compiler is unlikely to reference code using a label plus an
1242 offset anyway, since it doesn't know the sizes of the
1243 instructions.)
1244
1245 The simplification being done by gas/write.c:adjust_reloc_syms,
1246 however, turns the explicit-label usage into the label-plus-
1247 offset usage, re-introducing the ambiguity the compiler avoided.
1248 So we need to disable that simplification for symbols referring
1249 to merged data.
1250
1251 This only affects object size a little bit. */
1252 if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE)
1253 return 0;
1254
1255 if (m32c_relax)
1256 return 0;
1257
1258 return 1;
1259 }
1260
1261 /* Worker function for m32c_is_colon_insn(). */
1262 static char restore_colon PARAMS ((int));
1263
1264 static char
1265 restore_colon (int advance_i_l_p_by)
1266 {
1267 char c;
1268
1269 /* Restore the colon, and advance input_line_pointer to
1270 the end of the new symbol. */
1271 * input_line_pointer = ':';
1272 input_line_pointer += advance_i_l_p_by;
1273 c = * input_line_pointer;
1274 * input_line_pointer = 0;
1275
1276 return c;
1277 }
1278
1279 /* Determines if the symbol starting at START and ending in
1280 a colon that was at the location pointed to by INPUT_LINE_POINTER
1281 (but which has now been replaced bu a NUL) is in fact an
1282 :Z, :S, :Q, or :G suffix.
1283 If it is, then it restores the colon, advances INPUT_LINE_POINTER
1284 to the real end of the instruction/symbol, and returns the character
1285 that really terminated the symbol. Otherwise it returns 0. */
1286 char
1287 m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED)
1288 {
1289 char * i_l_p = input_line_pointer;
1290
1291 /* Check to see if the text following the colon is 'G' */
1292 if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1293 return restore_colon (2);
1294
1295 /* Check to see if the text following the colon is 'Q' */
1296 if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1297 return restore_colon (2);
1298
1299 /* Check to see if the text following the colon is 'S' */
1300 if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1301 return restore_colon (2);
1302
1303 /* Check to see if the text following the colon is 'Z' */
1304 if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1305 return restore_colon (2);
1306
1307 return 0;
1308 }
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