cpu/shift32.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: shift32.cc,v 1.31 2006/03/26 18:58:01 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2001  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26
  27
  28 #define NEED_CPU_REG_SHORTCUTS 1
  29 #include "bochs.h"
  30 #include "cpu.h"
  31 #define LOG_THIS BX_CPU_THIS_PTR
  32
  33
  34 void BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
  35 {
  36   Bit32u op1_32, op2_32, result_32;
  37   unsigned count;
  38
  39   /* op1:op2 << count.  result stored in op1 */
  40
  41   if (i->b1() == 0x1a4)
  42     count = i->Ib() & 0x1f;
  43   else // 0x1a5
  44     count = CL & 0x1f;
  45
  46   /* op1 is a register or memory reference */
  47   if (i->modC0()) {
  48     op1_32 = BX_READ_32BIT_REG(i->rm());
  49   }
  50   else {
  51     /* pointer, segment address pair */
  52     read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
  53   }
  54
  55   if (!count) return;
  56
  57   op2_32 = BX_READ_32BIT_REG(i->nnn());
  58
  59   result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
  60
  61   /* now write result back to destination */
  62   if (i->modC0()) {
  63     BX_WRITE_32BIT_REGZ(i->rm(), result_32);
  64   }
  65   else {
  66     write_RMW_virtual_dword(result_32);
  67   }
  68
  69   /* set eflags:
  70    * SHLD count affects the following flags: O,S,Z,A,P,C
  71    */
  72   SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHL32);
  73 }
  74
  75 void BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
  76 {
  77   Bit32u op1_32, op2_32, result_32;
  78   unsigned count;
  79
  80   if (i->b1() == 0x1ac)
  81     count = i->Ib() & 0x1f;
  82   else // 0x1ad
  83     count = CL & 0x1f;
  84
  85   /* op1 is a register or memory reference */
  86   if (i->modC0()) {
  87     op1_32 = BX_READ_32BIT_REG(i->rm());
  88   }
  89   else {
  90     /* pointer, segment address pair */
  91     read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
  92   }
  93
  94   if (!count) return;
  95
  96   op2_32 = BX_READ_32BIT_REG(i->nnn());
  97
  98   result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
  99
 100   /* now write result back to destination */
 101   if (i->modC0()) {
 102     BX_WRITE_32BIT_REGZ(i->rm(), result_32);
 103   }
 104   else {
 105     write_RMW_virtual_dword(result_32);
 106   }
 107
 108   /* set eflags:
 109    * SHRD count affects the following flags: O,S,Z,A,P,C
 110    */
 111   SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHRD32);
 112 }
 113
 114 void BX_CPU_C::ROL_Ed(bxInstruction_c *i)
 115 {
 116   Bit32u op1_32, result_32;
 117   unsigned count;
 118
 119   if (i->b1() == 0xc1)
 120     count = i->Ib() & 0x1f;
 121   else if (i->b1() == 0xd1)
 122     count = 1;
 123   else // (i->b1() == 0xd3)
 124     count = CL & 0x1f;
 125
 126   /* op1 is a register or memory reference */
 127   if (i->modC0()) {
 128     op1_32 = BX_READ_32BIT_REG(i->rm());
 129   }
 130   else {
 131     /* pointer, segment address pair */
 132     read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
 133   }
 134
 135   if (! count) return;
 136
 137   result_32 = (op1_32 << count) | (op1_32 >> (32 - count));
 138
 139   /* now write result back to destination */
 140   if (i->modC0()) {
 141     BX_WRITE_32BIT_REGZ(i->rm(), result_32);
 142   }
 143   else {
 144     write_RMW_virtual_dword(result_32);
 145   }
 146
 147   /* set eflags:
 148    * ROL count affects the following flags: C, O
 149    */
 150   bx_bool temp_CF = (result_32 & 0x01);
 151
 152   set_CF(temp_CF);
 153   set_OF(temp_CF ^ (result_32 >> 31));
 154 }
 155
 156 void BX_CPU_C::ROR_Ed(bxInstruction_c *i)
 157 {
 158   Bit32u op1_32, result_32;
 159   unsigned count;
 160
 161   if (i->b1() == 0xc1)
 162     count = i->Ib() & 0x1f;
 163   else if (i->b1() == 0xd1)
 164     count = 1;
 165   else // (i->b1() == 0xd3)
 166     count = CL & 0x1f;
 167
 168   /* op1 is a register or memory reference */
 169   if (i->modC0()) {
 170     op1_32 = BX_READ_32BIT_REG(i->rm());
 171   }
 172   else {
 173     /* pointer, segment address pair */
 174     read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
 175   }
 176
 177   if (! count) return;
 178
 179   result_32 = (op1_32 >> count) | (op1_32 << (32 - count));
 180
 181   /* now write result back to destination */
 182   if (i->modC0()) {
 183     BX_WRITE_32BIT_REGZ(i->rm(), result_32);
 184   }
 185   else {
 186     write_RMW_virtual_dword(result_32);
 187   }
 188
 189   /* set eflags:
 190    * ROR count affects the following flags: C, O
 191    */
 192   bx_bool result_b31 = (result_32 & 0x80000000) != 0;
 193   bx_bool result_b30 = (result_32 & 0x40000000) != 0;
 194
 195   set_CF(result_b31);
 196   set_OF(result_b31 ^ result_b30);
 197 }
 198
 199 void BX_CPU_C::RCL_Ed(bxInstruction_c *i)
 200 {
 201   Bit32u op1_32, result_32;
 202   unsigned count;
 203
 204   if (i->b1() == 0xc1)
 205     count = i->Ib() & 0x1f;
 206   else if (i->b1() == 0xd1)
 207     count = 1;
 208   else // (i->b1() == 0xd3)
 209     count = CL & 0x1f;
 210
 211   /* op1 is a register or memory reference */
 212   if (i->modC0()) {
 213     op1_32 = BX_READ_32BIT_REG(i->rm());
 214   }
 215   else {
 216     /* pointer, segment address pair */
 217     read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
 218   }
 219
 220   if (!count) return;
 221
 222   if (count==1) {
 223     result_32 = (op1_32 << 1) | getB_CF();
 224   }
 225   else {
 226     result_32 = (op1_32 << count) | (getB_CF() << (count - 1)) |
 227                 (op1_32 >> (33 - count));
 228   }
 229
 230   /* now write result back to destination */
 231   if (i->modC0()) {
 232     BX_WRITE_32BIT_REGZ(i->rm(), result_32);
 233   }
 234   else {
 235     write_RMW_virtual_dword(result_32);
 236   }
 237
 238   /* set eflags:
 239    * RCL count affects the following flags: C, O
 240    */
 241   bx_bool temp_CF = (op1_32 >> (32 - count)) & 0x01;
 242
 243   set_CF(temp_CF);
 244   set_OF(temp_CF ^ (result_32 >> 31));
 245 }
 246
 247 void BX_CPU_C::RCR_Ed(bxInstruction_c *i)
 248 {
 249   Bit32u op1_32, result_32;
 250   unsigned count;
 251
 252   if (i->b1() == 0xc1)
 253     count = i->Ib() & 0x1f;
 254   else if (i->b1() == 0xd1)
 255     count = 1;
 256   else // (i->b1() == 0xd3)
 257     count = CL & 0x1f;
 258
 259   /* op1 is a register or memory reference */
 260   if (i->modC0()) {
 261     op1_32 = BX_READ_32BIT_REG(i->rm());
 262   }
 263   else {
 264     /* pointer, segment address pair */
 265     read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
 266   }
 267
 268   if (!count) return;
 269
 270   if (count==1) {
 271     result_32 = (op1_32 >> 1) | (getB_CF() << 31);
 272   }
 273   else {
 274     result_32 = (op1_32 >> count) | (getB_CF() << (32 - count)) |
 275                 (op1_32 << (33 - count));
 276   }
 277
 278   /* now write result back to destination */
 279   if (i->modC0()) {
 280     BX_WRITE_32BIT_REGZ(i->rm(), result_32);
 281   }
 282   else {
 283     write_RMW_virtual_dword(result_32);
 284   }
 285
 286   /* set eflags:
 287    * RCR count affects the following flags: C, O
 288    */
 289
 290   set_CF((op1_32 >> (count - 1)) & 0x01);
 291   set_OF((((result_32 << 1) ^ result_32) & 0x80000000) > 0);
 292 }
 293
 294 void BX_CPU_C::SHL_Ed(bxInstruction_c *i)
 295 {
 296   Bit32u op1_32, result_32;
 297   unsigned count;
 298
 299   if (i->b1() == 0xc1)
 300     count = i->Ib() & 0x1f;
 301   else if (i->b1() == 0xd1)
 302     count = 1;
 303   else // (i->b1() == 0xd3)
 304     count = CL & 0x1f;
 305
 306   /* op1 is a register or memory reference */
 307   if (i->modC0()) {
 308     op1_32 = BX_READ_32BIT_REG(i->rm());
 309   }
 310   else {
 311     /* pointer, segment address pair */
 312     read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
 313   }
 314
 315   if (!count) return;
 316
 317   result_32 = (op1_32 << count);
 318
 319   /* now write result back to destination */
 320   if (i->modC0()) {
 321     BX_WRITE_32BIT_REGZ(i->rm(), result_32);
 322   }
 323   else {
 324     write_RMW_virtual_dword(result_32);
 325   }
 326
 327   SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHL32);
 328 }
 329
 330 void BX_CPU_C::SHR_Ed(bxInstruction_c *i)
 331 {
 332   Bit32u op1_32, result_32;
 333   unsigned count;
 334
 335   if (i->b1() == 0xc1)
 336     count = i->Ib() & 0x1f;
 337   else if (i->b1() == 0xd1)
 338     count = 1;
 339   else // (i->b1() == 0xd3)
 340     count = CL & 0x1f;
 341
 342   /* op1 is a register or memory reference */
 343   if (i->modC0()) {
 344     op1_32 = BX_READ_32BIT_REG(i->rm());
 345   }
 346   else {
 347     /* pointer, segment address pair */
 348     read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
 349   }
 350
 351     if (!count) return;
 352
 353 #if defined(BX_HostAsm_Shr32)
 354   Bit32u flags32;
 355   asmShr32(result_32, op1_32, count, flags32);
 356   setEFlagsOSZAPC(flags32);
 357 #else
 358   result_32 = (op1_32 >> count);
 359   SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHR32);
 360 #endif
 361
 362   /* now write result back to destination */
 363   if (i->modC0()) {
 364     BX_WRITE_32BIT_REGZ(i->rm(), result_32);
 365   }
 366   else {
 367     write_RMW_virtual_dword(result_32);
 368   }
 369 }
 370
 371 void BX_CPU_C::SAR_Ed(bxInstruction_c *i)
 372 {
 373   Bit32u op1_32, result_32;
 374   unsigned count;
 375
 376   if (i->b1() == 0xc1)
 377     count = i->Ib() & 0x1f;
 378   else if (i->b1() == 0xd1)
 379     count = 1;
 380   else // (i->b1() == 0xd3)
 381     count = CL & 0x1f;
 382
 383   /* op1 is a register or memory reference */
 384   if (i->modC0()) {
 385     op1_32 = BX_READ_32BIT_REG(i->rm());
 386   }
 387   else {
 388     /* pointer, segment address pair */
 389     read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
 390   }
 391
 392   if (!count) return;
 393
 394   /* count < 32, since only lower 5 bits used */
 395   if (op1_32 & 0x80000000) {
 396     result_32 = (op1_32 >> count) | (0xffffffff << (32 - count));
 397   }
 398   else {
 399     result_32 = (op1_32 >> count);
 400   }
 401
 402   /* now write result back to destination */
 403   if (i->modC0()) {
 404     BX_WRITE_32BIT_REGZ(i->rm(), result_32);
 405   }
 406   else {
 407     write_RMW_virtual_dword(result_32);
 408   }
 409
 410   SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SAR32);
 411 }