soc/intel/xeon_sp: Modify FSP-T code caching parameters
[coreboot.git] / src / soc / intel / xeon_sp / bootblock / bootblock.c
blobdc88adc308719a5485878d992641fb7544d8ece3
1 /*
2 * This file is part of the coreboot project.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <bootblock_common.h>
17 #include <device/pci.h>
18 #include <FsptUpd.h>
19 #include <intelblocks/fast_spi.h>
20 #include <soc/iomap.h>
21 #include <console/console.h>
22 #include <cpu/x86/mtrr.h>
24 const FSPT_UPD temp_ram_init_params = {
25 .FspUpdHeader = {
26 .Signature = FSPT_UPD_SIGNATURE,
27 .Revision = 1,
28 .Reserved = {0},
30 .FsptCoreUpd = {
31 .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
32 .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
33 .CodeRegionBase = (UINT32)CACHE_ROM_BASE,
34 .CodeRegionLength = (UINT32)CACHE_ROM_SIZE,
35 .Reserved1 = {0},
37 .FsptConfig = {
38 .PcdFsptPort80RouteDisable = 0,
39 .ReservedTempRamInitUpd = {0},
41 .UnusedUpdSpace0 = {0},
42 .UpdTerminator = 0x55AA,
45 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
47 fast_spi_cache_bios_region();
49 bootblock_main_with_basetime(base_timestamp);
52 void bootblock_soc_early_init(void)
54 fast_spi_early_init(SPI_BASE_ADDRESS);
57 void bootblock_soc_init(void)
59 if (CONFIG(BOOTBLOCK_CONSOLE))
60 printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");