src/soc/intel/alderlake/pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Alder Lake Processor PCH Datasheet
   5  * Document number: 621483
   6  * Chapter number: 4
   7  */
   8
   9 #include <acpi/acpigen.h>
  10 #include <console/console.h>
  11 #include <device/mmio.h>
  12 #include <device/device.h>
  13 #include <drivers/intel/pmc_mux/chip.h>
  14 #include <intelblocks/acpi.h>
  15 #include <intelblocks/pmc.h>
  16 #include <intelblocks/pmc_ipc.h>
  17 #include <intelblocks/pmclib.h>
  18 #include <intelblocks/rtc.h>
  19 #include <soc/cpu.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/pm.h>
  22 #include <soc/soc_chip.h>
  23 #include <stdint.h>
  24 #include <bootstate.h>
  25
  26 #define PMC_HID         "INTC1026"
  27
  28 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
  29 {
  30         uint32_t reg;
  31         uint8_t *pmcbase = pmc_mmio_regs();
  32
  33         printk(BIOS_DEBUG, "%sabling Deep S%c\n",
  34                 enable ? "En" : "Dis", sx + '0');
  35         reg = read32(pmcbase + offset);
  36         if (enable)
  37                 reg |= mask;
  38         else
  39                 reg &= ~mask;
  40         write32(pmcbase + offset, reg);
  41 }
  42
  43 static void config_deep_s5(int on_ac, int on_dc)
  44 {
  45         /* Treat S4 the same as S5. */
  46         config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
  47         config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
  48         config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
  49         config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
  50 }
  51
  52 static void config_deep_s3(int on_ac, int on_dc)
  53 {
  54         config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
  55         config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
  56 }
  57
  58 static void config_deep_sx(uint32_t deepsx_config)
  59 {
  60         uint32_t reg;
  61         uint8_t *pmcbase = pmc_mmio_regs();
  62
  63         reg = read32(pmcbase + DSX_CFG);
  64         reg &= ~DSX_CFG_MASK;
  65         reg |= deepsx_config;
  66         write32(pmcbase + DSX_CFG, reg);
  67 }
  68
  69 static void soc_pmc_enable(struct device *dev)
  70 {
  71         const config_t *config = config_of_soc();
  72
  73         rtc_init();
  74
  75         pmc_set_power_failure_state(true);
  76         pmc_gpe_init();
  77
  78         config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
  79         config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
  80         config_deep_sx(config->deep_sx_config);
  81 }
  82
  83 static void soc_pmc_read_resources(struct device *dev)
  84 {
  85         struct resource *res;
  86
  87         /* Add the fixed MMIO resource */
  88         mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
  89
  90         /* Add the fixed I/O resource */
  91         res = new_resource(dev, 1);
  92         res->base = (resource_t)ACPI_BASE_ADDRESS;
  93         res->size = (resource_t)ACPI_BASE_SIZE;
  94         res->limit = res->base + res->size - 1;
  95         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  96 }
  97
  98 static void soc_pmc_fill_ssdt(const struct device *dev)
  99 {
 100         const char *scope = acpi_device_scope(dev);
 101         const char *name = acpi_device_name(dev);
 102         if (!scope || !name)
 103                 return;
 104
 105         acpigen_write_scope(scope);
 106         acpigen_write_device(name);
 107
 108         acpigen_write_name_string("_HID", PMC_HID);
 109         acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller");
 110         acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
 111
 112         /*
 113          * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF).
 114          * The PMC gets 0xFE000000 - 0xFE00FFFF.
 115          */
 116         acpigen_write_name("_CRS");
 117         acpigen_write_resourcetemplate_header();
 118         acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
 119         acpigen_write_resourcetemplate_footer();
 120
 121         /* Define IPC Write Method */
 122         if (CONFIG(PMC_IPC_ACPI_INTERFACE))
 123                 pmc_ipc_acpi_fill_ssdt();
 124
 125         acpigen_pop_len(); /* PMC Device */
 126         acpigen_pop_len(); /* Scope */
 127
 128         if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) {
 129                 const struct soc_pmc_lpm adl_pmc_lpm = {
 130                         .num_substates = 8,
 131                         .num_req_regs = 6,
 132                         .lpm_ipc_offset = 0x1000,
 133                         .req_reg_stride = 0x30,
 134                         .lpm_enable_mask = get_supported_lpm_mask(),
 135                 };
 136
 137                 generate_acpi_power_engine_with_lpm(&adl_pmc_lpm);
 138         }
 139
 140         printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name,
 141                dev_path(dev));
 142 }
 143
 144 static void soc_pmc_init(struct device *dev)
 145 {
 146         /*
 147          * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
 148          * to ensure the ordering does not break the assumptions that other
 149          * drivers make about ACPI mode (e.g. Chrome EC). Since it disables
 150          * ACPI mode, other drivers may take different actions based on this
 151          * (e.g. Chrome EC will flush any pending hostevent bits). Because
 152          * TGL has its PMC device available for device_operations, it can be
 153          * done from the "ops->init" callback.
 154          */
 155         pmc_set_acpi_mode();
 156
 157         /*
 158          * Disable ACPI PM timer based on Kconfig
 159          *
 160          * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
 161          * Disabling ACPI PM timer also switches off TCO
 162          */
 163         if (!CONFIG(USE_PM_ACPI_TIMER))
 164                 setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
 165 }
 166
 167 static void pm1_enable_pwrbtn_smi(void *unused)
 168 {
 169         /* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
 170         pmc_update_pm1_enable(PWRBTN_EN);
 171 }
 172
 173 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
 174
 175 /*
 176  * `pmc_final` function is native implementation of equivalent events performed by
 177  * each FSP NotifyPhase() API invocations.
 178  *
 179  *
 180  * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits)
 181  *
 182  * Perform the PMCON status bit clear operation from `.final`
 183  * to cover any such chances where later boot stage requested a global
 184  * reset and PMCON status bit remains set.
 185  */
 186 static void pmc_final(struct device *dev)
 187 {
 188         pmc_clear_pmcon_sts();
 189 }
 190
 191 struct device_operations pmc_ops = {
 192         .read_resources   = soc_pmc_read_resources,
 193         .set_resources    = noop_set_resources,
 194         .init             = soc_pmc_init,
 195         .enable           = soc_pmc_enable,
 196 #if CONFIG(HAVE_ACPI_TABLES)
 197         .acpi_fill_ssdt   = soc_pmc_fill_ssdt,
 198 #endif
 199         .scan_bus         = scan_static_bus,
 200         .final            = pmc_final,
 201 };