src/soc/intel/apollolake/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #define __SIMPLE_DEVICE__
   4
   5 #include <acpi/acpi.h>
   6 #include <acpi/acpi_pm.h>
   7 #include <arch/io.h>
   8 #include <device/mmio.h>
   9 #include <console/console.h>
  10 #include <device/device.h>
  11 #include <device/pci.h>
  12 #include <intelblocks/msr.h>
  13 #include <intelblocks/pmclib.h>
  14 #include <intelblocks/rtc.h>
  15 #include <intelblocks/tco.h>
  16 #include <soc/iomap.h>
  17 #include <soc/cpu.h>
  18 #include <soc/pci_devs.h>
  19 #include <soc/pm.h>
  20 #include <soc/smbus.h>
  21 #include <security/vboot/vbnv.h>
  22
  23 #include "chip.h"
  24
  25 uint8_t *pmc_mmio_regs(void)
  26 {
  27         return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
  28 }
  29
  30 uintptr_t soc_read_pmc_base(void)
  31 {
  32         return (uintptr_t)pmc_mmio_regs();
  33 }
  34
  35 uint32_t *soc_pmc_etr_addr(void)
  36 {
  37         return (uint32_t *)(soc_read_pmc_base() + ETR);
  38 }
  39
  40 const char *const *soc_smi_sts_array(size_t *a)
  41 {
  42         static const char *const smi_sts_bits[] = {
  43                 [BIOS_STS_BIT] = "BIOS",
  44                 [LEGACY_USB_STS_BIT] = "LEGACY USB",
  45                 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
  46                 [APM_STS_BIT] = "APM",
  47                 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
  48                 [PM1_STS_BIT] = "PM1",
  49                 [GPE0_STS_BIT] = "GPE0 (reserved)",
  50                 [GPIO_STS_BIT] = "GPIO_SMI",
  51                 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI",
  52                 [MC_SMI_STS_BIT] = "MCSMI",
  53                 [TCO_STS_BIT] = "TCO",
  54                 [PERIODIC_STS_BIT] = "PERIODIC",
  55                 [SERIRQ_SMI_STS_BIT] = "SERIRQ",
  56                 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
  57                 [XHCI_SMI_STS_BIT] = "XHCI",
  58                 [HSMBUS_SMI_STS_BIT] = "HOST_SMBUS",
  59                 [SCS_SMI_STS_BIT] = "SCS",
  60                 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
  61                 [SCC2_SMI_STS_BIT] = "SCC2",
  62                 [SPI_SSMI_STS_BIT] = "SPI_SSMI",
  63                 [SPI_SMI_STS_BIT] = "SPI",
  64                 [PMC_OCP_SMI_STS_BIT] = "OCP_CSE",
  65         };
  66
  67         *a = ARRAY_SIZE(smi_sts_bits);
  68         return smi_sts_bits;
  69 }
  70
  71 /*
  72  * For APL/GLK this check for power button status if nothing else
  73  * is indicating an SMI and SMIs aren't turned into SCIs.
  74  * Apparently, there is no PM1 status bit in the SMI status
  75  * register.  That makes things difficult for
  76  * determining if the power button caused an SMI.
  77  */
  78 uint32_t soc_get_smi_status(uint32_t generic_sts)
  79 {
  80         if (generic_sts == 0 && !(pmc_read_pm1_control() & SCI_EN)) {
  81                 uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
  82
  83                 /* Fake PM1 status bit if power button pressed. */
  84                 if (pm1_sts & PWRBTN_STS)
  85                         generic_sts |= (1 << PM1_STS_BIT);
  86         }
  87
  88         /*
  89          * GPE0_STS is reserved in APL/GLK datasheets. For compatibility
  90          * with common code, mask it out so that it is always zero.
  91          */
  92         return generic_sts & ~(1 << GPE0_STS_BIT);
  93 }
  94
  95 const char *const *soc_tco_sts_array(size_t *a)
  96 {
  97         static const char *const tco_sts_bits[] = {
  98                 [3] = "TIMEOUT",
  99                 [17] = "SECOND_TO",
 100         };
 101
 102         *a = ARRAY_SIZE(tco_sts_bits);
 103         return tco_sts_bits;
 104 }
 105
 106 const char *const *soc_std_gpe_sts_array(size_t *a)
 107 {
 108         static const char *const gpe_sts_bits[] = {
 109                 [0] = "PCIE_SCI",
 110                 [2] = "SWGPE",
 111                 [3] = "PCIE_WAKE0",
 112                 [4] = "PUNIT",
 113                 [6] = "PCIE_WAKE1",
 114                 [7] = "PCIE_WAKE2",
 115                 [8] = "PCIE_WAKE3",
 116                 [9] = "PCI_EXP",
 117                 [10] = "BATLOW",
 118                 [11] = "CSE_PME",
 119                 [12] = "XDCI_PME",
 120                 [13] = "XHCI_PME",
 121                 [14] = "AVS_PME",
 122                 [15] = "GPIO_TIER1_SCI",
 123                 [16] = "SMB_WAK",
 124                 [17] = "SATA_PME",
 125         };
 126
 127         *a = ARRAY_SIZE(gpe_sts_bits);
 128         return gpe_sts_bits;
 129 }
 130
 131 void soc_clear_pm_registers(uintptr_t pmc_bar)
 132 {
 133         uint32_t gen_pmcon1;
 134
 135         gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1);
 136         /* Clear the status bits. The RPS field is cleared on a 0 write. */
 137         write32p(pmc_bar + GEN_PMCON1, gen_pmcon1 & ~RPS);
 138 }
 139
 140 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 141 {
 142         DEVTREE_CONST struct soc_intel_apollolake_config *config;
 143
 144         config = config_of_soc();
 145
 146         /* Assign to out variable */
 147         *dw0 = config->gpe0_dw1;
 148         *dw1 = config->gpe0_dw2;
 149         *dw2 = config->gpe0_dw3;
 150 }
 151
 152 void soc_fill_power_state(struct chipset_power_state *ps)
 153 {
 154         uintptr_t pmc_bar0 = soc_read_pmc_base();
 155
 156         ps->tco1_sts = tco_read_reg(TCO1_STS);
 157         ps->tco2_sts = tco_read_reg(TCO2_STS);
 158
 159         ps->prsts = read32p(pmc_bar0 + PRSTS);
 160         ps->gen_pmcon1 = read32p(pmc_bar0 + GEN_PMCON1);
 161         ps->gen_pmcon2 = read32p(pmc_bar0 + GEN_PMCON2);
 162         ps->gen_pmcon3 = read32p(pmc_bar0 + GEN_PMCON3);
 163
 164         printk(BIOS_DEBUG, "prsts: %08x\n",
 165                ps->prsts);
 166         printk(BIOS_DEBUG, "tco_sts:   %04x %04x\n",
 167                ps->tco1_sts, ps->tco2_sts);
 168         printk(BIOS_DEBUG,
 169                "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
 170                ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
 171 }
 172
 173 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 174 int soc_prev_sleep_state(const struct chipset_power_state *ps,
 175         int prev_sleep_state)
 176 {
 177         /* WAK_STS bit will not be set when waking from G3 state */
 178
 179         if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon1 & COLD_BOOT_STS))
 180                 prev_sleep_state = ACPI_S5;
 181         return prev_sleep_state;
 182 }
 183
 184 static int rtc_failed(uint32_t gen_pmcon1)
 185 {
 186         return !!(gen_pmcon1 & RPS);
 187 }
 188
 189 int soc_get_rtc_failed(void)
 190 {
 191         const struct chipset_power_state *ps;
 192
 193         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
 194                 return 1;
 195
 196         return rtc_failed(ps->gen_pmcon1);
 197 }
 198
 199 int vbnv_cmos_failed(void)
 200 {
 201         uintptr_t pmc_bar = soc_read_pmc_base();
 202         uint32_t gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1);
 203         int rtc_failure = rtc_failed(gen_pmcon1);
 204
 205         if (rtc_failure) {
 206                 printk(BIOS_INFO, "RTC failed!\n");
 207
 208                 /* We do not want to write 1 to clear-1 bits. Set them to 0. */
 209                 gen_pmcon1 &= ~GEN_PMCON1_CLR1_BITS;
 210
 211                 /* RPS is write 0 to clear. */
 212                 gen_pmcon1 &= ~RPS;
 213
 214                 write32p(pmc_bar + GEN_PMCON1, gen_pmcon1);
 215         }
 216
 217         return rtc_failure;
 218 }
 219
 220 /* STM Support */
 221 uint16_t get_pmbase(void)
 222 {
 223         return (uint16_t)ACPI_BASE_ADDRESS;
 224 }
 225
 226 /* Set which power state system will be after reapplying the power (from G3 State) */
 227 void pmc_soc_set_afterg3_en(const bool on)
 228 {
 229         uint8_t reg8;
 230         uint8_t *const pmcbase = pmc_mmio_regs();
 231
 232         reg8 = read8(pmcbase + GEN_PMCON_A);
 233         if (on)
 234                 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
 235         else
 236                 reg8 |= SLEEP_AFTER_POWER_FAIL;
 237         write8(pmcbase + GEN_PMCON_A, reg8);
 238 }