src/soc/intel/elkhartlake/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 #include <assert.h>
   3 #include <cbfs.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <fsp/api.h>
   7 #include <fsp/ppi/mp_service_ppi.h>
   8 #include <fsp/util.h>
   9 #include <option.h>
  10 #include <intelblocks/lpss.h>
  11 #include <intelblocks/pmclib.h>
  12 #include <intelblocks/xdci.h>
  13 #include <intelpch/lockdown.h>
  14 #include <soc/intel/common/vbt.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/ramstage.h>
  17 #include <soc/soc_chip.h>
  18 #include <types.h>
  19
  20 /* SATA DEVSLP idle timeout default values */
  21 #define DEF_DMVAL               15
  22 #define DEF_DITOVAL_MS          625
  23
  24 /* Native function controls pads termination */
  25 #define GPIO_TERM_NATIVE        0x1F
  26
  27 /* PM related values */
  28 /* Imon offset is defined in 1/1000 increments */
  29 #define IMON_OFFSET     1
  30 /* Policy Imon slope is defined in 1/100 increments */
  31 #define IMON_SLOPE      100
  32 /* Thermal Design Current current limit in 1/8A units */
  33 #define TDC_CURRENT_LIMIT_MAX   112
  34 /* AcLoadline in 1/100 mOhms */
  35 #define AC_LOADLINE_LANE_0_MAX  112
  36 #define AC_LOADLINE_LANE_1_MAX  3
  37 /* DcLoadline in 1/100 mOhms */
  38 #define DC_LOADLINE_LANE_0_MAX  92
  39 #define DC_LOADLINE_LANE_1_MAX  3
  40 /* VR Icc Max limit. 0-255A in 1/4 A units */
  41 #define ICC_LIMIT_MAX   104
  42 /* Core Ratio Limit: For overclocking part: LFM to Fused */
  43 #define CORE_RATIO_LIMIT        0x13
  44
  45 /*
  46  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
  47  * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
  48  * In order to ensure that mainboard setting does not disable L1 substates
  49  * incorrectly, chip config parameter values are offset by 1 with 0 meaning
  50  * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
  51  * value is set in fsp_params.
  52  * 0: Use FSP UPD default
  53  * 1: Disable L1 substates
  54  * 2: Use L1.1
  55  * 3: Use L1.2 (FSP UPD default)
  56  */
  57 static int get_l1_substate_control(enum L1_substates_control ctl)
  58 {
  59         if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
  60                 ctl = L1_SS_L1_2;
  61         return ctl - 1;
  62 }
  63
  64 static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
  65                 const struct soc_intel_elkhartlake_config *config)
  66 {
  67         s_cfg->PchFivrExtV1p05RailEnabledStates = config->fivr.v1p05_state;
  68         s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = config->fivr.v1p05_rail;
  69         s_cfg->PchFivrExtVnnRailEnabledStates = config->fivr.vnn_state;
  70         s_cfg->PchFivrExtVnnRailSupportedVoltageStates = config->fivr.vnn_rail;
  71         s_cfg->PchFivrExtVnnRailSxEnabledStates = config->fivr.vnn_sx_state;
  72         s_cfg->PchFivrVccinAuxLowToHighCurModeVolTranTime = config->fivr.vcc_low_high_us;
  73         s_cfg->PchFivrVccinAuxRetToHighCurModeVolTranTime = config->fivr.vcc_ret_high_us;
  74         s_cfg->PchFivrVccinAuxRetToLowCurModeVolTranTime = config->fivr.vcc_ret_low_us;
  75         s_cfg->PchFivrVccinAuxOffToHighCurModeVolTranTime = config->fivr.vcc_off_high_us;
  76         /* Convert mV to number of 2.5 mV increments */
  77         s_cfg->PchFivrExtVnnRailSxVoltage = (config->fivr.vnn_sx_mv * 10) / 25;
  78         s_cfg->PchFivrExtV1p05RailIccMaximum = config->fivr.v1p05_icc_max_ma;
  79         s_cfg->FivrSpreadSpectrum = config->fivr.spread_spectrum;
  80 }
  81
  82 static void fill_fsps_tsn_params(FSP_S_CONFIG *params,
  83                 const struct soc_intel_elkhartlake_config *config)
  84 {
  85         /*
  86          * Currently EHL TSN GBE only supports link speed with 2 type of
  87          * PCH XTAL frequency: 24 MHz and 38.4 MHz.
  88          * These are the config values for PchTsnGbeLinkSpeed in FSP-S UPD:
  89          * 0: 24MHz 2.5Gbps, 1: 24MHz 1Gbps, 2: 38.4MHz 2.5Gbps,
  90          * 3: 38.4MHz 1Gbps
  91          */
  92         int xtal_freq_enum = pmc_get_xtal_freq();
  93         if ((xtal_freq_enum != XTAL_24_MHZ) && (xtal_freq_enum != XTAL_38_4_MHZ)) {
  94                 printk(BIOS_ERR, "XTAL not supported. Disabling All TSN GBE ports.\n");
  95                 params->PchTsnEnable = 0;
  96                 params->PchPseGbeEnable[0] = 0;
  97                 params->PchPseGbeEnable[1] = 0;
  98                 devfn_disable(pci_root_bus(), PCH_DEVFN_GBE);
  99                 devfn_disable(pci_root_bus(), PCH_DEVFN_PSEGBE0);
 100                 devfn_disable(pci_root_bus(), PCH_DEVFN_PSEGBE1);
 101         }
 102         /*
 103          * PCH TSN settings:
 104          * Due to EHL GBE comes with time sensitive networking (TSN)
 105          * capability integrated, EHL FSP is using PchTsnEnable instead of
 106          * usual PchLanEnable flag for GBE control. Hence, force
 107          * PchLanEnable to disable to avoid it being used in the future.
 108          */
 109         params->PchLanEnable = 0x0;
 110         params->PchTsnEnable = is_devfn_enabled(PCH_DEVFN_GBE);
 111         if (params->PchTsnEnable) {
 112                 params->PchTsnGbeSgmiiEnable = config->PchTsnGbeSgmiiEnable;
 113                 params->PchTsnGbeMultiVcEnable = config->PchTsnGbeMultiVcEnable;
 114                 params->PchTsnGbeLinkSpeed = (config->PchTsnGbeLinkSpeed) + xtal_freq_enum;
 115         }
 116
 117         /* PSE TSN settings */
 118         if (!CONFIG(PSE_ENABLE))
 119                 return;
 120         for (unsigned int i = 0; i < MAX_PSE_TSN_PORTS; i++) {
 121                 switch (i) {
 122                 case 0:
 123                         params->PchPseGbeEnable[i] = is_devfn_enabled(PCH_DEVFN_PSEGBE0) ?
 124                                 Host_Owned : config->PseGbeOwn[0];
 125                         break;
 126                 case 1:
 127                         params->PchPseGbeEnable[i] = is_devfn_enabled(PCH_DEVFN_PSEGBE1) ?
 128                                 Host_Owned : config->PseGbeOwn[i];
 129                         break;
 130                 default:
 131                         break;
 132                 }
 133                 if (params->PchPseGbeEnable[i]) {
 134                         params->PseTsnGbeMultiVcEnable[i] = config->PseTsnGbeMultiVcEnable[i];
 135                         params->PseTsnGbeSgmiiEnable[i] = config->PseTsnGbeSgmiiEnable[i];
 136                         params->PseTsnGbePhyInterfaceType[i] =
 137                                 !config->PseTsnGbeSgmiiEnable[i] ?
 138                                 RGMII : config->PseTsnGbePhyType[i];
 139                         params->PseTsnGbeLinkSpeed[i] =
 140                                 (params->PseTsnGbePhyInterfaceType[i] < SGMII_plus) ?
 141                                 xtal_freq_enum + 1 : xtal_freq_enum;
 142                 }
 143         }
 144 }
 145
 146 static void fill_fsps_pse_params(FSP_S_CONFIG *params,
 147                 const struct soc_intel_elkhartlake_config *config)
 148 {
 149         static char psefwbuf[(CONFIG_PSE_FW_FILE_SIZE_KIB +
 150                 CONFIG_PSE_CONFIG_BUFFER_SIZE_KIB) * KiB];
 151         uint32_t pse_fw_base;
 152         size_t psefwsize = cbfs_load("pse.bin", psefwbuf, sizeof(psefwbuf));
 153         if (psefwsize > 0) {
 154                 pse_fw_base = (uintptr_t)&psefwbuf;
 155                 params->SiipRegionBase = pse_fw_base;
 156                 params->SiipRegionSize = psefwsize;
 157                 printk(BIOS_DEBUG, "PSE base: %08x size: %08zx\n", pse_fw_base, psefwsize);
 158
 159                 /* Configure PSE peripherals */
 160                 FSP_ARRAY_LOAD(params->PchPseDmaEnable, config->PseDmaOwn);
 161                 FSP_ARRAY_LOAD(params->PchPseDmaSbInterruptEnable, config->PseDmaSbIntEn);
 162                 FSP_ARRAY_LOAD(params->PchPseUartEnable, config->PseUartOwn);
 163                 FSP_ARRAY_LOAD(params->PchPseUartSbInterruptEnable, config->PseUartSbIntEn);
 164                 FSP_ARRAY_LOAD(params->PchPseHsuartEnable, config->PseHsuartOwn);
 165                 FSP_ARRAY_LOAD(params->PchPseQepEnable, config->PseQepOwn);
 166                 FSP_ARRAY_LOAD(params->PchPseQepSbInterruptEnable, config->PseQepSbIntEn);
 167                 FSP_ARRAY_LOAD(params->PchPseI2cEnable, config->PseI2cOwn);
 168                 FSP_ARRAY_LOAD(params->PchPseI2cSbInterruptEnable, config->PseI2cSbIntEn);
 169                 FSP_ARRAY_LOAD(params->PchPseI2sEnable, config->PseI2sOwn);
 170                 FSP_ARRAY_LOAD(params->PchPseI2sSbInterruptEnable, config->PseI2sSbIntEn);
 171                 FSP_ARRAY_LOAD(params->PchPseSpiEnable, config->PseSpiOwn);
 172                 FSP_ARRAY_LOAD(params->PchPseSpiSbInterruptEnable, config->PseSpiSbIntEn);
 173                 FSP_ARRAY_LOAD(params->PchPseSpiCs0Enable, config->PseSpiCs0Own);
 174                 FSP_ARRAY_LOAD(params->PchPseSpiCs1Enable, config->PseSpiCs1Own);
 175                 FSP_ARRAY_LOAD(params->PchPseCanEnable, config->PseCanOwn);
 176                 FSP_ARRAY_LOAD(params->PchPseCanSbInterruptEnable, config->PseCanSbIntEn);
 177                 params->PchPsePwmEnable = config->PsePwmOwn;
 178                 params->PchPsePwmSbInterruptEnable = config->PsePwmSbIntEn;
 179                 FSP_ARRAY_LOAD(params->PchPsePwmPinEnable, config->PsePwmPinEn);
 180                 params->PchPseAdcEnable = config->PseAdcOwn;
 181                 params->PchPseAdcSbInterruptEnable = config->PseAdcSbIntEn;
 182                 params->PchPseLh2PseSbInterruptEnable = config->PseLh2PseSbIntEn;
 183                 params->PchPseShellEnabled = config->PseShellEn;
 184
 185                 /*
 186                  * As a minimum requirement for PSE initialization, the configuration
 187                  * of devices below are required as shown.
 188                  * TODO: Help needed to find a better way to handle this part of code
 189                  * as the settings from devicetree are overwritten here.
 190                  *
 191                  * Set the ownership of these devices to PSE. These are hardcoded for now,
 192                  * if the PSE should be opened one day (hopefully), this can be handled
 193                  * much better.
 194                  */
 195                 params->PchPseDmaEnable[0] = PSE_Owned;
 196                 params->PchPseUartEnable[2] = PSE_Owned;
 197                 params->PchPseHsuartEnable[2] = PSE_Owned;
 198                 params->PchPseI2cEnable[2] = PSE_Owned;
 199                 params->PchPseTimedGpioEnable[0] = PSE_Owned;
 200                 params->PchPseTimedGpioEnable[1] = PSE_Owned;
 201                 /* Disable PSE DMA Sideband Interrupt for DMA 0 */
 202                 params->PchPseDmaSbInterruptEnable[0] = 0;
 203                 /* Set the log output to PSE UART 2 */
 204                 params->PchPseLogOutputChannel = 3;
 205         } else {
 206                 die("PSE enabled but PSE FW not available!\n");
 207         }
 208 }
 209
 210 static void parse_devicetree(FSP_S_CONFIG *params)
 211 {
 212         const struct soc_intel_elkhartlake_config *config = config_of_soc();
 213
 214         /* LPSS controllers configuration */
 215
 216         /* I2C */
 217         FSP_ARRAY_LOAD(params->SerialIoI2cMode, config->SerialIoI2cMode);
 218         FSP_ARRAY_LOAD(params->PchSerialIoI2cPadsTermination,
 219                 config->SerialIoI2cPadsTermination);
 220
 221         params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09;        //GPIO native mode for GPP_H9
 222         params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08;        //GPIO native mode for GPP_H8
 223
 224         /* GSPI */
 225         FSP_ARRAY_LOAD(params->SerialIoSpiMode, config->SerialIoGSpiMode);
 226         FSP_ARRAY_LOAD(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable);
 227         FSP_ARRAY_LOAD(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode);
 228         FSP_ARRAY_LOAD(params->SerialIoSpiCsState, config->SerialIoGSpiCsState);
 229         params->SerialIoSpiCsPolarity[2] = 0;
 230
 231         /* UART */
 232         FSP_ARRAY_LOAD(params->SerialIoUartMode, config->SerialIoUartMode);
 233         FSP_ARRAY_LOAD(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable);
 234
 235         params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F;    //GPIO native mode for GPP_T15
 236         params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E;    //GPIO native mode for GPP_T14
 237         params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C;     //GPIO native mode for GPP_T12
 238         params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D;     //GPIO native mode for GPP_T13
 239
 240         /* Provide correct UART number for FSP debug logs */
 241         params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
 242 }
 243
 244 /* UPD parameters to be initialized before SiliconInit */
 245 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 246 {
 247         unsigned int i;
 248
 249         FSP_S_CONFIG *params = &supd->FspsConfig;
 250         struct soc_intel_elkhartlake_config *config = config_of_soc();
 251
 252         /* Parse device tree and fill in FSP UPDs */
 253         parse_devicetree(params);
 254
 255         /* Load VBT before devicetree-specific config. */
 256         params->GraphicsConfigPtr = (uintptr_t)vbt_get();
 257
 258         /* Check if IGD is present and fill Graphics init param accordingly */
 259         params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 260
 261         /* Display config */
 262         params->DdiPortAConfig = config->DdiPortAConfig;
 263         params->DdiPortBConfig = config->DdiPortBConfig;
 264         params->DdiPortCConfig = config->DdiPortCConfig;
 265         params->DdiPortAHpd = config->DdiPortAHpd;
 266         params->DdiPortBHpd = config->DdiPortBHpd;
 267         params->DdiPortCHpd = config->DdiPortCHpd;
 268         params->DdiPort1Hpd = config->DdiPort1Hpd;
 269         params->DdiPort2Hpd = config->DdiPort2Hpd;
 270         params->DdiPort3Hpd = config->DdiPort3Hpd;
 271         params->DdiPort4Hpd = config->DdiPort4Hpd;
 272         params->DdiPortADdc = config->DdiPortADdc;
 273         params->DdiPortBDdc = config->DdiPortBDdc;
 274         params->DdiPortCDdc = config->DdiPortCDdc;
 275         params->DdiPort1Ddc = config->DdiPort1Ddc;
 276         params->DdiPort2Ddc = config->DdiPort2Ddc;
 277         params->DdiPort3Ddc = config->DdiPort3Ddc;
 278         params->DdiPort4Ddc = config->DdiPort4Ddc;
 279
 280         /* Intel Speed Step */
 281         params->Eist = config->eist_enable;
 282
 283         /* Use coreboot MP PPI services if Kconfig is enabled */
 284         if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
 285                 params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
 286
 287         /* Chipset Lockdown */
 288         if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
 289                 params->PchLockDownGlobalSmi = 0;
 290                 params->PchLockDownBiosLock = 0;
 291                 params->PchLockDownBiosInterface = 0;
 292                 params->PchWriteProtectionEnable[0] = 0;
 293                 params->PchUnlockGpioPads = 1;
 294                 params->RtcMemoryLock = 0;
 295                 params->SkipPamLock = 1;
 296         } else {
 297                 params->PchLockDownGlobalSmi = 1;
 298                 params->PchLockDownBiosLock = 1;
 299                 params->PchLockDownBiosInterface = 1;
 300                 params->PchWriteProtectionEnable[0] = 1;
 301                 params->PchUnlockGpioPads = 0;
 302                 params->RtcMemoryLock = 1;
 303                 params->SkipPamLock = 0;
 304         }
 305
 306         /* Disable PAVP */
 307         params->PavpEnable = 0;
 308
 309         /* Legacy 8254 timer support */
 310         bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
 311         params->Enable8254ClockGating = !use_8254;
 312         params->Enable8254ClockGatingOnS3 = 1;
 313
 314         /*
 315          * Legacy PM ACPI Timer (and TCO Timer)
 316          * This *must* be 1 in any case to keep FSP from
 317          *  1) enabling PM ACPI Timer emulation in uCode.
 318          *  2) disabling the PM ACPI Timer.
 319          * We handle both by ourself!
 320          */
 321         params->EnableTcoTimer = 1;
 322
 323         /* Set up recommended real time parameters if real time tuning is enabled. */
 324         if (config->realtime_tuning_enable) {
 325                 params->PchPostMasterClockGating = 0;
 326                 params->PchPostMasterPowerGating = 0;
 327                 params->PchPwrOptEnable = 0;
 328                 params->PsfTccEnable = 1;
 329                 params->PmcLpmS0ixSubStateEnableMask = 0;
 330                 params->PchDmiAspmCtrl = 0;
 331                 params->PchLegacyIoLowLatency = 0;
 332                 params->EnableItbm = 0;
 333                 params->D3ColdEnable = 0;
 334                 params->PmcOsIdleEnable = 0;
 335         } else {
 336                 params->PchPostMasterClockGating = 1;
 337                 params->PchPostMasterPowerGating = 1;
 338         }
 339         /* HECI */
 340         params->Heci3Enabled = config->Heci3Enable;
 341
 342         /* USB configuration */
 343         for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 344                 params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
 345                 params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
 346                 params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
 347                 params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
 348                 params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 349                 params->Usb2OverCurrentPin[i] = config->usb2_ports[i].enable ?
 350                         config->usb2_ports[i].ocpin : 0xff;
 351         }
 352
 353         for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 354                 params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 355                 params->Usb3OverCurrentPin[i] = config->usb3_ports[i].enable ?
 356                         config->usb3_ports[i].ocpin : 0xff;
 357                 if (config->usb3_ports[i].tx_de_emp) {
 358                         params->Usb3HsioTxDeEmphEnable[i] = 1;
 359                         params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
 360                 }
 361                 if (config->usb3_ports[i].tx_downscale_amp) {
 362                         params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
 363                         params->Usb3HsioTxDownscaleAmp[i] =
 364                                 config->usb3_ports[i].tx_downscale_amp;
 365                 }
 366         }
 367
 368         params->UsbClockGatingEnable = 1;
 369         params->UsbPowerGatingEnable = 1;
 370
 371         params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
 372
 373         /* PCIe root ports config */
 374         for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
 375                 params->PcieRpClkReqDetect[i] =
 376                         !config->PcieRpClkReqDetectDisable[i];
 377                 params->PcieRpL1Substates[i] =
 378                         get_l1_substate_control(config->PcieRpL1Substates[i]);
 379                 params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i];
 380                 params->PcieRpAdvancedErrorReporting[i] =
 381                         !config->PcieRpAdvancedErrorReportingDisable[i];
 382                 params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
 383                 params->PciePtm[i] = config->PciePtm[i];
 384                 params->PcieRpPcieSpeed[i] = config->PcieRpPcieSpeed[i];
 385                 params->PcieRpLtrMaxNoSnoopLatency[i] = 0x1003;
 386                 params->PcieRpLtrMaxSnoopLatency[i] = 0x1003;
 387                 /* Virtual Channel 1 to Traffic Class mapping */
 388                 params->PcieRpVc1TcMap[i] = 0x60;
 389                 if (config->realtime_tuning_enable)
 390                         params->PcieRpEnableCpm[i] = 0;
 391                 params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
 392         }
 393
 394         /* SATA config */
 395         params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
 396         if (params->SataEnable) {
 397                 params->SataMode = config->SataMode;
 398                 params->SataSalpSupport = config->SataSalpSupport;
 399                 params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
 400                 params->SataSpeedLimit = config->SataSpeed;
 401
 402                 for (i = 0; i < CONFIG_MAX_SATA_PORTS; i++) {
 403                         params->SataPortsEnable[i] = config->SataPortsEnable[i];
 404                         params->SataPortsDevSlp[i] = config->SataPortsDevSlp[i];
 405                         params->SataPortsSolidStateDrive[i] = config->SataPortsSSD[i];
 406                         if (config->SataPortsEnableDitoConfig[i]) {
 407                                 params->SataPortsDmVal[i] =
 408                                         config->SataPortsDmVal[i] ? : DEF_DMVAL;
 409                                 params->SataPortsDitoVal[i] =
 410                                         config->SataPortsDitoVal[i] ? : DEF_DITOVAL_MS;
 411                         }
 412                 }
 413         }
 414
 415         /* SDCard config */
 416         params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
 417         if (params->ScsSdCardEnabled) {
 418                 params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
 419                 params->SdCardGpioCmdPadTermination = GPIO_TERM_NATIVE;
 420                 params->SdCardGpioDataPadTermination[0] = GPIO_TERM_NATIVE;
 421                 params->SdCardGpioDataPadTermination[1] = GPIO_TERM_NATIVE;
 422                 params->SdCardGpioDataPadTermination[2] = GPIO_TERM_NATIVE;
 423                 params->SdCardGpioDataPadTermination[3] = GPIO_TERM_NATIVE;
 424         }
 425
 426         /* eMMC config */
 427         params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
 428         if (params->ScsEmmcEnabled) {
 429                 params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
 430                 params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled;
 431         }
 432
 433         /* Thermal config */
 434         params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
 435         params->ProcHotResponse = 0x0;  //Disable PROCHOT response
 436         /* Thermal sensor (TS) target width */
 437         params->DmiTS0TW = 3;
 438         params->DmiTS1TW = 2;
 439         params->DmiTS2TW = 1;
 440         /* Enable memory thermal throttling by default */
 441         if (!config->MemoryThermalThrottlingDisable) {
 442                 params->PchMemoryPmsyncEnable[0] = 1;
 443                 params->PchMemoryPmsyncEnable[1] = 1;
 444                 params->PchMemoryC0TransmitEnable[0] = 1;
 445                 params->PchMemoryC0TransmitEnable[1] = 1;
 446         }
 447
 448         /* TccActivationOffset config */
 449         params->TccActivationOffset = config->tcc_offset;
 450         params->TccOffsetClamp = config->tcc_offset_clamp;
 451         params->TccOffsetLock = 0x1;    //lock Tcc Offset register
 452
 453         /* Power management config */
 454         params->ImonSlope[0] = IMON_SLOPE;
 455         params->ImonOffset[0] = IMON_OFFSET;
 456         params->TdcCurrentLimit[0] = TDC_CURRENT_LIMIT_MAX;
 457         params->AcLoadline[0] = AC_LOADLINE_LANE_0_MAX;
 458         params->DcLoadline[0] = DC_LOADLINE_LANE_0_MAX;
 459         params->AcLoadline[1] = AC_LOADLINE_LANE_1_MAX;
 460         params->DcLoadline[1] = DC_LOADLINE_LANE_1_MAX;
 461         params->IccMax[0] = ICC_LIMIT_MAX;
 462         params->OneCoreRatioLimit = CORE_RATIO_LIMIT;
 463         params->TwoCoreRatioLimit = CORE_RATIO_LIMIT;
 464         params->ThreeCoreRatioLimit = CORE_RATIO_LIMIT;
 465         params->FourCoreRatioLimit = CORE_RATIO_LIMIT;
 466         params->FiveCoreRatioLimit = CORE_RATIO_LIMIT;
 467         params->SixCoreRatioLimit = CORE_RATIO_LIMIT;
 468         params->SevenCoreRatioLimit = CORE_RATIO_LIMIT;
 469         params->EightCoreRatioLimit = CORE_RATIO_LIMIT;
 470         params->PsysPmax = 0;   //Set max platform power to auto profile
 471         params->Custom1TurboActivationRatio = 0;
 472         params->Custom2TurboActivationRatio = 0;
 473         params->Custom3TurboActivationRatio = 0;
 474         params->PchPwrOptEnable = 0x1;  //Enable PCH DMI Power Optimizer
 475         params->TStates = 0x0;  //Disable T state
 476         params->PkgCStateLimit = 0x7;   //Set C state limit to C9
 477         params->FastPkgCRampDisable[0] = 0x1;
 478         params->SlowSlewRate[0] = 0x1;
 479         params->MaxRatio = 0x8; //Set max P state ratio
 480         params->PchEspiLgmrEnable = 0;
 481         params->PchPmPwrBtnOverridePeriod = config->PchPmPwrBtnOverridePeriod;
 482         params->PchS0ixAutoDemotion = 0;
 483         params->PmcV1p05PhyExtFetControlEn = 0x1;
 484         params->PmcV1p05IsExtFetControlEn = 0x1;
 485         /* FIVR config */
 486         if (config->fivr.fivr_config_en) {
 487                 fill_fsps_fivr_params(params, config);
 488         }
 489
 490         /* FuSa (Functional Safety) config */
 491         if (!config->FuSaEnable) {
 492                 params->DisplayFusaConfigEnable = 0;
 493                 params->GraphicFusaConfigEnable = 0;
 494                 params->OpioFusaConfigEnable = 0;
 495                 params->PsfFusaConfigEnable = 0;
 496         }
 497
 498         /* PSE (Intel Programmable Services Engine) config */
 499         if (CONFIG(PSE_ENABLE) && cbfs_file_exists("pse.bin"))
 500                 fill_fsps_pse_params(params, config);
 501
 502         /* TSN GBE config */
 503         fill_fsps_tsn_params(params, config);
 504
 505         /* Override/Fill FSP Silicon Param for mainboard */
 506         mainboard_silicon_init_params(params);
 507 }
 508
 509 /* Mainboard GPIO Configuration */
 510 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 511 {
 512         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 513 }