mb/system76/cml-u/dt: Make use of chipset devicetree
[coreboot.git] / src / soc / intel / elkhartlake / systemagent.c
blob9eadf89c5775e1ce05656ad6e1fdf32d1e1fae9e
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <delay.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ops.h>
7 #include <intelblocks/power_limit.h>
8 #include <intelblocks/systemagent.h>
9 #include <soc/iomap.h>
10 #include <soc/soc_chip.h>
11 #include <soc/systemagent.h>
14 * SoC implementation
16 * Add all known fixed memory ranges for Host Controller/Memory
17 * controller.
19 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
21 static const struct sa_mmio_descriptor soc_fixed_resources[] = {
22 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
23 "PCIEXBAR" },
24 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
25 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
26 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
27 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
28 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
31 sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
32 ARRAY_SIZE(soc_fixed_resources));
34 /* Add Vt-d resources if VT-d is enabled */
35 if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
36 return;
38 sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
39 ARRAY_SIZE(soc_vtd_resources));
43 * SoC implementation
45 * Perform System Agent Initialization during Ramstage phase.
47 void soc_systemagent_init(struct device *dev)
49 struct soc_power_limits_config *soc_config;
50 config_t *config;
52 /* Enable Power Aware Interrupt Routing */
53 enable_power_aware_intr();
55 /* Enable BIOS Reset CPL */
56 enable_bios_reset_cpl();
58 mdelay(1);
60 config = config_of_soc();
61 soc_config = &config->power_limits_config;
62 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);