mb/system76/cml-u/dt: Make use of chipset devicetree
[coreboot.git] / src / soc / intel / jasperlake / acpi / southbridge.asl
bloba463304228a30e458590996b10caa877701edc6c
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <intelblocks/itss.h>
4 #include <intelblocks/pcr.h>
5 #include <soc/itss.h>
6 #include <soc/pcr_ids.h>
8 /* PCI IRQ assignment */
9 #include "pci_irqs.asl"
11 /* PCR access */
12 #include <soc/intel/common/acpi/pch_pcr.asl>
14 /* PCH clock */
15 #include "camera_clock_ctl.asl"
17 /* GPIO controller */
18 #include "gpio.asl"
20 /* ESPI 0:1f.0 */
21 #include <soc/intel/common/block/acpi/acpi/lpc.asl>
23 /* PCH HDA */
24 #include "pch_hda.asl"
26 /* PCIE Ports */
27 #include "pcie.asl"
29 /* pmc 0:1f.2 */
30 #include "pmc.asl"
32 /* Serial IO */
33 #include "serialio.asl"
35 /* SMBus 0:1f.4 */
36 #include <soc/intel/common/block/acpi/acpi/smbus.asl>
38 /* ISH 0:12.0 */
39 #include <soc/intel/common/block/acpi/acpi/ish.asl>
41 /* USB XHCI 0:14.0 */
42 #include "xhci.asl"
44 /* PCI _OSC */
45 #include <soc/intel/common/acpi/pci_osc.asl>
47 /* EMMC/SD card */
48 #include "scs.asl"
50 /* GbE 0:1f.6 */
51 #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>