src/soc/intel/xeon_sp/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpigen.h>
   4 #include <assert.h>
   5 #include <intelblocks/acpi.h>
   6 #include <soc/chip_common.h>
   7 #include <soc/pci_devs.h>
   8 #include <soc/util.h>
   9 #include <stdint.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12
  13 #include "chip.h"
  14
  15 /*
  16  * List of supported C-states in this processor.
  17  */
  18 enum {
  19         C_STATE_C1,     /* 0 */
  20         C_STATE_C3,     /* 1 */
  21         C_STATE_C6,     /* 2 */
  22         C_STATE_C7,     /* 3 */
  23         NUM_C_STATES
  24 };
  25
  26 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  27         [C_STATE_C1] = {
  28                 /* C1 */
  29                 .latency = 1,
  30                 .power = 0x3e8,
  31                 .resource = MWAIT_RES(0, 0),
  32         },
  33         [C_STATE_C3] = {
  34                 /* C3 */
  35                 .latency = 15,
  36                 .power = 0x1f4,
  37                 .resource = MWAIT_RES(1, 0),
  38         },
  39         [C_STATE_C6] = {
  40                 /* C6 */
  41                 .latency = 41,
  42                 .power = 0x15e,
  43                 .resource = MWAIT_RES(2, 0),
  44         },
  45         [C_STATE_C7] = {
  46                 /* C7 */
  47                 .latency = 41,
  48                 .power = 0x0c8,
  49                 .resource = MWAIT_RES(3, 0),
  50         }
  51 };
  52
  53 /* Max states supported */
  54 static int cstate_set_all[] = {
  55         C_STATE_C1,
  56         C_STATE_C3,
  57         C_STATE_C6,
  58         C_STATE_C7
  59 };
  60
  61 static int cstate_set_c1_c6[] = {
  62         C_STATE_C1,
  63         C_STATE_C6,
  64 };
  65
  66 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
  67 {
  68         static acpi_cstate_t map[ARRAY_SIZE(cstate_set_all)];
  69         int *cstate_set;
  70         int i;
  71
  72         const config_t *config = config_of_soc();
  73
  74         const enum acpi_cstate_mode states = config->cstate_states;
  75
  76         switch (states) {
  77         case CSTATES_C1C6:
  78                 *entries = ARRAY_SIZE(cstate_set_c1_c6);
  79                 cstate_set = cstate_set_c1_c6;
  80                 break;
  81         case CSTATES_ALL:
  82         default:
  83                 *entries = ARRAY_SIZE(cstate_set_all);
  84                 cstate_set = cstate_set_all;
  85                 break;
  86         }
  87
  88         for (i = 0; i < *entries; i++) {
  89                 map[i] = cstate_map[cstate_set[i]];
  90                 map[i].ctype = i + 1;
  91         }
  92         return map;
  93 }
  94
  95 void iio_domain_set_acpi_name(struct device *dev, const char *prefix)
  96 {
  97         const union xeon_domain_path dn = {
  98                 .domain_path = dev->path.domain.domain
  99         };
 100
 101         assert(dn.socket < CONFIG_MAX_SOCKET);
 102         assert(dn.stack < 16);
 103         assert(prefix != NULL && strlen(prefix) == 2);
 104
 105         if (dn.socket >= CONFIG_MAX_SOCKET || dn.stack >= 16 ||
 106             !prefix || strlen(prefix) != 2)
 107                 return;
 108
 109         char *name = xmalloc(ACPI_NAME_BUFFER_SIZE);
 110         snprintf(name, ACPI_NAME_BUFFER_SIZE, "%s%1X%1X", prefix, dn.socket, dn.stack);
 111         dev->name = name;
 112 }
 113
 114 const char *soc_acpi_name(const struct device *dev)
 115 {
 116         if (dev->path.type == DEVICE_PATH_DOMAIN)
 117                 return dev->name;
 118
 119         /* FIXME: Add SoC specific device names here */
 120
 121         return NULL;
 122 }
 123
 124 void acpigen_write_OSC_pci_domain_fixed_caps(const struct device *domain,
 125                                 const uint32_t granted_pcie_features,
 126                                 const bool is_cxl_domain,
 127                                 const uint32_t granted_cxl_features)
 128 {
 129         acpigen_write_method("_OSC", 4);
 130
 131         acpigen_write_return_namestr("\\_SB.POSC");
 132         acpigen_emit_byte(ARG0_OP);
 133         acpigen_emit_byte(ARG1_OP);
 134         acpigen_emit_byte(ARG2_OP);
 135         acpigen_emit_byte(ARG3_OP);
 136         acpigen_write_integer(granted_pcie_features);
 137         acpigen_write_integer(is_cxl_domain);
 138         acpigen_write_integer(granted_cxl_features);
 139
 140         acpigen_pop_len();
 141 }