mb/system76/cml-u/dt: Make use of chipset devicetree
[coreboot.git] / src / soc / intel / xeon_sp / skx / chip.c
blob37535a3cf02107a52aa61084bbfacce457664f9d
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #include <acpi/acpigen_pci.h>
3 #include <cbfs.h>
4 #include <console/console.h>
5 #include <device/pci.h>
6 #include <gpio.h>
7 #include <intelblocks/acpi.h>
8 #include <soc/acpi.h>
9 #include <soc/chip_common.h>
10 #include <soc/numa.h>
11 #include <soc/pch.h>
12 #include <soc/soc_pch.h>
13 #include <soc/ramstage.h>
14 #include <soc/soc_util.h>
15 #include <soc/util.h>
17 static struct device_operations cpu_bus_ops = {
18 .read_resources = noop_read_resources,
19 .set_resources = noop_set_resources,
20 .init = mp_cpu_bus_init,
21 #if CONFIG(HAVE_ACPI_TABLES)
22 /* defined in src/soc/intel/common/block/acpi/acpi.c */
23 .acpi_fill_ssdt = generate_cpu_entries,
24 #endif
27 static void soc_enable_dev(struct device *dev)
29 /* Set the operations if it is a special bus type */
30 if (dev->path.type == DEVICE_PATH_DOMAIN) {
31 /* domain ops are assigned at their creation */
32 } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
33 dev->ops = &cpu_bus_ops;
34 } else if (dev->path.type == DEVICE_PATH_GPIO) {
35 block_gpio_enable(dev);
39 static void soc_init(void *data)
41 unlock_pam_regions();
43 printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
44 fsp_silicon_init();
46 setup_pds();
47 attach_iio_stacks();
49 override_hpet_ioapic_bdf();
50 pch_lock_dmictl();
53 static void soc_final(void *data)
55 // Temp Fix - should be done by FSP, in 2S bios completion
56 // is not carried out on socket 2
57 set_bios_init_completion();
60 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
62 const struct microcode *microcode_file;
63 size_t microcode_len;
65 microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len);
67 if ((microcode_file) && (microcode_len != 0)) {
68 /* Update CPU Microcode patch base address/size */
69 silupd->FspsConfig.PcdCpuMicrocodePatchBase =
70 (uint32_t)microcode_file;
71 silupd->FspsConfig.PcdCpuMicrocodePatchSize =
72 (uint32_t)microcode_len;
75 mainboard_silicon_init_params(silupd);
78 struct chip_operations soc_intel_xeon_sp_skx_ops = {
79 .name = "Intel Skylake-SP",
80 .enable_dev = soc_enable_dev,
81 .init = soc_init,
82 .final = soc_final
85 struct pci_operations soc_pci_ops = {
86 .set_subsystem = pci_dev_set_subsystem,