src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb

   1 chip soc/intel/apollolake
   2
   3         device cpu_cluster 0 on
   4                 device lapic 0 on end
   5         end
   6
   7         register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
   8         # Disable unused clkreq of PCIe root ports
   9         register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt
  10         register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
  11         register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
  12         register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
  13         register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
  14
  15         # GPIO for PERST_0
  16         # If the Board has PERST_0 signal, assign the GPIO
  17         # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
  18         register "prt0_gpio" = "GPIO_163"
  19
  20         # GPIO for SD card detect
  21         register "sdcard_cd_gpio" = "GPIO_186"
  22
  23         # EMMC TX DATA Delay 1
  24         # Refer to EDS-Vol2-22.3.
  25         # [14:8] steps of delay for HS400, each 125ps.
  26         # [6:0] steps of delay for SDR104/HS200, each 125ps.
  27         register "emmc_tx_data_cntl1" = "0x0C3A"
  28
  29         # EMMC TX DATA Delay 2
  30         # Refer to EDS-Vol2-22.3.
  31         # [30:24] steps of delay for SDR50, each 125ps.
  32         # [22:16] steps of delay for DDR50, each 125ps.
  33         # [14:8] steps of delay for SDR25/HS50, each 125ps.
  34         # [6:0] steps of delay for SDR12, each 125ps.
  35         register "emmc_tx_data_cntl2" = "0x28272929"
  36
  37         # EMMC RX CMD/DATA Delay 1
  38         # Refer to EDS-Vol2-22.3.
  39         # [30:24] steps of delay for SDR50, each 125ps.
  40         # [22:16] steps of delay for DDR50, each 125ps.
  41         # [14:8] steps of delay for SDR25/HS50, each 125ps.
  42         # [6:0] steps of delay for SDR12, each 125ps.
  43         register "emmc_rx_cmd_data_cntl1" = "0x003B263B"
  44
  45         # EMMC RX CMD/DATA Delay 2
  46         # Refer to EDS-Vol2-22.3.
  47         # [17:16] stands for Rx Clock before Output Buffer
  48         # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
  49         # [6:0] steps of delay for HS200, each 125ps.
  50         register "emmc_rx_cmd_data_cntl2" = "0x10008"
  51
  52         register "emmc_rx_strobe_cntl" = "0x0a0a"
  53         register "emmc_tx_cmd_cntl" = "0x1305"
  54
  55         # Enable DPTF
  56         register "dptf_enable" = "1"
  57
  58         # PL1 override: 7.5W setting gives a run-time 6W actual
  59         # Set RAPL PL2 to 15W.
  60         register "power_limits_config" = "{
  61                 .tdp_pl1_override = 7,
  62                 .tdp_pl2_override = 15,
  63         }"
  64
  65         # Enable Audio Clock and Power gating
  66         register "hdaudio_clk_gate_enable" = "1"
  67         register "hdaudio_pwr_gate_enable" = "1"
  68         register "hdaudio_bios_config_lockdown" = "1"
  69
  70         # Enable lpss s0ix
  71         register "lpss_s0ix_enable" = "1"
  72
  73         # GPE configuration
  74         # Note that GPE events called out in ASL code rely on this
  75         # route, i.e., if this route changes then the affected GPE
  76         # offset bits also need to be changed. This sets the PMC register
  77         # GPE_CFG fields.
  78         #PMC_GPE_NW_63_32 - 03
  79         #PMC_GPE_N_95_64  - 08
  80         #PMC_GPE_NW_31_0  - 02
  81         register "gpe0_dw1" = "PMC_GPE_NW_63_32"
  82         register "gpe0_dw2" = "PMC_GPE_N_95_64"
  83         register "gpe0_dw3" = "PMC_GPE_NW_31_0"
  84
  85         # Intel Common SoC Config
  86         #+-------------------+---------------------------+
  87         #| Field             |  Value                    |
  88         #+-------------------+---------------------------+
  89         #| I2C0              | Audio                     |
  90         #+-------------------+---------------------------+
  91         register "common_soc_config" = "{
  92                 .i2c[0] = {
  93                         .speed = I2C_SPEED_FAST,
  94                         .rise_time_ns = 104,
  95                         .fall_time_ns = 52,
  96                 },
  97         }"
  98
  99         # Minimum SLP S3 assertion width 28ms.
 100         register "slp_s3_assertion_width_usecs" = "28000"
 101
 102         register "pnp_settings" = "PNP_PERF_POWER"
 103
 104         device domain 0 on
 105                 device pci 00.0 on  end # - Host Bridge
 106                 device pci 00.1 on  end # - DPTF
 107                 device pci 00.2 on  end # - NPK
 108                 device pci 02.0 on  end # - Gen
 109                 device pci 03.0 on  end # - Iunit
 110                 device pci 0c.0 on  end # - CNVi
 111                 device pci 0d.0 on  end # - P2SB
 112                 device pci 0d.1 on  end # - PMC
 113                 device pci 0d.2 on  end # - SPI
 114                 device pci 0d.3 on  end # - Shared SRAM
 115                 device pci 0e.0 on      # - Audio
 116                         chip drivers/generic/max98357a
 117                                 register "hid" = ""MX98357A""
 118                                 register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_160)"
 119                                 register "sdmode_delay" = "5"
 120                                 device generic 0 on end
 121                         end
 122                 end
 123                 device pci 0f.0 on  end # - Heci1
 124                 device pci 0f.1 on  end # - Heci2
 125                 device pci 0f.2 on  end # - Heci3
 126                 device pci 11.0 off end # - ISH
 127                 device pci 12.0 on      # - SATA
 128                         register "SataPortsEnable[0]" = "1"
 129                         register "SataPortsEnable[1]" = "1"
 130                 end
 131                 device pci 13.0 off end # - PCIe-A 0 Slot 1
 132                 device pci 13.1 off end # - PCIe-A 1
 133                 device pci 13.2 off end # - PCIe-A 2 Onboard Lan
 134                 device pci 13.3 off end # - PCIe-A 3
 135                 device pci 14.0 off  end # - PCIe-B 0 Slot2
 136                 device pci 14.1 on  end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT)
 137                 device pci 15.0 on  end # - XHCI
 138                 device pci 15.1 off end # - XDCI
 139                 device pci 16.0 on      # - I2C 0
 140                         chip drivers/i2c/da7219
 141                                 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_20_IRQ)"
 142                                 register "btn_cfg" = "50"
 143                                 register "mic_det_thr" = "500"
 144                                 register "jack_ins_deb" = "20"
 145                                 register "jack_det_rate" = ""32ms_64ms""
 146                                 register "jack_rem_deb" = "1"
 147                                 register "a_d_btn_thr" = "0xa"
 148                                 register "d_b_btn_thr" = "0x16"
 149                                 register "b_c_btn_thr" = "0x21"
 150                                 register "c_mic_btn_thr" = "0x3e"
 151                                 register "btn_avg" = "4"
 152                                 register "adc_1bit_rpt" = "1"
 153                                 register "micbias_lvl" = "2600"
 154                                 register "mic_amp_in_sel" = ""diff""
 155                                 device i2c 1a on end
 156                         end
 157                 end
 158                 device pci 16.1 off end # - I2C 1
 159                 device pci 16.2 off end # - I2C 2
 160                 device pci 16.3 off end # - I2C 3
 161                 device pci 17.0 on
 162                         chip drivers/i2c/hid
 163                                 register "generic.hid" = ""ALPS0001""
 164                                 register "generic.desc" = ""Touchpad""
 165                                 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
 166                                 register "hid_desc_reg_offset" = "0x1"
 167                                 device i2c 2C on end
 168                         end
 169                 end # I2C 4
 170                 device pci 17.1 off end # - I2C 5
 171                 device pci 17.2 off end # - I2C 6
 172                 device pci 17.3 on  end # - I2C 7
 173                 device pci 18.0 on  end # - UART 0
 174                 device pci 18.1 off end # - UART 1
 175                 device pci 18.2 on  end # - UART 2
 176                 device pci 18.3 off end # - UART 3
 177                 device pci 19.0 on  end # - SPI 0
 178                 device pci 19.1 on  end # - SPI 1
 179                 device pci 19.2 on  end # - SPI 2
 180                 device pci 1a.0 on  end # - PWM
 181                 device pci 1b.0 on  end # - SDCARD
 182                 device pci 1c.0 on  end # - eMMC
 183                 device pci 1d.0 on  end # - UFS
 184                 device pci 1e.0 off end # - SDIO
 185                 device pci 1f.0 on      # - LPC
 186                         chip drivers/pc80/tpm
 187                         register "irq_polarity" = "2"
 188                         device pnp 0c31.0 on
 189                                 irq 0x70 = 10
 190                                 end
 191                         end
 192                         chip ec/google/chromeec
 193                                 device pnp 0c09.0 on end
 194                         end
 195                 end
 196                 device pci 1f.1 on  end # - SMBUS
 197         end
 198 end