src/mainboard/intel/adlrvp/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/cpu.h>
   4 #include <baseboard/gpio.h>
   5 #include <baseboard/variants.h>
   6 #include <cpu/intel/cpu_ids.h>
   7 #include <device/device.h>
   8 #include <drivers/intel/gma/opregion.h>
   9 #include <ec/ec.h>
  10 #include <soc/gpio.h>
  11 #include <smbios.h>
  12 #include <stdint.h>
  13 #include <string.h>
  14 #include "board_id.h"
  15 #include <fw_config.h>
  16
  17 const char *smbios_system_sku(void)
  18 {
  19         static char sku_str[7] = "";
  20         uint8_t sku_id = get_board_id();
  21
  22         snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
  23         return sku_str;
  24 }
  25
  26 static void mainboard_init(void *chip_info)
  27 {
  28         variant_configure_gpio_pads();
  29
  30         if (CONFIG(EC_GOOGLE_CHROMEEC))
  31                 mainboard_ec_init();
  32
  33         variant_devtree_update();
  34 }
  35
  36 void __weak variant_devtree_update(void)
  37 {
  38         /* Override dev tree settings per board */
  39 }
  40
  41 #if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
  42 static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
  43 {
  44         struct smbios_type11 *t;
  45         char buffer[64];
  46
  47         t = (struct smbios_type11 *)arg;
  48
  49         snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name);
  50         t->count = smbios_add_string(t->eos, buffer);
  51 }
  52
  53 static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t)
  54 {
  55         fw_config_for_each_found(add_fw_config_oem_string, t);
  56 }
  57 #endif
  58
  59 static void mainboard_enable(struct device *dev)
  60 {
  61 #if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
  62         dev->ops->get_smbios_strings = mainboard_smbios_strings;
  63 #endif
  64 }
  65
  66 struct chip_operations mainboard_ops = {
  67         .init = mainboard_init,
  68         .enable_dev = mainboard_enable,
  69 };
  70
  71 const char *mainboard_vbt_filename(void)
  72 {
  73         if (!CONFIG(CHROMEOS))
  74                 return "vbt.bin";
  75
  76         uint32_t cpu_id = cpu_get_cpuid();
  77         uint8_t sku_id = get_board_id();
  78         switch (sku_id) {
  79         case ADL_P_LP5_1:
  80         case ADL_P_LP5_2:
  81                 if (cpu_id == CPUID_RAPTORLAKE_P_J0)
  82                         return "vbt_adlrvp_rpl_lp5.bin";
  83                 return "vbt_adlrvp_lp5.bin";
  84         case ADL_M_LP5:
  85                 return "vbt_adlrvp_m_lp5.bin";
  86         case ADL_P_DDR5_1:
  87         case ADL_P_DDR5_2:
  88                 return "vbt_adlrvp_ddr5.bin";
  89         case ADL_M_LP4:
  90                 return "vbt_adlrvp_m_lp4.bin";
  91         default:
  92                 return "vbt.bin";
  93         }
  94 }