1 config SOC_INTEL_TIGERLAKE
4 Intel Tigerlake support
6 config SOC_INTEL_TIGERLAKE_PCH_H
11 config CPU_SPECIFIC_OPTIONS
13 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
15 select BOOT_DEVICE_SUPPORTS_WRITES
16 select CACHE_MRC_SETTINGS
17 select CPU_INTEL_COMMON
18 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
19 select CPU_SUPPORTS_INTEL_TME
20 select CPU_SUPPORTS_PM_TIMER_EMULATION
21 select DISPLAY_FSP_VERSION_INFO if !FSP_TYPE_IOT
22 select DRIVERS_USB_ACPI
23 select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
24 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
25 select FSP_COMPRESS_FSP_S_LZ4
27 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
28 select GENERIC_GPIO_LIB
30 select HAVE_HYPERTHREADING
31 select HAVE_INTEL_FSP_REPO
32 select INTEL_DESCRIPTOR_MODE_CAPABLE
33 select HAVE_SMI_HANDLER
34 select IDT_IN_EVERY_STAGE
35 select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM
36 select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED
37 select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
38 select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED
40 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
41 select MP_SERVICES_PPI_V1
42 select MRC_SETTINGS_PROTECT
43 select PARALLEL_MP_AP_WORK
44 select PLATFORM_USES_FSP2_2
45 select PMC_GLOBAL_RESET_ENABLE_LOCK
46 select SOC_INTEL_COMMON
47 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
48 select SOC_INTEL_COMMON_BLOCK
49 select SOC_INTEL_COMMON_BLOCK_ACPI
50 select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
51 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
52 select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
53 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
54 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
55 select SOC_INTEL_COMMON_BLOCK_CAR
56 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
57 select SOC_INTEL_COMMON_BLOCK_CNVI
58 select SOC_INTEL_COMMON_BLOCK_CPU
59 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
60 select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
61 select SOC_INTEL_COMMON_BLOCK_DTT
62 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
63 select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
64 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
65 select SOC_INTEL_COMMON_BLOCK_HDA
66 select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
67 select SOC_INTEL_COMMON_BLOCK_IRQ
68 select SOC_INTEL_COMMON_BLOCK_MEMINIT
69 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
70 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
71 select SOC_INTEL_COMMON_BLOCK_SA
72 select SOC_INTEL_COMMON_BLOCK_SMM
73 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
74 select SOC_INTEL_COMMON_BLOCK_TCSS
75 select SOC_INTEL_COMMON_BLOCK_USB4
76 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
77 select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
78 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
79 select SOC_INTEL_COMMON_FSP_RESET
80 select SOC_INTEL_COMMON_PCH_CLIENT
81 select SOC_INTEL_COMMON_RESET
82 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
83 select SOC_INTEL_CSE_SET_EOP
84 select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
86 select SUPPORT_CPU_UCODE_IN_CBFS
87 select TSC_MONOTONIC_TIMER
89 select UDK_2017_BINDING
90 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
91 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
92 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
93 select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
94 select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50
98 default 16 if SOC_INTEL_TIGERLAKE_PCH_H
104 config DCACHE_RAM_BASE
107 config DCACHE_RAM_SIZE
110 The size of the cache-as-ram region required during bootblock
113 config DCACHE_BSP_STACK_SIZE
117 The amount of anticipated stack usage in CAR by bootblock and
118 other stages. In the case of FSP_USES_CB_STACK default value will be
119 sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement
122 config FSP_TEMP_RAM_SIZE
126 The amount of anticipated heap usage in CAR by FSP.
127 Refer to Platform FSP integration guide document to know
128 the exact FSP requirement for Heap setup.
130 config CHIPSET_DEVICETREE
132 default "soc/intel/tigerlake/chipset_pch_h.cb" if SOC_INTEL_TIGERLAKE_PCH_H
133 default "soc/intel/tigerlake/chipset.cb"
135 config EXT_BIOS_WIN_BASE
138 config EXT_BIOS_WIN_SIZE
145 config IED_REGION_SIZE
156 config MAX_ROOT_PORTS
158 default 24 if SOC_INTEL_TIGERLAKE_PCH_H
161 config MAX_PCIE_CLOCK_SRC
163 default 16 if SOC_INTEL_TIGERLAKE_PCH_H
170 config SMM_RESERVED_SIZE
174 config PCR_BASE_ADDRESS
178 This option allows you to select MMIO Base Address of sideband bus.
180 config ECAM_MMCONF_BASE_ADDRESS
187 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
194 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
198 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
202 config SOC_INTEL_I2C_DEV_MAX
206 config SOC_INTEL_TIGERLAKE_S3
210 Select if using S3 instead of S0ix to disable D3Cold
212 config SOC_INTEL_UART_DEV_MAX
216 config CONSOLE_UART_BASE_ADDRESS
219 depends on INTEL_LPSS_UART_FOR_CONSOLE
221 # Clock divider parameters for 115200 baud rate
222 # Baudrate = (UART source clock * M) /(N *16)
223 # TGL UART source clock: 100MHz
224 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
228 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
232 config VBT_DATA_SIZE_KB
237 select VBOOT_MUST_REQUEST_DISPLAY
238 select VBOOT_STARTS_IN_BOOTBLOCK
239 select VBOOT_VBNV_CMOS
240 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
249 This option allows to select FSP IOT type from 3rdparty/fsp repo
251 config FSP_TYPE_CLIENT
253 default !FSP_TYPE_IOT
255 This option allows to select FSP CLIENT type from 3rdparty/fsp repo
257 config FSP_HEADER_PATH
258 default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Include/" if FSP_TYPE_IOT
259 default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Include/" if FSP_TYPE_CLIENT
262 default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Fsp.fd" if FSP_TYPE_IOT
263 default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Fsp.fd" if FSP_TYPE_CLIENT
265 config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT
266 int "Debug Consent for TGL"
267 # USB DBC is more common for developers so make this default to 3 if
268 # SOC_INTEL_DEBUG_CONSENT=y
269 default 3 if SOC_INTEL_DEBUG_CONSENT
272 This is to control debug interface on SOC.
273 Setting non-zero value will allow to use DBC or DCI to debug SOC.
274 PlatformDebugConsent in FspmUpd.h has the details.
276 Desired platform debug type are
277 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
278 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
279 6:Enable (2-wire DCI OOB), 7:Manual
281 config PRERAM_CBMEM_CONSOLE_SIZE
285 config DATA_BUS_WIDTH
289 config DIMMS_PER_CHANNEL
293 config MRC_CHANNEL_WIDTH
297 # Intel recommends reserving the following resources per USB4 root port,
298 # from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5
300 # - 194 MiB Non-prefetchable memory
301 # - 448 MiB Prefetchable memory
302 if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
304 config PCIEXP_HOTPLUG_BUSES
307 config PCIEXP_HOTPLUG_MEM
308 default 0xc200000 # 194 MiB
310 config PCIEXP_HOTPLUG_PREFETCH_MEM
311 default 0x1c000000 # 448 MiB
313 endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
315 config INTEL_GMA_BCLV_OFFSET
318 config INTEL_GMA_BCLV_WIDTH
321 config INTEL_GMA_BCLM_OFFSET
324 config INTEL_GMA_BCLM_WIDTH