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soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / brya / variants / trulo / overridetree.cb
blob631fe7b8d8ac93e8b956c4ce81ca2689fceb6459
1 fw_config
2 field THERMAL_SOLUTION 0 0
3 option THERMAL_SOLUTION_6W 0
4 option THERMAL_SOLUTION_15W 1
5 end
6 field PDC_CONTROL 1 2
7 option PDC_CONTROL_UNKNOWN 0
8 option PDC_RTS_BYPASS 1
9 option PDC_TI_BYPASS 2
10 end
11 field STORAGE 30 31
12 option STORAGE_EMMC 0
13 option STORAGE_NVME 1
14 option STORAGE_UFS 2
15 option STORAGE_UNKNOWN 3
16 end
17 end
18
19 chip soc/intel/alderlake
20 register "sagv" = "SaGv_Enabled"
21
22 # S0ix enable
23 register "s0ix_enable" = "true"
24
25 # DPTF enable
26 register "dptf_enable" = "1"
27
28 register "tcc_offset" = "10" # TCC of 90
29
30 # Enable CNVi BT
31 register "cnvi_bt_core" = "true"
32
33 # eMMC HS400
34 register "emmc_enable_hs400_mode" = "true"
35
36 #eMMC DLL tuning parameters
37 # EMMC Tx CMD Delay
38 # Refer to EDS-Vol2-42.3.7.
39 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
40 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
41 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
42
43 # EMMC TX DATA Delay 1
44 # Refer to EDS-Vol2-42.3.8.
45 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
46 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
47 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
48
49 # EMMC TX DATA Delay 2
50 # Refer to EDS-Vol2-42.3.9.
51 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
52 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
53 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
54 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
55 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
56
57 # EMMC RX CMD/DATA Delay 1
58 # Refer to EDS-Vol2-42.3.10.
59 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
60 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
61 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
62 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
63 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
64
65 # EMMC RX CMD/DATA Delay 2
66 # Refer to EDS-Vol2-42.3.12.
67 # [17:16] stands for Rx Clock before Output Buffer,
68 # 00: Rx clock after output buffer,
69 # 01: Rx clock before output buffer,
70 # 10: Automatic selection based on working mode.
71 # 11: Reserved
72 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
73 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
74 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E"
75
76 # EMMC Rx Strobe Delay
77 # Refer to EDS-Vol2-42.3.11.
78 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
79 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
80 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
81
82 register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB2_A0(MLB)
83 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 (DB)
84 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
85 register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 (MLB)
86
87 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 (MLB)
88 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 (DB)
89
90 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
91
92 # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
93 # Bit 2 - C1 has a redriver which does SBU muxing.
94 # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
95 register "tcss_aux_ori" = "0"
96
97 # HD Audio
98 register "pch_hda_dsp_enable" = "1"
99 register "pch_hda_audio_link_hda_enable" = "1"
100 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
101 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
102 register "pch_hda_idisp_codec_enable" = "1"
103
104 # Configure external V1P05/Vnn/VnnSx Rails
105 register "ext_fivr_settings" = "{
106 .configure_ext_fivr = 1,
107 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
108 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
109 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
110 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
111 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
112 .v1p05_voltage_mv = 1050,
113 .vnn_voltage_mv = 780,
114 .vnn_sx_voltage_mv = 1050,
115 .v1p05_icc_max_ma = 500,
116 .vnn_icc_max_ma = 500,
117 }"
118
119 register "serial_io_i2c_mode" = "{
120 [PchSerialIoIndexI2C0] = PchSerialIoPci,
121 [PchSerialIoIndexI2C1] = PchSerialIoPci,
122 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
123 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
124 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
125 [PchSerialIoIndexI2C5] = PchSerialIoPci,
126 }"
127
128 register "serial_io_gspi_mode" = "{
129 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
130 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
131 }"
132
133 register "serial_io_uart_mode" = "{
134 [PchSerialIoIndexUART0] = PchSerialIoPci,
135 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
136 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
137 }"
138
139 # FIXME: To be enabled in future based on PNP impact data.
140 # Disable Package C-state demotion for nissa baseboard.
141 register "disable_package_c_state_demotion" = "true"
142
143 # Intel Common SoC Config
144 #+-------------------+---------------------------+
145 #| Field | Value |
146 #+-------------------+---------------------------+
147 #| I2C0 | TPM. Early init is |
148 #| | required to set up a BAR |
149 #| | for TPM communication |
150 #| I2C1 | Trackpad |
151 #| I2C5 | Touchscreen |
152 #+-------------------+---------------------------+
153 register "common_soc_config" = "{
154 .i2c[0] = {
155 .early_init = 1,
156 .speed = I2C_SPEED_FAST_PLUS,
157 .speed_config[0] = {
158 .speed = I2C_SPEED_FAST_PLUS,
159 .scl_lcnt = 55,
160 .scl_hcnt = 30,
161 .sda_hold = 7,
162 }
163 },
164 .i2c[1] = {
165 .speed = I2C_SPEED_FAST,
166 .speed_config[0] = {
167 .speed = I2C_SPEED_FAST,
168 .scl_lcnt = 158,
169 .scl_hcnt = 79,
170 .sda_hold = 7,
171 }
172 },
173 .i2c[5] = {
174 .speed = I2C_SPEED_FAST,
175 .speed_config[0] = {
176 .speed = I2C_SPEED_FAST,
177 .scl_lcnt = 158,
178 .scl_hcnt = 79,
179 .sda_hold = 7,
180 }
181 },
182 }"
183
184 register "power_limits_config[ADL_N_041_6W_CORE]" = "{
185 .tdp_pl1_override = 20,
186 .tdp_pl2_override = 25,
187 .tdp_pl4 = 78,
188 }"
189
190 register "power_limits_config[ADL_N_081_7W_CORE]" = "{
191 .tdp_pl1_override = 20,
192 .tdp_pl2_override = 25,
193 .tdp_pl4 = 78,
194 }"
195
196 register "power_limits_config[ADL_N_081_15W_CORE]" = "{
197 .tdp_pl1_override = 20,
198 .tdp_pl2_override = 35,
199 .tdp_pl4 = 83,
200 }"
201
202 device domain 0 on
203 device ref igpu on end
204 device ref dtt on
205 chip drivers/intel/dptf
206 ## sensor information
207 register "options.tsr[0].desc" = ""DDR""
208 register "options.tsr[1].desc" = ""charger""
209 register "options.tsr[2].desc" = ""ambient""
210
211 ## Active Policy
212 register "policies.active" = "{
213 [0] = {
214 .target = DPTF_CPU,
215 .thresholds = {
216 TEMP_PCT(70, 100),
217 TEMP_PCT(60, 65),
218 TEMP_PCT(42, 60),
219 TEMP_PCT(39, 55),
220 TEMP_PCT(38, 50),
221 TEMP_PCT(35, 43),
222 TEMP_PCT(31, 30),
223 }
224 },
225 [1] = {
226 .target = DPTF_TEMP_SENSOR_0,
227 .thresholds = {
228 TEMP_PCT(60, 100),
229 TEMP_PCT(55, 65),
230 TEMP_PCT(52, 60),
231 TEMP_PCT(50, 55),
232 TEMP_PCT(48, 50),
233 TEMP_PCT(45, 43),
234 TEMP_PCT(41, 30),
235 }
236 }
237 }"
238
239 ## Passive Policy
240 register "policies.passive" = "{
241 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
242 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
243 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
244 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
245 }"
246
247 ## Critical Policy
248 register "policies.critical" = "{
249 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
250 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
251 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
252 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
253 }"
254
255 register "controls.power_limits" = "{
256 .pl1 = {
257 .min_power = 6000,
258 .max_power = 20000,
259 .time_window_min = 28 * MSECS_PER_SEC,
260 .time_window_max = 28 * MSECS_PER_SEC,
261 .granularity = 500
262 },
263 .pl2 = {
264 .min_power = 25000,
265 .max_power = 25000,
266 .time_window_min = 32 * MSECS_PER_SEC,
267 .time_window_max = 32 * MSECS_PER_SEC,
268 .granularity = 500
269 }
270 }"
271
272 ## Charger Performance Control (Control, mA)
273 register "controls.charger_perf" = "{
274 [0] = { 255, 1700 },
275 [1] = { 24, 1500 },
276 [2] = { 16, 1000 },
277 [3] = { 8, 500 }
278 }"
279
280 ## Fan Performance Control (Percent, Speed, Noise, Power)
281 register "controls.fan_perf" = "{
282 [0] = { 100, 6000, 220, 2200, },
283 [1] = { 92, 5500, 180, 1800, },
284 [2] = { 85, 5000, 145, 1450, },
285 [3] = { 70, 4400, 115, 1150, },
286 [4] = { 56, 3900, 90, 900, },
287 [5] = { 45, 3300, 55, 550, },
288 [6] = { 38, 3000, 30, 300, },
289 [7] = { 33, 2900, 15, 150, },
290 [8] = { 10, 800, 10, 100, },
291 [9] = { 0, 0, 0, 50, }
292 }"
293
294 ## Fan options
295 register "options.fan.fine_grained_control" = "1"
296 register "options.fan.step_size" = "2"
297
298 device generic 0 on
299 probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
300 end
301 end
302 chip drivers/intel/dptf
303 ## sensor information
304 register "options.tsr[0].desc" = ""DDR""
305 register "options.tsr[1].desc" = ""charger""
306 register "options.tsr[2].desc" = ""ambient""
307
308 ## Active Policy
309 register "policies.active" = "{
310 [0] = {
311 .target = DPTF_CPU,
312 .thresholds = {
313 TEMP_PCT(70, 100),
314 TEMP_PCT(60, 65),
315 TEMP_PCT(42, 58),
316 TEMP_PCT(39, 53),
317 TEMP_PCT(38, 47),
318 TEMP_PCT(35, 43),
319 TEMP_PCT(31, 30),
320 }
321 },
322 [1] = {
323 .target = DPTF_TEMP_SENSOR_0,
324 .thresholds = {
325 TEMP_PCT(60, 100),
326 TEMP_PCT(55, 65),
327 TEMP_PCT(52, 58),
328 TEMP_PCT(50, 53),
329 TEMP_PCT(48, 47),
330 TEMP_PCT(45, 43),
331 TEMP_PCT(41, 30),
332 }
333 }
334 }"
335
336 ## Passive Policy
337 register "policies.passive" = "{
338 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
339 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
340 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
341 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
342 }"
343
344 ## Critical Policy
345 register "policies.critical" = "{
346 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
347 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
348 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
349 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
350 }"
351
352 register "controls.power_limits" = "{
353 .pl1 = {
354 .min_power = 15000,
355 .max_power = 20000,
356 .time_window_min = 28 * MSECS_PER_SEC,
357 .time_window_max = 28 * MSECS_PER_SEC,
358 .granularity = 500
359 },
360 .pl2 = {
361 .min_power = 35000,
362 .max_power = 35000,
363 .time_window_min = 32 * MSECS_PER_SEC,
364 .time_window_max = 32 * MSECS_PER_SEC,
365 .granularity = 500
366 }
367 }"
368
369 ## Charger Performance Control (Control, mA)
370 register "controls.charger_perf" = "{
371 [0] = { 255, 1700 },
372 [1] = { 24, 1500 },
373 [2] = { 16, 1000 },
374 [3] = { 8, 500 }
375 }"
376
377 ## Fan Performance Control (Percent, Speed, Noise, Power)
378 register "controls.fan_perf" = "{
379 [0] = { 100, 6000, 220, 2200, },
380 [1] = { 92, 5500, 180, 1800, },
381 [2] = { 85, 5000, 145, 1450, },
382 [3] = { 70, 4400, 115, 1150, },
383 [4] = { 56, 3900, 90, 900, },
384 [5] = { 45, 3300, 55, 550, },
385 [6] = { 38, 3000, 30, 300, },
386 [7] = { 33, 2900, 15, 150, },
387 [8] = { 10, 800, 10, 100, },
388 [9] = { 0, 0, 0, 50, }
389 }"
390
391 ## Fan options
392 register "options.fan.fine_grained_control" = "1"
393 register "options.fan.step_size" = "2"
394
395 device generic 1 on
396 probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
397 end
398 end
399 end
400 device ref tcss_xhci on
401 chip drivers/usb/acpi
402 device ref tcss_root_hub on
403 chip drivers/usb/acpi
404 register "desc" = ""USB3 Type-C Port C0 (MLB)""
405 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
406 register "use_custom_pld" = "true"
407 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
408 device ref tcss_usb3_port1 on end
409 end
410 end
411 end
412 end
413 device ref xhci on
414 chip drivers/usb/acpi
415 device ref xhci_root_hub on
416 chip drivers/usb/acpi
417 register "desc" = ""USB2 Type-A Port A0 (MLB)""
418 register "type" = "UPC_TYPE_A"
419 register "use_custom_pld" = "true"
420 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
421 device ref usb2_port1 on end
422 end
423 chip drivers/usb/acpi
424 register "desc" = ""USB2 Type-A Port A1 (DB)""
425 register "type" = "UPC_TYPE_A"
426 register "use_custom_pld" = "true"
427 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
428 device ref usb2_port2 on end
429 end
430 chip drivers/usb/acpi
431 register "desc" = ""USB2 Camera""
432 register "type" = "UPC_TYPE_INTERNAL"
433 device ref usb2_port3 on end
434 end
435 chip drivers/usb/acpi
436 register "desc" = ""USB2 Type-C Port C0 (MLB)""
437 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
438 register "use_custom_pld" = "true"
439 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
440 device ref usb2_port5 on end
441 end
442 chip drivers/usb/acpi
443 register "desc" = ""USB2 Bluetooth""
444 register "type" = "UPC_TYPE_INTERNAL"
445 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
446 device ref usb2_port10 on end
447 end
448 chip drivers/usb/acpi
449 register "desc" = ""USB3 Type-A Port A0 (MLB)""
450 register "type" = "UPC_TYPE_USB3_A"
451 register "use_custom_pld" = "true"
452 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
453 device ref usb3_port1 on end
454 end
455 chip drivers/usb/acpi
456 register "desc" = ""USB3 Type-A Port A1 (DB)""
457 register "type" = "UPC_TYPE_USB3_A"
458 register "use_custom_pld" = "true"
459 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
460 device ref usb3_port2 on end
461 end
462 end
463 end
464 end
465 device ref shared_sram on end
466 device ref cnvi_wifi on
467 chip drivers/wifi/generic
468 register "wake" = "GPE0_PME_B0"
469 register "enable_cnvi_ddr_rfim" = "true"
470 register "add_acpi_dma_property" = "true"
471 device generic 0 on end
472 end
473 end
474 device ref i2c0 on
475 chip drivers/i2c/tpm
476 register "hid" = ""GOOG0005""
477 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)"
478 device i2c 50 on end
479 end
480 end #I2C0
481 device ref i2c1 on
482 chip drivers/i2c/generic
483 register "hid" = ""ELAN0000""
484 register "desc" = ""ELAN Touchpad""
485 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
486 register "wake" = "GPE0_DW1_03"
487 register "detect" = "1"
488 device i2c 15 on end
489 end
490 end #I2C1
491 device ref i2c5 on
492 chip drivers/i2c/hid
493 register "generic.hid" = ""ELAN9004""
494 register "generic.desc" = ""ELAN Touchscreen""
495 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
496 register "generic.detect" = "1"
497 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
498 register "generic.reset_delay_ms" = "20"
499 register "generic.reset_off_delay_ms" = "2"
500 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
501 register "generic.enable_delay_ms" = "1"
502 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
503 register "generic.stop_delay_ms" = "150"
504 register "generic.stop_off_delay_ms" = "2"
505 register "generic.has_power_resource" = "1"
506 register "hid_desc_reg_offset" = "0x01"
507 device i2c 10 on end
508 end
509 end #I2C5
510 device ref heci1 on end
511 device ref emmc on
512 probe STORAGE STORAGE_UNKNOWN
513 probe STORAGE STORAGE_EMMC
514 end
515 device ref ufs on
516 probe STORAGE STORAGE_UNKNOWN
517 probe STORAGE STORAGE_UFS
518 end
519 device ref uart0 on end
520 device ref pch_espi on
521 chip ec/google/chromeec
522 device pnp 0c09.0 on end
523 end
524 end
525 device ref pmc hidden end
526 device ref hda on
527 chip drivers/sof
528 register "spkr_tplg" = "max98360a"
529 register "jack_tplg" = "rt5682"
530 register "mic_tplg" = "_2ch_pdm0"
531 device generic 0 on end
532 end
533 end
534 end
535 end
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