src/soc/intel/pantherlake/cpu.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <cpu/cpu.h>
   5 #include <cpu/intel/common/common.h>
   6 #include <cpu/intel/microcode.h>
   7 #include <cpu/intel/smm_reloc.h>
   8 #include <cpu/intel/turbo.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <cpu/x86/mp.h>
  11 #include <cpu/x86/msr.h>
  12 #include <device/pci.h>
  13 #include <fsp/api.h>
  14 #include <intelblocks/acpi.h>
  15 #include <intelblocks/cpulib.h>
  16 #include <intelblocks/mp_init.h>
  17 #include <intelblocks/msr.h>
  18 #include <soc/cpu.h>
  19 #include <soc/msr.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/soc_chip.h>
  22 #include <static.h>
  23
  24 bool cpu_soc_is_in_untrusted_mode(void)
  25 {
  26         msr_t msr;
  27
  28         msr = rdmsr(MSR_BIOS_DONE);
  29         return !!(msr.lo & ENABLE_IA_UNTRUSTED);
  30 }
  31
  32 void cpu_soc_bios_done(void)
  33 {
  34         msr_t msr;
  35
  36         msr = rdmsr(MSR_BIOS_DONE);
  37         msr.lo |= ENABLE_IA_UNTRUSTED;
  38         wrmsr(MSR_BIOS_DONE, msr);
  39 }
  40
  41 uint8_t get_supported_lpm_mask(void)
  42 {
  43         return LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2;
  44 }
  45
  46 static void soc_fsp_load(void)
  47 {
  48         fsps_load();
  49 }
  50
  51 static void configure_misc(void)
  52 {
  53         msr_t msr;
  54
  55         const struct soc_intel_pantherlake_config *conf = config_of_soc();
  56
  57         msr = rdmsr(IA32_MISC_ENABLE);
  58         msr.lo |= FAST_STRINGS_ENABLE_BIT;
  59         msr.lo |= TM1_TM2_EMTTM_ENABLE_BIT;
  60         wrmsr(IA32_MISC_ENABLE, msr);
  61
  62         /* Set EIST status */
  63         cpu_set_eist(conf->eist_enable);
  64
  65         /* Disable Thermal interrupts */
  66         msr.lo = 0;
  67         msr.hi = 0;
  68         wrmsr(IA32_THERM_INTERRUPT, msr);
  69
  70         /* Enable package critical interrupt only */
  71         msr.lo = CRITICAL_TEMP_INTERRUPT_ENABLE;
  72         msr.hi = 0;
  73         wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
  74
  75         /* Enable PROCHOT and Power Performance Platform Override */
  76         msr = rdmsr(MSR_POWER_CTL);
  77         msr.lo |= ENABLE_BIDIR_PROCHOT;
  78         msr.lo |= VR_THERM_ALERT_DISABLE_LOCK;
  79         msr.lo |= PWR_PERF_PLATFORM_OVR;
  80         wrmsr(MSR_POWER_CTL, msr);
  81 }
  82
  83 enum core_type get_soc_cpu_type(void)
  84 {
  85         if (cpu_is_hybrid_supported())
  86                 return cpu_get_cpu_type();
  87
  88         return CPUID_CORE_TYPE_INTEL_CORE;
  89 }
  90
  91 bool soc_is_nominal_freq_supported(void)
  92 {
  93         return true;
  94 }
  95
  96 static void enable_x2apic(void)
  97 {
  98         if (!CONFIG(X2APIC_LATE_WORKAROUND))
  99                 return;
 100
 101         enable_lapic_mode(true);
 102 }
 103
 104 /* All CPUs including BSP will run the following function. */
 105 void soc_core_init(struct device *cpu)
 106 {
 107         /* Clear out pending MCEs */
 108         mca_configure();
 109
 110         enable_x2apic();
 111
 112         enable_lapic_tpr();
 113
 114         /* Configure Enhanced SpeedStep and Thermal Sensors */
 115         configure_misc();
 116
 117         enable_pm_timer_emulation();
 118
 119         /* Enable Direct Cache Access */
 120         configure_dca_cap();
 121
 122         /* Set energy policy */
 123         set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 124
 125         const struct soc_intel_pantherlake_config *conf = config_of_soc();
 126         /* Set energy-performance preference */
 127         if (conf != NULL && conf->enable_energy_perf_pref) {
 128                 if (check_energy_perf_cap())
 129                         set_energy_perf_pref(conf->energy_perf_pref_value);
 130         }
 131
 132         /* Enable Turbo */
 133         enable_turbo();
 134
 135         /* Set core type in struct cpu_info */
 136         set_dev_core_type();
 137
 138         if (CONFIG(INTEL_TME) && is_tme_supported())
 139                 set_tme_core_activate();
 140
 141         if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) {
 142                 /* Disable 3-strike error */
 143                 disable_signaling_three_strike_event();
 144
 145                 set_aesni_lock();
 146
 147                 /* Enable VMX */
 148                 set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !conf->disable_vmx);
 149
 150                 /* Feature control lock configure */
 151                 set_feature_ctrl_lock();
 152         }
 153 }
 154
 155 static void per_cpu_smm_trigger(void)
 156 {
 157         /* Relocate the SMM handler. */
 158         smm_relocate();
 159 }
 160
 161 static void pre_mp_init(void)
 162 {
 163         soc_fsp_load();
 164
 165         const struct soc_intel_pantherlake_config *conf = config_of_soc();
 166         if (conf == NULL) {
 167                 printk(BIOS_ERR, "Configuration could not be retrieved.\n");
 168                 return;
 169         }
 170         if (conf->enable_energy_perf_pref) {
 171                 if (check_energy_perf_cap())
 172                         enable_energy_perf_pref();
 173                 else
 174                         printk(BIOS_WARNING, "Energy Performance Preference not supported!\n");
 175         }
 176 }
 177
 178 static void post_mp_init(void)
 179 {
 180         /* Set Max Ratio */
 181         cpu_set_max_ratio();
 182
 183         /*
 184          * 1. Now that all APs have been relocated as well as the BSP let SMIs
 185          * start flowing.
 186          * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
 187          * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
 188          */
 189         global_smi_enable_no_pwrbtn();
 190 }
 191
 192 static const struct mp_ops mp_ops = {
 193         /*
 194          * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
 195          * that are set prior to ramstage.
 196          * Real MTRRs programming are being done after resource allocation.
 197          */
 198         .pre_mp_init = pre_mp_init,
 199         .get_cpu_count = get_cpu_count,
 200         .get_smm_info = smm_info,
 201         .get_microcode_info = get_microcode_info,
 202         .pre_mp_smm_init = smm_initialize,
 203         .per_cpu_smm_trigger = per_cpu_smm_trigger,
 204         .relocation_handler = smm_relocation_handler,
 205         .post_mp_init = post_mp_init,
 206 };
 207
 208 void mp_init_cpus(struct bus *cpu_bus)
 209 {
 210         if (mp_init_with_smm(cpu_bus, &mp_ops))
 211                 printk(BIOS_ERR, "MP initialization failure.\n");
 212
 213         /* Thermal throttle activation offset */
 214         configure_tcc_thermal_target();
 215 }
 216
 217 int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 218 {
 219         if (!CONFIG(CHROMEOS))
 220                 return 0;
 221         /*
 222          * Locked RO Descriptor Implications:
 223          *
 224          * - A locked descriptor signals the RO binary is fixed; the FIT will load the
 225          *   RO's microcode during system reset.
 226          * - Attempts to load newer microcode from the RW CBFS will cause a boot-time
 227          *   delay (~60ms, core-dependent), as the microcode must be reloaded on BSP+APs.
 228          * - The kernel can load microcode updates without impacting AP FW boot time.
 229          * - Skipping RW CBFS microcode loading is low-risk when the RO is locked,
 230          *   prioritizing fast boot times.
 231          */
 232         if (CONFIG(LOCK_MANAGEMENT_ENGINE) && current_patch_id)
 233                 return 1;
 234
 235         return 0;
 236 }