src/soc/intel/pantherlake/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootmode.h>
   4 #include <cpu/intel/microcode.h>
   5 #include <fsp/api.h>
   6 #include <fsp/fsp_debug_event.h>
   7 #include <fsp/fsp_gop_blt.h>
   8 #include <fsp/ppi/mp_service_ppi.h>
   9 #include <intelblocks/irq.h>
  10 #include <intelblocks/mp_init.h>
  11 #include <intelblocks/systemagent.h>
  12 #include <intelblocks/xdci.h>
  13 #include <intelpch/lockdown.h>
  14 #include <option.h>
  15 #include <soc/cpu.h>
  16 #include <soc/intel/common/vbt.h>
  17 #include <soc/pcie.h>
  18 #include <soc/ramstage.h>
  19 #include <static.h>
  20
  21 #define MAX_ONBOARD_PCIE_DEVICES 256
  22
  23 /* THC assignment definition */
  24 enum {
  25         THC_NONE,
  26         THC_0,
  27         THC_1
  28 };
  29
  30 /* LPSS UART Power Gating mode */
  31 enum {
  32         LPSS_UART_PG_DISABLED,
  33         LPSS_UART_PG_ENABLED,
  34         LPSS_UART_PG_AUTO
  35 };
  36
  37 static const pci_devfn_t i2c_dev[] = {
  38         PCI_DEVFN_I2C0,
  39         PCI_DEVFN_I2C1,
  40         PCI_DEVFN_I2C2,
  41         PCI_DEVFN_I2C3,
  42         PCI_DEVFN_I2C4,
  43         PCI_DEVFN_I2C5,
  44 };
  45
  46 static const pci_devfn_t uart_dev[] = {
  47         PCI_DEVFN_UART0,
  48         PCI_DEVFN_UART1,
  49         PCI_DEVFN_UART2
  50 };
  51
  52 static const pci_devfn_t gspi_dev[] = {
  53         PCI_DEVFN_GSPI0,
  54         PCI_DEVFN_GSPI1,
  55         PCI_DEVFN_GSPI2
  56 };
  57
  58 /*
  59  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
  60  * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
  61  * In order to ensure that mainboard setting does not disable L1 substates
  62  * incorrectly, chip config parameter values are offset by 1 with 0 meaning
  63  * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
  64  * value is set in fsp_params.
  65  * 0: Use FSP UPD default
  66  * 1: Disable L1 substates
  67  * 2: Use L1.1
  68  * 3: Use L1.2 (FSP UPD default)
  69  */
  70 static int get_l1_substate_control(enum L1_substates_control ctl)
  71 {
  72         if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
  73                 ctl = L1_SS_DISABLED;
  74         else if (ctl > L1_SS_L1_2 || ctl == L1_SS_FSP_DEFAULT)
  75                 ctl = L1_SS_L1_2;
  76         return ctl - 1;
  77 }
  78
  79 /*
  80  * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
  81  * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
  82  * that the mainboard setting does not disable ASPM incorrectly, chip
  83  * config parameter values are offset by 1 with 0 meaning use FSP UPD default.
  84  * get_aspm_control() ensures that the right UPD value is set in fsp_params.
  85  * 0: Use FSP UPD default
  86  * 1: Disable ASPM
  87  * 2: L0s only
  88  * 3: L1 only
  89  * 4: L0s and L1
  90  * 5: Auto configuration
  91  */
  92 static unsigned int get_aspm_control(enum ASPM_control ctl)
  93 {
  94         if (ctl > ASPM_AUTO || ctl == ASPM_DEFAULT)
  95                 ctl = ASPM_AUTO;
  96         return ctl - 1;
  97 }
  98
  99 __weak void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 100 {
 101         /* Override settings per board. */
 102 }
 103
 104 static const struct slot_irq_constraints irq_constraints[] = {
 105         {
 106                 .slot = PCI_DEV_SLOT_IGD,
 107                 .fns = {
 108                         /* INTERRUPT_PIN is RO/0x01 */
 109                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_IGD, PCI_INT_A),
 110                 },
 111         },
 112         {
 113                 .slot = PCI_DEV_SLOT_DPTF,
 114                 .fns = {
 115                         /* Dynamic Tuning Technology (DTT) device IRQ is not
 116                            programmable and is INT_A/PIRQ_A (IRQ 16) */
 117                         FIXED_INT_PIRQ(PCI_DEVFN_DPTF, PCI_INT_A, PIRQ_A),
 118                 },
 119         },
 120         {
 121                 .slot = PCI_DEV_SLOT_IPU,
 122                 .fns = {
 123                         /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW,
 124                            but S0ix fails when not set to 16 (b/193434192) */
 125                         FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A),
 126                 },
 127         },
 128         {
 129                 .slot = PCI_DEV_SLOT_PCIE_2,
 130                 .fns = {
 131                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A),
 132                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
 133 #if CONFIG(SOC_INTEL_PANTHERLAKE_H)
 134                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
 135                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
 136 #endif
 137                 },
 138         },
 139         {
 140                 .slot = PCI_DEV_SLOT_TBT,
 141                 .fns = {
 142                         ANY_PIRQ(PCI_DEVFN_TBT0),
 143                         ANY_PIRQ(PCI_DEVFN_TBT1),
 144                         ANY_PIRQ(PCI_DEVFN_TBT2),
 145                         ANY_PIRQ(PCI_DEVFN_TBT3),
 146                 },
 147         },
 148         {
 149                 .slot = PCI_DEV_SLOT_NPU,
 150                 .fns = {
 151                         /* INTERRUPT_PIN is RO/0x01 */
 152                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPU, PCI_INT_A),
 153                 },
 154         },
 155         {
 156                 .slot = PCI_DEV_SLOT_TCSS,
 157                 .fns = {
 158                         ANY_PIRQ(PCI_DEVFN_TCSS_XHCI),
 159                 },
 160         },
 161         {
 162                 .slot = PCI_DEV_SLOT_THC,
 163                 .fns = {
 164                         ANY_PIRQ(PCI_DEVFN_THC0),
 165                         ANY_PIRQ(PCI_DEVFN_THC1),
 166                 },
 167         },
 168         {
 169                 .slot = PCI_DEV_SLOT_ISH,
 170                 .fns = {
 171                         DIRECT_IRQ(PCI_DEVFN_ISH),
 172                 },
 173         },
 174         {
 175                 .slot = PCI_DEV_SLOT_XHCI,
 176                 .fns = {
 177                         ANY_PIRQ(PCI_DEVFN_XHCI),
 178                         DIRECT_IRQ(PCI_DEVFN_USBOTG),
 179                         ANY_PIRQ(PCI_DEVFN_CNVI_WIFI),
 180                 },
 181         },
 182         {
 183                 .slot = PCI_DEV_SLOT_SIO0,
 184                 .fns = {
 185                         DIRECT_IRQ(PCI_DEVFN_I2C0),
 186                         DIRECT_IRQ(PCI_DEVFN_I2C1),
 187                         DIRECT_IRQ(PCI_DEVFN_I2C2),
 188                         DIRECT_IRQ(PCI_DEVFN_I2C3),
 189                 },
 190         },
 191         {
 192                 .slot = PCI_DEV_SLOT_CSE,
 193                 .fns = {
 194                         ANY_PIRQ(PCI_DEVFN_CSE),
 195                         ANY_PIRQ(PCI_DEVFN_CSE_2),
 196                         ANY_PIRQ(PCI_DEVFN_CSE_IDER),
 197                         ANY_PIRQ(PCI_DEVFN_CSE_KT),
 198                         ANY_PIRQ(PCI_DEVFN_CSE_3),
 199                         ANY_PIRQ(PCI_DEVFN_CSE_4),
 200                 },
 201         },
 202         {
 203                 .slot = PCI_DEV_SLOT_SIO1,
 204                 .fns = {
 205                         DIRECT_IRQ(PCI_DEVFN_I2C4),
 206                         DIRECT_IRQ(PCI_DEVFN_I2C5),
 207                         DIRECT_IRQ(PCI_DEVFN_UART2),
 208                 },
 209         },
 210         {
 211                 .slot = PCI_DEV_SLOT_PCIE_1,
 212                 .fns = {
 213                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
 214                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
 215                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
 216                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
 217                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
 218                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
 219                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
 220                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
 221                 },
 222         },
 223         {
 224                 .slot = PCI_DEV_SLOT_SIO2,
 225                 .fns = {
 226                         /* UART0 shares an interrupt line with TSN0, so must use
 227                            a PIRQ */
 228                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART0, PCI_INT_A),
 229                         /* UART1 shares an interrupt line with TSN1, so must use
 230                            a PIRQ */
 231                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART1, PCI_INT_B),
 232                         DIRECT_IRQ(PCI_DEVFN_GSPI0),
 233                         DIRECT_IRQ(PCI_DEVFN_GSPI1),
 234                 },
 235         },
 236         {
 237                 .slot = PCI_DEV_SLOT_ESPI,
 238                 .fns = {
 239                         ANY_PIRQ(PCI_DEVFN_HDA),
 240                         ANY_PIRQ(PCI_DEVFN_SMBUS),
 241                         ANY_PIRQ(PCI_DEVFN_GBE),
 242                         /* INTERRUPT_PIN is RO/0x01 */
 243                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPK, PCI_INT_A),
 244                 },
 245         },
 246 };
 247
 248 static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
 249                                   const struct soc_intel_pantherlake_config *config)
 250 {
 251         size_t i;
 252
 253         for (i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
 254                 s_cfg->SerialIoI2cMode[i] =
 255                         is_devfn_enabled(i2c_dev[i]) ? config->serial_io_i2c_mode[i] : 0;
 256
 257         for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
 258                 s_cfg->SerialIoLpssSpiCsMode[i] = config->serial_io_gspi_cs_mode[i];
 259                 s_cfg->SerialIoLpssSpiCsState[i] = config->serial_io_gspi_cs_state[i];
 260                 s_cfg->SerialIoLpssSpiMode[i] =
 261                         is_devfn_enabled(gspi_dev[i]) ? config->serial_io_gspi_mode[i] : 0;
 262         }
 263
 264         for (i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) {
 265                 s_cfg->SerialIoUartMode[i] = is_devfn_enabled(uart_dev[i]) ?
 266                         config->serial_io_uart_mode[i] : 0;
 267                 s_cfg->SerialIoUartPowerGating[i] = is_devfn_enabled(uart_dev[i]) ?
 268                         LPSS_UART_PG_ENABLED : LPSS_UART_PG_AUTO;
 269         }
 270 }
 271
 272 static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
 273                                  const struct soc_intel_pantherlake_config *config)
 274 {
 275         if (!CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
 276                 return;
 277
 278         s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
 279 }
 280
 281 static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg,
 282                                  const struct soc_intel_pantherlake_config *config)
 283 {
 284         const struct microcode *microcode;
 285         size_t length;
 286
 287         if (!CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS))
 288                 return;
 289
 290         /* Locate microcode and pass to FSP-S for 2nd microcode loading */
 291         microcode = intel_microcode_find();
 292         if (!microcode)
 293                 return;
 294
 295         length = get_microcode_size(microcode);
 296         if (!length)
 297                 return;
 298
 299         /* Update CPU Microcode patch base address/size */
 300         s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode;
 301         s_cfg->MicrocodeRegionSize = (uint32_t)length;
 302 }
 303
 304 static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
 305                                  const struct soc_intel_pantherlake_config *config)
 306 {
 307         /* Load VBT before devicetree-specific config. */
 308         s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get();
 309
 310         /* Check if IGD is present and fill Graphics init param accordingly */
 311         s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD);
 312         s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
 313         s_cfg->PavpEnable = CONFIG(PAVP);
 314 }
 315
 316 static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 317                                   const struct soc_intel_pantherlake_config *config)
 318 {
 319         s_cfg->TcssAuxOri = config->tcss_aux_ori;
 320
 321         /* Explicitly clear this field to avoid using defaults */
 322         memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg));
 323
 324         /* D3Cold for TCSS */
 325         s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable;
 326         s_cfg->UsbTcPortEn = 0;
 327
 328         for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++)
 329                 if (config->tcss_ports[i].enable)
 330                         s_cfg->UsbTcPortEn |= BIT(i);
 331 }
 332
 333 static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
 334                                               const struct soc_intel_pantherlake_config *config)
 335 {
 336         /* Chipset Lockdown */
 337         const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
 338
 339         s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp;
 340         s_cfg->PchLockDownBiosInterface = lockdown_by_fsp;
 341         s_cfg->PchUnlockGpioPads = !lockdown_by_fsp;
 342         s_cfg->RtcMemoryLock = lockdown_by_fsp;
 343         s_cfg->SkipPamLock = !lockdown_by_fsp;
 344
 345         /* coreboot will send EOP before loading payload */
 346         s_cfg->EndOfPostMessage = 0; /* EOP disable */
 347
 348         s_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG);
 349 }
 350
 351 static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
 352                                   const struct soc_intel_pantherlake_config *config)
 353 {
 354         size_t i;
 355
 356         for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) {
 357                 s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable;
 358                 s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
 359                 s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
 360                 s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
 361                 s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 362
 363                 if (config->usb2_ports[i].enable)
 364                         s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
 365                 else
 366                         s_cfg->Usb2OverCurrentPin[i] = OC_SKIP;
 367
 368                 s_cfg->PortResetMessageEnable[i] = config->usb2_ports[i].type_c;
 369         }
 370
 371         for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) {
 372                 s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 373                 if (config->usb3_ports[i].enable)
 374                         s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 375                 else
 376                         s_cfg->Usb3OverCurrentPin[i] = OC_SKIP;
 377
 378                 if (config->usb3_ports[i].tx_de_emp) {
 379                         s_cfg->Usb3HsioTxDeEmphEnable[i] = 1;
 380                         s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
 381                 }
 382                 if (config->usb3_ports[i].tx_downscale_amp) {
 383                         s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1;
 384                         s_cfg->Usb3HsioTxDownscaleAmp[i] =
 385                                 config->usb3_ports[i].tx_downscale_amp;
 386                 }
 387         }
 388
 389         for (i = 0; i < MAX_TYPE_C_PORTS; i++)
 390                 if (config->tcss_ports[i].enable)
 391                         s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
 392 }
 393
 394 static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,
 395                                   const struct soc_intel_pantherlake_config *config)
 396 {
 397         s_cfg->XdciEnable = xdci_can_enable(PCI_DEVFN_USBOTG);
 398 }
 399
 400 static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg,
 401                                      const struct soc_intel_pantherlake_config *config)
 402 {
 403         s_cfg->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF);
 404 }
 405
 406 static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
 407 {
 408         const struct pci_irq_entry *entry = get_cached_pci_irqs();
 409         SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
 410         size_t pch_total = 0, cfg_count = 0;
 411
 412         if (!entry)
 413                 return NULL;
 414
 415         /* Count PCH devices */
 416         while (entry) {
 417                 if (is_pch_slot(entry->devfn))
 418                         pch_total++;
 419                 entry = entry->next;
 420         }
 421
 422         /* Convert PCH device entries to FSP format */
 423         config = calloc(pch_total, sizeof(*config));
 424         entry = get_cached_pci_irqs();
 425         while (entry) {
 426                 if (!is_pch_slot(entry->devfn)) {
 427                         entry = entry->next;
 428                         continue;
 429                 }
 430
 431                 config[cfg_count].Device = PCI_SLOT(entry->devfn);
 432                 config[cfg_count].Function = PCI_FUNC(entry->devfn);
 433                 config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
 434                 config[cfg_count].Irq = entry->irq;
 435                 cfg_count++;
 436
 437                 entry = entry->next;
 438         }
 439
 440         *out_count = cfg_count;
 441
 442         return config;
 443 }
 444
 445 static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
 446                                  const struct soc_intel_pantherlake_config *config)
 447 {
 448         if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
 449                 die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n");
 450
 451         size_t pch_count = 0;
 452         const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
 453
 454         s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
 455         s_cfg->NumOfDevIntConfig = pch_count;
 456         printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
 457 }
 458
 459 static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid)
 460 {
 461         if (!(dev && svid && ssid))
 462                 return;
 463
 464         *svid = CONFIG_SUBSYSTEM_VENDOR_ID ? : (dev->subsystem_vendor ? : 0x8086);
 465         *ssid = CONFIG_SUBSYSTEM_DEVICE_ID ? : (dev->subsystem_device ? : 0xfffe);
 466 }
 467
 468 /*
 469  * Programming SSID before FSP-S is important because SSID registers of a few PCIE
 470  * devices (e.g. IPU, Crashlog, XHCI, TCSS_XHCI etc.) are locked after FSP-S hence
 471  * provide a custom SSID (same as DID by default) value via UPD.
 472  */
 473 static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg,
 474                                       const struct soc_intel_pantherlake_config *config)
 475 {
 476         struct svid_ssid_init_entry {
 477                 union {
 478                         struct {
 479                                 uint64_t reg:12;
 480                                 uint64_t function:3;
 481                                 uint64_t device:5;
 482                                 uint64_t bus:8;
 483                                 uint64_t ignore1:4;
 484                                 uint64_t segment:16;
 485                                 uint64_t ignore2:16;
 486                         };
 487                         uint64_t data;
 488                 };
 489                 struct {
 490                         uint16_t svid;
 491                         uint16_t ssid;
 492                 };
 493                 uint32_t ignore3;
 494         };
 495
 496         static struct svid_ssid_init_entry ssid_table[MAX_ONBOARD_PCIE_DEVICES];
 497         const struct device *dev;
 498         size_t i = 0;
 499
 500         for (dev = all_devices; dev; dev = dev->next) {
 501                 if (!(is_dev_enabled(dev) && dev->path.type == DEVICE_PATH_PCI &&
 502                     dev->upstream->secondary == 0))
 503                         continue;
 504
 505                 if (dev->path.pci.devfn == PCI_DEVFN_ROOT) {
 506                         evaluate_ssid(dev, &s_cfg->SiCustomizedSvid, &s_cfg->SiCustomizedSsid);
 507                 } else {
 508                         ssid_table[i].reg       = PCI_SUBSYSTEM_VENDOR_ID;
 509                         ssid_table[i].device    = PCI_SLOT(dev->path.pci.devfn);
 510                         ssid_table[i].function  = PCI_FUNC(dev->path.pci.devfn);
 511                         evaluate_ssid(dev, &ssid_table[i].svid, &ssid_table[i].ssid);
 512                         i++;
 513                 }
 514         }
 515
 516         s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table;
 517         s_cfg->SiNumberOfSsidTableEntry = i;
 518
 519         /* Ensure FSP will program the registers */
 520         s_cfg->SiSkipSsidProgramming = 0;
 521 }
 522
 523 static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg,
 524                                  const struct soc_intel_pantherlake_config *config)
 525 {
 526         s_cfg->PchLanEnable = is_devfn_enabled(PCI_DEVFN_GBE);
 527 }
 528
 529 static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
 530                                   const struct soc_intel_pantherlake_config *config)
 531 {
 532         s_cfg->CnviMode = is_devfn_enabled(PCI_DEVFN_CNVI_WIFI);
 533         s_cfg->CnviWifiCore = config->cnvi_wifi_core;
 534         s_cfg->CnviBtCore = config->cnvi_bt_core;
 535         s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload;
 536
 537         if (!s_cfg->CnviMode && s_cfg->CnviWifiCore) {
 538                 printk(BIOS_ERR, "CNVi WiFi is enabled without CNVi being enabled\n");
 539                 s_cfg->CnviWifiCore = 0;
 540         }
 541         if (!s_cfg->CnviBtCore && s_cfg->CnviBtAudioOffload) {
 542                 printk(BIOS_ERR, "BT offload is enabled without CNVi BT being enabled\n");
 543                 s_cfg->CnviBtAudioOffload = 0;
 544         }
 545         if (!s_cfg->CnviMode && s_cfg->CnviBtCore) {
 546                 printk(BIOS_ERR, "CNVi BT is enabled without CNVi being enabled\n");
 547                 s_cfg->CnviBtCore = 0;
 548                 s_cfg->CnviBtAudioOffload = 0;
 549         }
 550
 551         s_cfg->CnviBtInterface = is_devfn_enabled(PCI_DEVFN_CNVI_BT) ? 2 : 1;
 552 }
 553
 554 static void fill_fsps_pmcpd_params(FSP_S_CONFIG *s_cfg,
 555                                    const struct soc_intel_pantherlake_config *config)
 556 {
 557         s_cfg->PmcPdEnable = 1;
 558 }
 559
 560 static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg,
 561                                  const struct soc_intel_pantherlake_config *config)
 562 {
 563         s_cfg->ThcAssignment[0] = is_devfn_enabled(PCI_DEVFN_THC0) ? THC_0 : THC_NONE;
 564         s_cfg->ThcAssignment[1] = is_devfn_enabled(PCI_DEVFN_THC1) ? THC_1 : THC_NONE;
 565 }
 566
 567 static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg,
 568                                   const struct soc_intel_pantherlake_config *config)
 569 {
 570         bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
 571         s_cfg->Enable8254ClockGating = !use_8254;
 572         s_cfg->Enable8254ClockGatingOnS3 = !use_8254;
 573 }
 574
 575 static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg,
 576                                       const struct soc_intel_pantherlake_config *config)
 577 {
 578         /*
 579          * Legacy PM ACPI Timer (and TCO Timer)
 580          * This *must* be 1 in any case to keep FSP from
 581          *  1) enabling PM ACPI Timer emulation in uCode.
 582          *  2) disabling the PM ACPI Timer.
 583          * We handle both by ourself!
 584          */
 585         s_cfg->EnableTcoTimer = 1;
 586 }
 587
 588 static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 589                                   const struct soc_intel_pantherlake_config *config)
 590 {
 591         uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table());
 592
 593         for (size_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
 594                 const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i];
 595                 if (!(enable_mask & BIT(i)))
 596                         continue;
 597                 s_cfg->PcieRpL1Substates[i] =
 598                         get_l1_substate_control(rp_cfg->PcieRpL1Substates);
 599                 s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
 600                 s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
 601                 s_cfg->PcieRpHotPlug[i] =
 602                         !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 603                 s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
 604                 if (rp_cfg->pcie_rp_aspm)
 605                         s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
 606         }
 607
 608         s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 609 }
 610
 611 static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 612                                         const struct soc_intel_pantherlake_config *config)
 613 {
 614         /* Skip setting D0I3 bit for all HECI devices */
 615         s_cfg->DisableD0I3SettingForHeci = 1;
 616
 617         s_cfg->Hwp = 1;
 618         s_cfg->Cx = 1;
 619         /* Enable the energy efficient turbo mode */
 620         s_cfg->EnergyEfficientTurbo = 1;
 621         s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
 622         /* Un-Demotion from Demoted C1 need to be disable when
 623            C1 auto demotion is disabled. */
 624         s_cfg->C1StateUnDemotion = !config->disable_c1_state_auto_demotion;
 625         s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion;
 626         s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion;
 627         s_cfg->PkgCStateUnDemotion = !config->disable_package_c_state_demotion;
 628         s_cfg->PmcV1p05PhyExtFetControlEn = 1;
 629
 630         /* Enable/Disable PCH to CPU energy report feature. */
 631         s_cfg->PchPmDisableEnergyReport = !config->pch_pm_energy_report_enable;
 632 }
 633
 634 static void fill_fsps_npu_params(FSP_S_CONFIG *s_cfg,
 635                                  const struct soc_intel_pantherlake_config *config)
 636 {
 637         s_cfg->NpuEnable = is_devfn_enabled(PCI_DEVFN_NPU);
 638 }
 639
 640 static void fill_fsps_audio_params(FSP_S_CONFIG *s_cfg,
 641                                    const struct soc_intel_pantherlake_config *config)
 642 {
 643         if (!is_devfn_enabled(PCI_DEVFN_HDA))
 644                 return;
 645
 646         /* Fill MIC privacy settings */
 647         s_cfg->PchHdaMicPrivacyHwModeSoundWire0 = 1;
 648         s_cfg->PchHdaMicPrivacyHwModeSoundWire1 = 1;
 649         s_cfg->PchHdaMicPrivacyHwModeSoundWire2 = 1;
 650         s_cfg->PchHdaMicPrivacyHwModeSoundWire3 = 1;
 651         s_cfg->PchHdaMicPrivacyHwModeSoundWire4 = 1;
 652         s_cfg->PchHdaMicPrivacyHwModeDmic = 1;
 653 }
 654
 655 static void fill_fsps_iax_params(FSP_S_CONFIG *s_cfg,
 656                                  const struct soc_intel_pantherlake_config *config)
 657 {
 658         s_cfg->IaxEnable = is_devfn_enabled(PCI_DEVFN_IAA);
 659 }
 660
 661 static void arch_silicon_init_params(FSPS_ARCH2_UPD *s_arch_cfg)
 662 {
 663         /* Assign FspEventHandler arch Upd to use coreboot debug event handler */
 664         if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)
 665             && CONFIG(CONSOLE_SERIAL)
 666             && CONFIG(FSP_ENABLE_SERIAL_DEBUG))
 667                 s_arch_cfg->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *)
 668                                                           fsp_debug_event_handler);
 669
 670 }
 671
 672 static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 673                                     const struct soc_intel_pantherlake_config *config)
 674 {
 675         void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg,
 676                                    const struct soc_intel_pantherlake_config *config) = {
 677                 fill_fsps_lpss_params,
 678                 fill_fsps_cpu_params,
 679                 fill_fsps_microcode_params,
 680                 fill_fsps_igd_params,
 681                 fill_fsps_tcss_params,
 682                 fill_fsps_chipset_lockdown_params,
 683                 fill_fsps_xhci_params,
 684                 fill_fsps_xdci_params,
 685                 fill_fsps_thermal_params,
 686                 fill_fsps_irq_params,
 687                 fill_fsps_pci_ssid_params,
 688                 fill_fsps_lan_params,
 689                 fill_fsps_cnvi_params,
 690                 fill_fsps_pmcpd_params,
 691                 fill_fsps_thc_params,
 692                 fill_fsps_8254_params,
 693                 fill_fsps_pm_timer_params,
 694                 fill_fsps_pcie_params,
 695                 fill_fsps_misc_power_params,
 696                 fill_fsps_npu_params,
 697                 fill_fsps_audio_params,
 698                 fill_fsps_iax_params,
 699         };
 700
 701         for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)
 702                 fill_fsps_params[i](s_cfg, config);
 703 }
 704
 705 /* UPD parameters to be initialized before SiliconInit */
 706 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 707 {
 708         struct soc_intel_pantherlake_config *config;
 709         FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
 710         FSPS_ARCH2_UPD *s_arch_cfg = &supd->FspsArchUpd;
 711
 712         config = config_of_soc();
 713         arch_silicon_init_params(s_arch_cfg);
 714         /* Override settings per board if required. */
 715         mainboard_update_soc_chip_config(config);
 716         soc_silicon_init_params(s_cfg, config);
 717         mainboard_silicon_init_params(s_cfg);
 718 }
 719
 720 /*
 721  * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
 722  * This platform supports below MultiPhaseSIInit Phase(s):
 723  *
 724  * Phase |  FSP return point                    |  Purpose
 725  * ----- + -------------------------------------+ ------------------------
 726  *   1   |  After TCSS initialization completed |  for TCSS specific init
 727  */
 728 void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
 729 {
 730         switch (phase_index) {
 731         case 1:
 732                 /* TCSS specific initialization here */
 733                 printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
 734                        __FILE__, __func__);
 735
 736                 if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
 737                         const struct soc_intel_pantherlake_config *config = config_of_soc();
 738                         tcss_configure(config->typec_aux_bias_pads);
 739                 }
 740                 break;
 741         default:
 742                 break;
 743         }
 744 }
 745
 746 /* Mainboard GPIO Configuration */
 747 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
 748 {
 749         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 750 }
 751
 752 /* Handle FSP logo params */
 753 void soc_load_logo(FSPS_UPD *supd)
 754 {
 755         efi_uintn_t logo, blt_size;
 756         uint32_t logo_size;
 757
 758         fsp_convert_bmp_to_gop_blt(&logo, &logo_size,
 759                                    &supd->FspsConfig.BltBufferAddress,
 760                                    &blt_size,
 761                                    &supd->FspsConfig.LogoPixelHeight,
 762                                    &supd->FspsConfig.LogoPixelWidth);
 763 }