src/southbridge/intel/i82371eb/fadt.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /*
   4  * Based on src/southbridge/via/vt8237r/vt8237_fadt.c
   5  */
   6
   7 #include <acpi/acpi.h>
   8 #include <device/device.h>
   9 #include <device/pci.h>
  10 #include <version.h>
  11
  12 #include "i82371eb.h"
  13
  14 /**
  15  * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
  16  * Reference: ACPIspec40a, 5.2.9, page 118
  17  */
  18 void acpi_fill_fadt(acpi_fadt_t *fadt)
  19 {
  20         fadt->sci_int = 9;
  21
  22         if (permanent_smi_handler()) {
  23                 /* TODO: SMI handler is not implemented. */
  24                 fadt->smi_cmd = 0x00;
  25         }
  26
  27         fadt->pm1a_evt_blk = DEFAULT_PMBASE;
  28         fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
  29
  30         fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR;
  31         fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS;
  32
  33         /* *_len define register width in bytes */
  34         fadt->pm1_evt_len = 4;
  35         fadt->pm1_cnt_len = 2;
  36         fadt->pm_tmr_len = 4;
  37         fadt->gpe0_blk_len = 4;
  38
  39         fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
  40         fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
  41         fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
  42         fadt->duty_width = 3; /* this width is in bits */
  43         fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
  44         fadt->mon_alrm = 0x0; /* not supported */
  45         /*
  46          * bit  meaning
  47          * 0    1: We have user-visible legacy devices
  48          * 1    1: 8042
  49          * 2    0: VGA is ok to probe
  50          * 3    1: MSI are not supported
  51          */
  52         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042 |
  53                                ACPI_FADT_MSI_NOT_SUPPORTED;
  54         /*
  55          * bit  meaning
  56          * 0    WBINVD
  57          *      Processors in new ACPI-compatible systems are required to
  58          *      support this function and indicate this to OSPM by setting
  59          *      this field.
  60          * 1    WBINVD_FLUSH
  61          *      If set, indicates that the hardware flushes all caches on the
  62          *      WBINVD instruction and maintains memory coherency, but does
  63          *      not guarantee the caches are invalidated.
  64          * 2    PROC_C1
  65          *      C1 power state (x86 hlt instruction) is supported on all cpus
  66          * 3    P_LVL2_UP
  67          *      0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor
  68          * 4    PWR_BUTTON
  69          *      0: pwr button is fixed feature
  70          *      1: pwr button has control method device if present
  71          * 5    SLP_BUTTON
  72          *      0: sleep button is fixed feature
  73          *      1: sleep button has control method device if present
  74          * 6    FIX_RTC
  75          *      0: RTC wake status supported in fixed register spce
  76          * 7    RTC_S4
  77          *      1: RTC can wake from S4
  78          * 8    TMR_VAL_EXT
  79          *      1: pmtimer is 32bit, 0: pmtimer is 24bit
  80          * 9    DCK_CAP
  81          *      1: system supports docking station
  82          * 10   RESET_REG_SUPPORT
  83          *      1: fadt describes reset register for system reset
  84          * 11   SEALED_CASE
  85          *      1: No expansion possible, sealed case
  86          * 12   HEADLESS
  87          *      1: Video output, keyboard and mouse are not connected
  88          * 13   CPU_SW_SLP
  89          *      1: Special processor instruction needs to be executed
  90          *      after writing SLP_TYP
  91          * 14   PCI_EXP_WAK
  92          *      1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set
  93          *      on platforms with pci express support
  94          * 15   USE_PLATFORM_CLOCK
  95          *      1: OS should prefer platform clock over processor internal
  96          *      clock.
  97          * 16   S4_RTC_STS_VALID
  98          * 17   REMOTE_POWER_ON_CAPABLE
  99          *      1: platform correctly supports OSPM leaving GPE wake events
 100          *      armed prior to an S5 transition.
 101          * 18   FORCE_APIC_CLUSTER_MODEL
 102          * 19   FORCE_APIC_PHYSICAL_DESTINATION_MODE
 103          */
 104         fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 105                        ACPI_FADT_S4_RTC_WAKE;
 106
 107         fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 108         fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
 109         fadt->x_pm1a_evt_blk.bit_offset = 0;
 110         fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
 111         fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
 112         fadt->x_pm1a_evt_blk.addrh = 0x0;
 113
 114         fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 115         fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
 116         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 117         fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
 118         fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
 119         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 120
 121         fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 122         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 123         fadt->x_pm_tmr_blk.bit_offset = 0;
 124         fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 125         fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
 126         fadt->x_pm_tmr_blk.addrh = 0x0;
 127
 128         fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 129         fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
 130         fadt->x_gpe0_blk.bit_offset = 0;
 131         fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
 132         fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
 133         fadt->x_gpe0_blk.addrh = 0x0;
 134 }