src/southbridge/intel/lynxpoint/smbus.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/path.h>
   5 #include <device/smbus.h>
   6 #include <device/pci.h>
   7 #include <device/pci_ids.h>
   8 #include <device/pci_ops.h>
   9 #include <device/smbus_host.h>
  10 #include <southbridge/intel/common/smbus_ops.h>
  11 #include "pch.h"
  12
  13 static void pch_smbus_init(struct device *dev)
  14 {
  15         struct resource *res;
  16
  17         /* Enable clock gating */
  18         pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
  19
  20         /* Set Receive Slave Address */
  21         res = probe_resource(dev, PCI_BASE_ADDRESS_4);
  22         if (res)
  23                 smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
  24 }
  25
  26 static struct device_operations smbus_ops = {
  27         .read_resources         = smbus_read_resources,
  28         .set_resources          = pci_dev_set_resources,
  29         .enable_resources       = pci_dev_enable_resources,
  30         .scan_bus               = scan_smbus,
  31         .init                   = pch_smbus_init,
  32         .ops_smbus_bus          = &lops_smbus_bus,
  33         .ops_pci                = &pci_dev_ops_pci,
  34 };
  35
  36 static const unsigned short pci_device_ids[] = {
  37         PCI_DID_INTEL_LPT_H_SMBUS,
  38         PCI_DID_INTEL_LPT_H_SMBUS_9,
  39         PCI_DID_INTEL_LPT_LP_SMBUS,
  40         PCI_DID_INTEL_WPT_LP_SMBUS,
  41         0
  42 };
  43
  44 static const struct pci_driver pch_smbus __pci_driver = {
  45         .ops     = &smbus_ops,
  46         .vendor  = PCI_VID_INTEL,
  47         .devices = pci_device_ids,
  48 };