soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off
[coreboot.git] / spd / lp4x / 
tree29e0d6f3eb03e82547dff4f334a9ff5f2f756420
drwxr-xr-x   ..
-rw-r--r-- 11019 memory_parts.json
-rw-r--r-- 118 platforms_manifest.generated.txt
drwxr-xr-x - set-0
drwxr-xr-x - set-1