src/mainboard/acer/aspire_vn7_572g/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <gpio.h>
   4 #include "include/gpio.h"
   5
   6 /*
   7  * TODO: Vendor configures many NC pads as _TERM_GPO. Why?
   8  * - On direction: Are some of these comments illusory? At least some pads
   9  *   are bidirectional on the other side of the GPIO.
  10  */
  11 /* NB: Do not reconfigure pads used by Optimus, their assertion state may be lost */
  12
  13 /*
  14  * TODO: Newgate-SLS and Rayleigh-SLS have PCH-H and use the same ProgramGPIOPei module.
  15  *       The GPIO tables retrieved from PCDs are ignored. However, progress on those SKUs
  16  *       is held up because the final table passed to function similar to RC's
  17  *       GpioConfigureSklPch() is neither, but a zero-assigned variable. The code may be
  18  *       computing and dereferencing address pointers from a blob of internal data.
  19  */
  20
  21 /* Pad configuration was generated automatically using intelp2m utility */
  22 static const struct pad_config gpio_table[] = {
  23         /* ------- GPIO Community 0 ------- */
  24
  25         /* ------- GPIO Group GPP_A ------- */
  26         // RCIN# <= H_RCIN#
  27         PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
  28         // LAD0 (ESPI_IO0) <=> LPC_AD_CPU_P0
  29         PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
  30         // LAD1 (ESPI_IO1) <=> LPC_AD_CPU_P1
  31         PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
  32         // LAD2 (ESPI_IO2) <=> LPC_AD_CPU_P2
  33         PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
  34         // LAD3 (ESPI_IO3) <=> LPC_AD_CPU_P3
  35         PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
  36         // LFRAME# (ESPI_CS#) => LPC_FRAME#_CPU
  37         PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
  38         // SERIRQ <=> INT_SERIRQ
  39         PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
  40         // PIRQA# = PIRQA#
  41         PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
  42         // CLKRUN# <= PM_CLKRUN#_EC
  43         PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
  44         // CLKOUT_LPC0 (ESPI_CLK) <= LPC_CLK_CPU_P0
  45         PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
  46         // CLKOUT_LPC1 <= LPC_CLK_CPU_P1
  47         PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
  48         // GPIO (PME#) // NC
  49         PAD_CFG_TERM_GPO(GPP_A11, 1, DN_20K, DEEP),
  50         // GPIO (SX_EXIT_HOLDOFF#/BM_BUSY#/ISH_GP6) <= GC6_FB_EN
  51         PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI),
  52         // SUSWARN#/SUSPWRDNACK = PM_SUSACK#
  53         PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
  54         // SUS_STAT# (ESPI_RESET#) => PM_SUS_STAT#
  55         PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
  56         // SUS_ACK# = PM_SUSACK#
  57         PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
  58         // GPIO (SD_1P8_SEL) // NC
  59         PAD_NC(GPP_A16, DN_20K),
  60         // GPIO (SD_PWR_EN#/ISH_GP7) // NC
  61         PAD_NC(GPP_A17, DN_20K),
  62         // GPIO (ISH_GP0) => GSENSOR_INT#
  63         PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, ACPI),
  64         // GPIO (ISH_GP1) // NC
  65         PAD_NC(GPP_A19, DN_20K),
  66         // GPIO (ISH_GP3) // NC
  67         PAD_NC(GPP_A21, DN_20K),
  68         // GPIO (ISH_GP4) <= GPU_EVENT#
  69         PAD_CFG_GPO(GPP_A22, 1, DEEP),
  70         // GPIO (ISH_GP5) // NC
  71         PAD_NC(GPP_A23, DN_20K),
  72
  73         /* ------- GPIO Group GPP_B ------- */
  74         // CORE_VID0 // V0.85A_VID0
  75         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  76         // CORE_VID1 // V0.85A_VID1
  77         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  78         // GPIO (CPU_GP2) <= TP_IN#
  79         // TODO: APIC-routed pads don't have host owners?
  80         PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, DEEP),
  81         // SRCCLKREQ0# <= PEG_CLKREQ_CPU#
  82         PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
  83         // SRCCLKREQ1# <= LAN_CLKREQ_CPU#
  84         PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  85         // SRCCLKREQ2# <= WLAN_CLKREQ_CPU#
  86         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
  87         // SRCCLKREQ3# <= MSATA_CLKREQ_CPU#
  88         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
  89         // SRCCLKREQ4# // SRCCLKREQ4# ("Remove TBT")
  90         PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
  91         // SRCCLKREQ5# // SRCCLKREQ5#
  92         PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
  93         // GPIO (EXT_PWR_GATE#) = EXT_PWR_GATE#
  94         PAD_CFG_TERM_GPO(GPP_B11, 1, DN_20K, DEEP),
  95         // GPIO (SLP_S0#) // NC
  96         PAD_CFG_TERM_GPO(GPP_B12, 1, DN_20K, DEEP),
  97         // PLTRST# => PLT_RST#
  98         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  99         // GPIO (SPKR) => HDA_SPKR (Strap - Top Swap Override)
 100         PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
 101         // GPIO (GSPI0_CS#) = TOUCH_DET#
 102         PAD_CFG_GPO(GPP_B15, 0, DEEP),
 103         // GPIO (GSPI0_CLK) // NC
 104         PAD_CFG_GPO(GPP_B16, 0, DEEP),
 105         // GPIO (GSPI0_MISO) // NC ("Remove TBT")
 106         PAD_CFG_GPI_SCI(GPP_B17, DN_20K, DEEP, EDGE_SINGLE, INVERT),
 107         // GPIO (GSPI0_MOSI) => GPP_B18/GSPI0_MOSI (Strap - No reboot)
 108         PAD_CFG_TERM_GPO(GPP_B18, 1, DN_20K, DEEP),
 109         // GPIO (GSPI1_CS#) => RTC_DET#
 110         PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI),
 111         // GPIO (GSPI1_CLK) <= PSW_CLR#
 112         PAD_CFG_GPI_TRIG_OWN(GPP_B20, DN_20K, DEEP, OFF, ACPI),
 113         // GPIO (GSPI1_MOSI) => GPP_B22/GSPI1_MOSI (Strap - Boot BIOS strap)
 114         PAD_CFG_TERM_GPO(GPP_B22, 1, DN_20K, DEEP),
 115         // GPIO (SML1ALERT#/PCHHOT#) => GPP_B23 (Strap)
 116         PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
 117
 118         /* ------- GPIO Community 1 ------- */
 119
 120         /* ------- GPIO Group GPP_C ------- */
 121         // SMBCLK <= SMB_CLK
 122         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 123         // SMBDATA = SMB_DATA
 124         PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
 125         // GPIO (SMBALERT#) => GPP_C2 (Strap - TLS Confidentiality)
 126         PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
 127         // GPIO (SML0CLK) // NC
 128         PAD_CFG_TERM_GPO(GPP_C3, 1, DN_20K, DEEP),
 129         // GPIO (SML0DATA) // NC
 130         PAD_CFG_TERM_GPO(GPP_C4, 1, DN_20K, DEEP),
 131         // GPIO (SML0ALERT#) // NC (Strap - eSPI or LPC)
 132         PAD_CFG_TERM_GPO(GPP_C5, 1, DN_20K, DEEP),
 133         // RESERVED (SML1CLK) <=> SML1_CLK (KBC)
 134         // RESERVED (SML1DATA) <=> SML1_DATA (KBC)
 135         // GPIO (UART0_RXD) // NC
 136         PAD_CFG_TERM_GPO(GPP_C8, 1, DN_20K, DEEP),
 137         // GPIO (UART0_TXD) // NC
 138         PAD_CFG_TERM_GPO(GPP_C9, 1, DN_20K, DEEP),
 139         // GPIO (UART0_RTS#) // NC
 140         PAD_CFG_TERM_GPO(GPP_C10, 1, DN_20K, DEEP),
 141         // GPIO (UART0_CTS#) // NC
 142         PAD_CFG_TERM_GPO(GPP_C11, 1, DN_20K, DEEP),
 143         // GPIO (UART1_RXD/ISH_UART1_RXD) // NC
 144         PAD_NC(GPP_C12, DN_20K),
 145         // GPIO (UART1_TXD/ISH_UART1_TXD) // NC
 146         PAD_NC(GPP_C13, DN_20K),
 147         // GPIO (UART1_RTS#/ISH_UART1_RTS#) // NC
 148         PAD_NC(GPP_C14, DN_20K),
 149         // GPIO (UART1_CTS#/ISH_UART1_CTS#) // NC
 150         PAD_NC(GPP_C15, DN_20K),
 151         // I2C0_SDA <=> I2C0_DATA_CPU (Touch Panel)
 152         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 153         // I2C0_SCL <=> I2C0_CLK_CPU (Touch Panel)
 154         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 155         // I2C1_SDA <=> I2C1_DATA_CPU (Touch Pad)
 156         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 157         // I2C1_SCL <=> I2C1_CLK_CPU (Touch Pad)
 158         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 159         // UART2_RXD = LPSS_UART2_RXD
 160         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 161         // UART2_TXD = LPSS_UART2_TXD
 162         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 163         // UART2_RTS# = LPSS_UART2_RTS#
 164         PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
 165         // UART2_CTS# = LPSS_UART2_CTS#
 166         PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
 167
 168         /* ------- GPIO Group GPP_D ------- */
 169         // GPIO (SPI1_CS#) // NC
 170         PAD_CFG_TERM_GPO(GPP_D0, 1, DN_20K, DEEP),
 171         // GPIO (SPI1_CLK) // NC
 172         PAD_CFG_TERM_GPO(GPP_D1, 1, DN_20K, DEEP),
 173         // SPI1_MISO // NC
 174         PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
 175         // SPI1_MOSI // NC
 176         PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
 177         // GPIO (FLASHTRIG) // NC
 178         PAD_CFG_TERM_GPO(GPP_D4, 1, DN_20K, DEEP),
 179         // GPIO (ISH_I2C0_SDA) // NC
 180         PAD_NC(GPP_D5, DN_20K),
 181         // GPIO (ISH_I2C0_SCL) // NC
 182         PAD_NC(GPP_D6, DN_20K),
 183         // GPIO (ISH_I2C1_SDA) // NC
 184         PAD_NC(GPP_D7, DN_20K),
 185         // GPIO (ISH_I2C1_SCL) // NC
 186         PAD_NC(GPP_D8, DN_20K),
 187         // GPIO // NC
 188         PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI),
 189         // GPIO => TOUCH_S_RST#
 190         PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI),
 191         // GPIO // NC
 192         PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI),
 193         // GPIO // NC ("Remove TBT")
 194         PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI),
 195         // GPIO (ISH_UART0_RXD/SML0BDATA/I2C4B_SDA) // NC
 196         PAD_CFG_TERM_GPO(GPP_D13, 1, DN_20K, DEEP),
 197         // GPIO (ISH_UART0_TXD/SML0BCLK/I2C4B_SCL) // NC
 198         PAD_CFG_TERM_GPO(GPP_D14, 1, DN_20K, DEEP),
 199         // GPIO (ISH_UART0_RTS#) // NC
 200         PAD_CFG_TERM_GPO(GPP_D15, 1, DN_20K, DEEP),
 201         // GPIO (ISH_UART0_CTS#/SML0BALERT#) // NC
 202         PAD_CFG_TERM_GPO(GPP_D16, 1, DN_20K, DEEP),
 203         // GPIO (DMIC_CLK1) // NC
 204         PAD_NC(GPP_D17, DN_20K),
 205         // GPIO (DMIC_DATA1) // NC
 206         PAD_NC(GPP_D18, DN_20K),
 207         // DMIC_CLK0 => DMIC_CLK_CON_R
 208         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 209         // DMIC_DATA0 => DMIC_PCH_DATA
 210         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 211         // SPI1_IO2 // NC
 212         PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 213         // SPI1_IO3 // NC
 214         PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
 215         // GPIO (I2S_MCLK) // NC
 216         PAD_NC(GPP_D23, DN_20K),
 217
 218         /* ------- GPIO Group GPP_E ------- */
 219         // SATAXPCIE0 (SATAGP0) = SATAGP0
 220         PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
 221         // SATAXPCIE1 (SATAGP1) // NC
 222         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 223         // SATAXPCIE2 (SATAGP2) = SATAGP2
 224         PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
 225         // GPIO (CPU_GP0) // NC
 226         PAD_CFG_GPO(GPP_E3, 1, DEEP),
 227         // GPIO (DEVSLP0) // NC ("Remove DEVSLP_PCH")
 228         PAD_CFG_TERM_GPO(GPP_E4, 1, DN_20K, DEEP),
 229         // GPIO (DEVSLP1) // NC
 230         PAD_CFG_TERM_GPO(GPP_E5, 1, DN_20K, DEEP),
 231         // GPIO (DEVSLP2) // NC
 232         PAD_CFG_TERM_GPO(GPP_E6, 1, DN_20K, DEEP),
 233         // GPIO (CPU_GP1) <= TOUCH_INT#
 234         PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, DEEP),
 235         // SATALED# = SATA_LED#
 236         PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
 237         // USB2_OC0# = USB_OC#
 238         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 239         // USB2_OC1# // USB_OC#
 240         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 241         // USB2_OC2# // USB_OC#
 242         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 243         // USB2_OC3# // USB_OC#
 244         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
 245         // DDPB_HPD0 <= DDI1_HDMI_HPD_CPU
 246         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 247         // DDPC_HPD1 // NC ("Remove HPD")
 248         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 249         // GPIO (DDPD_HPD2) <= EC_SMI#
 250         // FIXME: Vendor configures as _TERM_GPO. Why?
 251         PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, LEVEL, INVERT),
 252         // GPIO (DDPE_HPD3) <= EC_SCI#
 253         PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
 254         // EDP_HPD <= eDP_HPD_CPU
 255         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 256         // DDPB_CTRLCLK <=> DDI1_HDMI_CLK_CPU
 257         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
 258         // DDPB_CTRLDATA <=> DDI1_HDMI_DATA_CPU (Strap - Display Port B Detected)
 259         PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
 260         // DDPC_CTRLCLK // NC
 261         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 262         // DDPC_CTRLDATA => DDPC_CDA (Strap - Display Port C Detected)
 263         PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
 264         // GPIO // NC
 265         // TODO: Vendor configures as _GPIO_BIDIRECT. Why?
 266         PAD_NC(GPP_E22, NONE),
 267         // GPIO => DDPD_CDA (Strap - Display Port D Detected)
 268         PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),
 269
 270         /* ------- GPIO Community 2 ------- */
 271
 272         /* -------- GPIO Group GPD -------- */
 273         // GPIO (BATLOW#) = BATLOW
 274         PAD_CFG_TERM_GPO(GPD0, 1, DN_20K, PWROK),
 275         // ACPRESENT <= AC_PRESENT
 276         PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
 277         // GPIO (LAN_WAKE#) = GPD2/LAN_WAKE#
 278         PAD_CFG_TERM_GPO(GPD2, 1, DN_20K, PWROK),
 279         // PWRBTN# <= PM_PWRBTN#
 280         PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
 281         // SLP_S3# => PM_SLP_S3#
 282         PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
 283         // SLP_S4# => PM_SLP_S4#
 284         PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
 285         // SLP_A# // NC
 286         PAD_CFG_NF(GPD6, DN_20K, PWROK, NF1),
 287         // GPIO (RSVD#AT15) // NC
 288         PAD_CFG_TERM_GPO(GPD7, 1, DN_20K, PWROK),
 289         // SUSCLK => SUS_CLK_CPU
 290         PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
 291         // SLP_WLAN# // NC
 292         PAD_CFG_NF(GPD9, DN_20K, PWROK, NF1),
 293         // SLP_S5# // NC
 294         PAD_CFG_NF(GPD10, DN_20K, PWROK, NF1),
 295         // GPIO (LANPHYPC) // NC
 296         PAD_CFG_TERM_GPO(GPD11, 1, DN_20K, PWROK),
 297
 298         /* ------- GPIO Community 3 ------- */
 299
 300         /* ------- GPIO Group GPP_F ------- */
 301         // GPIO (I2S2_SCLK) // NC
 302         PAD_NC(GPP_F0, DN_20K),
 303         // GPIO (I2S2_SFRM) // NC
 304         PAD_NC(GPP_F1, DN_20K),
 305         // GPIO (I2S2_TXD) // NC
 306         PAD_NC(GPP_F2, DN_20K),
 307         // GPIO (I2S2_RXD) // NC
 308         PAD_NC(GPP_F3, DN_20K),
 309         // GPIO (I2C2_SDA) // NC
 310         PAD_NC(GPP_F4, DN_20K),
 311         // GPIO (I2C2_SCL) // NC
 312         PAD_NC(GPP_F5, DN_20K),
 313         // GPIO (I2C3_SDA) // NC
 314         PAD_NC(GPP_F6, DN_20K),
 315         // GPIO (I2C3_SCL) // NC
 316         PAD_NC(GPP_F7, DN_20K),
 317         // GPIO (I2C4_SDA) // NC
 318         PAD_CFG_TERM_GPO(GPP_F8, 1, DN_20K, DEEP),
 319         // GPIO (I2C4_SCL) // NC
 320         PAD_CFG_TERM_GPO(GPP_F9, 1, DN_20K, DEEP),
 321         // GPIO (I2C5_SDA/ISH_I2C2_SDA) // NC
 322         PAD_NC(GPP_F10, DN_20K),
 323         // GPIO (I2C5_SCL/ISH_I2C2_SCL) // NC
 324         PAD_NC(GPP_F11, DN_20K),
 325         // GPIO (EMMC_CMD) // NC
 326         PAD_NC(GPP_F12, DN_20K),
 327         // GPIO (EMMC_DATA0) // NC
 328         PAD_NC(GPP_F13, DN_20K),
 329         // GPIO (EMMC_DATA1) // NC
 330         PAD_NC(GPP_F14, DN_20K),
 331         // GPIO (EMMC_DATA2) // NC
 332         PAD_NC(GPP_F15, DN_20K),
 333         // GPIO (EMMC_DATA3) // NC
 334         PAD_NC(GPP_F16, DN_20K),
 335         // GPIO (EMMC_DATA4) // NC
 336         PAD_NC(GPP_F17, DN_20K),
 337         // GPIO (EMMC_DATA5) // NC
 338         PAD_NC(GPP_F18, DN_20K),
 339         // GPIO (EMMC_DATA6) // NC
 340         PAD_NC(GPP_F19, DN_20K),
 341         // GPIO (EMMC_DATA7) // NC
 342         PAD_NC(GPP_F20, DN_20K),
 343         // GPIO (EMMC_RCLK) // NC
 344         PAD_NC(GPP_F21, DN_20K),
 345         // GPIO (EMMC_CLK) // NC
 346         PAD_NC(GPP_F22, DN_20K),
 347         // GPIO // NC
 348         PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP),
 349
 350         /* ------- GPIO Group GPP_G ------- */
 351         // GPIO (SD_CMD) // NC
 352         PAD_NC(GPP_G0, DN_20K),
 353         // GPIO (SD_DATA0) // NC
 354         PAD_NC(GPP_G1, DN_20K),
 355         // GPIO (SD_DATA1) // NC
 356         PAD_NC(GPP_G2, DN_20K),
 357         // GPIO (SD_DATA2) // NC
 358         PAD_NC(GPP_G3, DN_20K),
 359         // GPIO (SD_DATA3) // NC
 360         // TODO: Vendor configures as _GPO. Why?
 361         PAD_NC(GPP_G4, NONE),
 362         // GPIO (SD_CD#) // NC
 363         PAD_NC(GPP_G5, DN_20K),
 364         // GPIO (SD_CLK) // NC
 365         PAD_NC(GPP_G6, DN_20K),
 366         // GPIO (SD_WP) // NC
 367         PAD_NC(GPP_G7, DN_20K),
 368 };
 369
 370 void mainboard_config_stage_gpios(void)
 371 {
 372         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 373 }