src/mainboard/amd/chausie/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/amd/mendocino
   4         register "common_config.espi_config" = "{
   5                 .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
   6                 .generic_io_range[0] = {
   7                         .base = 0x3f8,
   8                         .size = 8,
   9                 },
  10                 .generic_io_range[1] = {
  11                         .base = 0x600,
  12                         .size = 256,
  13                 },
  14                 .io_mode = ESPI_IO_MODE_QUAD,
  15                 .op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
  16                 .crc_check_enable = 1,
  17                 .alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
  18                 .periph_ch_en = 1,
  19                 .vw_ch_en = 1,
  20                 .oob_ch_en = 1,
  21                 .flash_ch_en = 0,
  22         }"
  23
  24         register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
  25                                         GPIO_I2C2_SCL | GPIO_I2C3_SCL"
  26
  27         register "i2c[0].early_init" = "1"
  28         register "i2c[1].early_init" = "1"
  29         register "i2c[2].early_init" = "1"
  30         register "i2c[3].early_init" = "1"
  31
  32         # I2C Pad Control RX Select Configuration
  33         register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
  34         register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
  35         register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
  36         register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
  37
  38         register "s0ix_enable" = "true"
  39
  40         register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
  41
  42         register "usb_phy_custom" = "1"
  43         register "usb_phy" = "{
  44                 .Usb2PhyPort[0] = {
  45                         .compdistune = 0x3,
  46                         .pllbtune = 0x1,
  47                         .pllitune = 0x0,
  48                         .pllptune = 0xe,
  49                         .sqrxtune = 0x3,
  50                         .txfslstune = 0x3,
  51                         .txpreempamptune = 0x2,
  52                         .txpreemppulsetune = 0x0,
  53                         .txrisetune = 0x1,
  54                         .txvreftune = 0x3,
  55                         .txhsxvtune = 0x3,
  56                         .txrestune = 0x2,
  57                 },
  58                 .Usb2PhyPort[1] = {
  59                         .compdistune = 0x3,
  60                         .pllbtune = 0x1,
  61                         .pllitune = 0x0,
  62                         .pllptune = 0xe,
  63                         .sqrxtune = 0x3,
  64                         .txfslstune = 0x3,
  65                         .txpreempamptune = 0x2,
  66                         .txpreemppulsetune = 0x0,
  67                         .txrisetune = 0x1,
  68                         .txvreftune = 0x3,
  69                         .txhsxvtune = 0x3,
  70                         .txrestune = 0x2,
  71                 },
  72                 .Usb2PhyPort[2] = {
  73                         .compdistune = 0x3,
  74                         .pllbtune = 0x1,
  75                         .pllitune = 0x0,
  76                         .pllptune = 0xe,
  77                         .sqrxtune = 0x3,
  78                         .txfslstune = 0x3,
  79                         .txpreempamptune = 0x2,
  80                         .txpreemppulsetune = 0x0,
  81                         .txrisetune = 0x1,
  82                         .txvreftune = 0x3,
  83                         .txhsxvtune = 0x3,
  84                         .txrestune = 0x2,
  85                 },
  86                 .Usb2PhyPort[3] = {
  87                         .compdistune = 0x3,
  88                         .pllbtune = 0x1,
  89                         .pllitune = 0x0,
  90                         .pllptune = 0xe,
  91                         .sqrxtune = 0x3,
  92                         .txfslstune = 0x3,
  93                         .txpreempamptune = 0x2,
  94                         .txpreemppulsetune = 0x0,
  95                         .txrisetune = 0x1,
  96                         .txvreftune = 0x3,
  97                         .txhsxvtune = 0x3,
  98                         .txrestune = 0x2,
  99                 },
 100                 .Usb2PhyPort[4] = {
 101                         .compdistune = 0x3,
 102                         .pllbtune = 0x1,
 103                         .pllitune = 0x0,
 104                         .pllptune = 0xe,
 105                         .sqrxtune = 0x3,
 106                         .txfslstune = 0x3,
 107                         .txpreempamptune = 0x2,
 108                         .txpreemppulsetune = 0x0,
 109                         .txrisetune = 0x1,
 110                         .txvreftune = 0x3,
 111                         .txhsxvtune = 0x3,
 112                         .txrestune = 0x2,
 113                 },
 114                 .Usb2PhyPort[5] = {
 115                         .compdistune = 0x3,
 116                         .pllbtune = 0x1,
 117                         .pllitune = 0x0,
 118                         .pllptune = 0xe,
 119                         .sqrxtune = 0x3,
 120                         .txfslstune = 0x3,
 121                         .txpreempamptune = 0x2,
 122                         .txpreemppulsetune = 0x0,
 123                         .txrisetune = 0x1,
 124                         .txvreftune = 0x3,
 125                         .txhsxvtune = 0x3,
 126                         .txrestune = 0x2,
 127                 },
 128                 .Usb3PhyPort[0] = {
 129                         .tx_term_ctrl = 0x2,
 130                         .rx_term_ctrl = 0x2,
 131                         .tx_vboost_lvl_en = 0x0,
 132                         .tx_vboost_lvl = 0x5,
 133                 },
 134                 .Usb3PhyPort[1] = {
 135                         .tx_term_ctrl = 0x2,
 136                         .rx_term_ctrl = 0x2,
 137                         .tx_vboost_lvl_en = 0x0,
 138                         .tx_vboost_lvl = 0x5,
 139                 },
 140                 .Usb3PhyPort[2] = {
 141                         .tx_term_ctrl = 0x2,
 142                         .rx_term_ctrl = 0x2,
 143                         .tx_vboost_lvl_en = 0x0,
 144                         .tx_vboost_lvl = 0x5,
 145                 },
 146                 .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
 147                 .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
 148                 .BatteryChargerEnable = 0,
 149                 .PhyP3CpmP4Support = 0,
 150         }"
 151
 152         register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 153         register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 154         register "gpp_clk_config[2]" = "GPP_CLK_OFF"
 155         register "gpp_clk_config[3]" = "GPP_CLK_REQ"
 156
 157         device domain 0 on
 158                 device ref iommu on end
 159                 device ref gpp_bridge_0 on end # GBE
 160                 device ref gpp_bridge_1 on end # WIFI
 161                 device ref gpp_bridge_2 on end # NVMe SSD
 162                 device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 163                         device ref gfx on end # Internal GPU (GFX)
 164                         device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
 165                         device ref crypto on end # Crypto Coprocessor
 166                         device ref xhci_0 on # USB 3.1 (USB0)
 167                                 chip drivers/usb/acpi
 168                                         device ref xhci_0_root_hub on
 169                                                 chip drivers/usb/acpi
 170                                                         device ref usb3_port0 on end
 171                                                 end
 172                                                 chip drivers/usb/acpi
 173                                                         device ref usb2_port0 on end
 174                                                 end
 175                                                 chip drivers/usb/acpi
 176                                                         device ref usb2_port1 on end
 177                                                 end
 178                                         end
 179                                 end
 180                         end
 181                         device ref xhci_1 on # USB 3.1 (USB1)
 182                                 chip drivers/usb/acpi
 183                                         device ref xhci_1_root_hub on
 184                                                 chip drivers/usb/acpi
 185                                                         device ref usb3_port2 on end
 186                                                 end
 187                                                 chip drivers/usb/acpi
 188                                                         device ref usb3_port3 on end
 189                                                 end
 190                                                 chip drivers/usb/acpi
 191                                                         device ref usb2_port2 on end
 192                                                 end
 193                                                 chip drivers/usb/acpi
 194                                                         device ref usb2_port3 on end
 195                                                 end
 196                                                 chip drivers/usb/acpi
 197                                                         device ref usb2_port4 on end
 198                                                 end
 199                                         end
 200                                 end
 201                         end
 202                         device ref acp on end # Audio Processor (ACP)
 203                         device ref mp2 on end # Sensor Fusion Hub (MP2)
 204                 end
 205                 device ref gpp_bridge_c on  # Internal GPP Bridge 2 to Bus C
 206                         device ref xhci_2 on
 207                                 ops xhci_pci_ops
 208                                 chip drivers/usb/acpi
 209                                         register "type" = "UPC_TYPE_HUB"
 210                                         device usb 0.0 alias xhci_2_root_hub on
 211                                                 chip drivers/usb/acpi
 212                                                         device usb 2.0 alias usb2_port5 on end
 213                                                 end
 214                                         end
 215                                 end
 216                         end
 217                 end
 218         end
 219
 220         device ref i2c_0 on end
 221         device ref i2c_1 on end
 222         device ref i2c_2 on end
 223         device ref i2c_3 on end
 224         device ref uart_0 on end # UART0
 225
 226 end