1 # SPDX
-License
-Identifier
: GPL
-2.0-only
3 chip northbridge
/intel
/sandybridge
4 register
"spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
6 subsystemid
0x1028 0x04aa inherit
7 chip southbridge
/intel
/bd82x6x # Intel Series
6 Cougar Point PCH
8 register
"docking_supported" = "0"
9 register
"pcie_port_coalesce" = "1"
11 register
"usb_port_config" = "{
16 { 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3510)=0x3510
17 { 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3514)=0x3514
20 { 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x3520)=0x3520
23 { 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x352c)=0x352c
28 device ref mei1 on
end
29 device ref ehci2 on
end
30 device ref pcie_rp1 on
end
31 device ref pcie_rp4 on
end
32 device ref pcie_rp5 on
end
33 device ref ehci1 on
end
35 register
"gen1_dec" = "0x003c0a01"
36 register
"spi_lvscc" = "0x2005"
37 register
"spi_uvscc" = "0x2005"
40 register
"sata_interface_speed_support" = "0x3"
41 register
"sata_port_map" = "0x1f"
43 device ref smbus on
end
45 device ref host_bridge on
end
46 device ref peg10 on
end