src/mainboard/hardkernel/odroid-h4/devicetree.cb

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/alderlake
   4         register "pmc_gpe0_dw0" = "PMC_GPP_A"
   5         register "pmc_gpe0_dw1" = "PMC_GPP_R"
   6         register "pmc_gpe0_dw2" = "PMC_GPD"
   7
   8         register "sagv" = "CONFIG(ODROID_H4_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled"
   9
  10         register "enable_c6dram" = "true"
  11
  12         register "tcc_offset" = "10" # TCC of 90C
  13
  14         device domain 0 on
  15                 device ref igpu on
  16                         register "ddi_portA_config" = "1"
  17                         register "ddi_portB_config" = "1"
  18                         register "ddi_ports_config" = "{
  19                                 [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  20                                 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  21                                 [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  22                         }"
  23                 end
  24                 device ref xhci on
  25                         ## Yes, the numbering of the three USB2 ports routed to the EXT_HEAD1
  26                         ## pin header does not correlate with the numbering of the USB2 ports
  27                         ## on the ADL-N SoC. But schematics and lsusb agree with the mapping.
  28                         ##
  29                         ## For onboard USB Type-A ports, tune PHYs for short trace lengths as
  30                         ## the ODROID-H4 is a tiny board (and exact trace length is unknown).
  31                         ##
  32                         ## The USB2 ports on the EXT_HEAD1 pin header are meant to be cabled.
  33                         ## So, have these ports use medium trace length PHY settings instead.
  34
  35                         register "usb2_ports" = "{
  36
  37 #define ODROID_H4_USB2_PORT_REAR { \
  38         .enable        = 1, \
  39         .ocpin         = OC_SKIP, \
  40         .tx_bias       = USB2_BIAS_0MV, \
  41         .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
  42         .pre_emp_bias  = USB2_BIAS_16P9MV, \
  43         .pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
  44 }
  45
  46                                 [0] = ODROID_H4_USB2_PORT_REAR,         // USB3_LAN1 Bottom
  47                                 [1] = ODROID_H4_USB2_PORT_REAR,         // USB3_LAN1 Top
  48                                 [2] = USB2_PORT_MID(OC_SKIP),           // EXT_HEAD1 P7
  49                                 [3] = USB2_PORT_MID(OC_SKIP),           // EXT_HEAD1 P5
  50                                 [4] = ODROID_H4_USB2_PORT_REAR,         // USBLAN1   Top
  51                                 [5] = USB2_PORT_MID(OC_SKIP),           // EXT_HEAD1 P6
  52                                 [6] = ODROID_H4_USB2_PORT_REAR,         // USBLAN1   Bottom
  53                         }"
  54                         register "usb3_ports" = "{
  55                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       // USB3_LAN1 Bottom
  56                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       // USB3_LAN1 Top
  57                         }"
  58
  59                         chip drivers/usb/acpi
  60                                 device ref xhci_root_hub on
  61                                         chip drivers/usb/acpi
  62                                                 register "desc" = ""USB3 Type-A (Bottom Right)""
  63                                                 register "type" = "UPC_TYPE_USB3_A"
  64                                                 device ref usb2_port1 on end
  65                                                 device ref usb3_port1 on end
  66                                         end
  67                                         chip drivers/usb/acpi
  68                                                 register "desc" = ""USB3 Type-A (Top Right)""
  69                                                 register "type" = "UPC_TYPE_USB3_A"
  70                                                 device ref usb2_port2 on end
  71                                                 device ref usb3_port2 on end
  72                                         end
  73                                         chip drivers/usb/acpi
  74                                                 register "desc" = ""USB2 P7 (EXT_HEAD1)""
  75                                                 register "type" = "UPC_TYPE_PROPRIETARY"
  76                                                 device ref usb2_port3 on end
  77                                         end
  78                                         chip drivers/usb/acpi
  79                                                 register "desc" = ""USB2 P5 (EXT_HEAD1)""
  80                                                 register "type" = "UPC_TYPE_PROPRIETARY"
  81                                                 device ref usb2_port4 on end
  82                                         end
  83                                         chip drivers/usb/acpi
  84                                                 register "desc" = ""USB2 Type-A (Top Left)""
  85                                                 register "type" = "UPC_TYPE_A"
  86                                                 device ref usb2_port5 on end
  87                                         end
  88                                         chip drivers/usb/acpi
  89                                                 register "desc" = ""USB2 P6 (EXT_HEAD1)""
  90                                                 register "type" = "UPC_TYPE_PROPRIETARY"
  91                                                 device ref usb2_port6 on end
  92                                         end
  93                                         chip drivers/usb/acpi
  94                                                 register "desc" = ""USB2 Type-A (Bottom Left)""
  95                                                 register "type" = "UPC_TYPE_A"
  96                                                 device ref usb2_port7 on end
  97                                         end
  98                                 end
  99                         end
 100                 end
 101                 device ref i2c0 on
 102                         register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
 103                         register "common_soc_config.i2c[0]" = "{
 104                                 .speed = I2C_SPEED_FAST,
 105                                 .rise_time_ns = 80,
 106                                 .fall_time_ns = 110,
 107                         }"
 108                 end
 109                 device ref i2c1 on
 110                         register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
 111                         register "common_soc_config.i2c[1]" = "{
 112                                 .speed = I2C_SPEED_FAST,
 113                                 .rise_time_ns = 80,
 114                                 .fall_time_ns = 110,
 115                         }"
 116                 end
 117                 device ref emmc on
 118                         register "emmc_enable_hs400_mode" = "true"
 119                 end
 120                 device ref pcie_rp3 on  # LAN1
 121                         register "pch_pcie_rp[PCH_RP(3)]" = "{
 122                                 .clk_src = 1,
 123                                 .clk_req = 1,
 124                                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
 125                         }"
 126                 end
 127                 device ref pcie_rp4 on  # LAN2
 128                         register "pch_pcie_rp[PCH_RP(4)]" = "{
 129                                 .clk_src = 2,
 130                                 .clk_req = 2,
 131                                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
 132                         }"
 133                 end
 134                 device ref pcie_rp7 on  # ASM1064B SATA
 135                         register "pch_pcie_rp[PCH_RP(7)]" = "{
 136                                 .clk_src = 3,
 137                                 .clk_req = 3,   // Use hardwired CLKREQ# to allow clock gating
 138                                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
 139                         }"
 140                 end
 141                 device ref pcie_rp9 on  # M.2 M (x4)
 142                         register "pch_pcie_rp[PCH_RP(9)]" = "{
 143                                 .clk_src = 0,
 144                                 .clk_req = 0,
 145                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
 146                         }"
 147                         smbios_slot_desc        "SlotTypeM2Socket3" "SlotLengthOther"
 148                                                 "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X"
 149                 end
 150                 device ref pch_espi on
 151                         register "gen1_dec" = "0x00fc0201"
 152                         register "gen2_dec" = "0x007c0a01"
 153                         register "gen3_dec" = "0x000c03e1"
 154                         register "gen4_dec" = "0x001c02e1"
 155
 156                         chip superio/ite/it8613e
 157                                 register "ec.vin_mask" = "VIN0 | VIN1 | VIN2 | VIN4 | VIN5"
 158                                 # TODO: figure out how to make PECI work
 159                                 register "TMPIN1.mode" = "THERMAL_DIODE"
 160                                 #register "TMPIN1.mode" = "THERMAL_PECI"
 161                                 #register "TMPIN1.offset" = "0x56"
 162                                 register "FAN2" = "{
 163                                         .mode = FAN_SMART_AUTOMATIC,
 164                                         .smart = {
 165                                                 .tmpin     =  1,
 166                                                 .tmp_off   = 20,
 167                                                 .tmp_start = 35,
 168                                                 .tmp_full  = 70,
 169                                                 .tmp_delta =  1,
 170                                                 .pwm_start = 20,
 171                                                 .slope     =  3,
 172                                                 .smoothing =  0,
 173                                         },
 174                                 }"
 175
 176                                 device pnp 2e.1 on      # COM 1
 177                                         io 0x60 = 0x3f8
 178                                         irq 0x70 = 4
 179                                         irq 0xf0 = 0x01
 180                                 end
 181                                 device pnp 2e.4 on      # Environment Controller
 182                                         io 0x60 = 0xa30
 183                                         io 0x62 = 0xa20
 184                                         irq 0x70 = 0x00
 185                                         irq 0xf0 = 0x80
 186                                         irq 0xfc = 0xa0
 187                                 end
 188                                 device pnp 2e.5 off end # Keyboard
 189                                 device pnp 2e.6 off end # Mouse
 190                                 device pnp 2e.7 on      # GPIO
 191                                         io 0x60 = 0xa10
 192                                         io 0x62 = 0xa00
 193                                 end
 194                                 device pnp 2e.a off end # CIR
 195                         end
 196                 end
 197                 device ref hda on
 198                         register "pch_hda_dsp_enable"                   = "true"
 199                         register "pch_hda_sdi_enable[0]"                = "true"
 200                         register "pch_hda_audio_link_hda_enable"        = "true"
 201                         register "pch_hda_idisp_codec_enable"           = "true"
 202                         register "pch_hda_idisp_link_frequency"         = "HDA_LINKFREQ_96MHZ"
 203                         register "pch_hda_idisp_link_tmode"             = "HDA_TMODE_8T"
 204                 end
 205                 device ref smbus on end
 206
 207                 chip drivers/crb
 208                         device mmio 0xfed40000 on end
 209                 end
 210         end
 211 end