src/mainboard/intel/cedarisland_crb/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <device/pci_def.h>
   5 #include <device/pci_ops.h>
   6 #include <intelblocks/lpc_lib.h>
   7 #include <intelblocks/pcr.h>
   8 #include <soc/pci_devs.h>
   9 #include <soc/pcr_ids.h>
  10 #include <superio/aspeed/ast2400/ast2400.h>
  11 #include <superio/aspeed/common/aspeed.h>
  12 #include "include/gpio.h"
  13
  14 void bootblock_mainboard_early_init(void)
  15 {
  16         /* Configure Lewisburg PCH GPIOs */
  17         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
  18
  19         /* Enable COM1 only */
  20         pcr_write32(PID_DMI, 0x2770, 0);
  21         pcr_write32(PID_DMI, 0x2774, 1);
  22
  23         /* Decode for SuperIO (0x2e) and COM1 (0x3f8) */
  24         pci_s_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16));
  25
  26         const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1);
  27         aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
  28 }