1 chip northbridge
/intel
/sandybridge
3 register
"gfx" = "GMA_STATIC_DISPLAYS(0)"
5 # Enable DisplayPort
1 Hotplug with
6ms pulse
6 register
"gpu_dp_d_hotplug" = "0x06"
8 # Enable DisplayPort
0 Hotplug with
6ms pulse
9 register
"gpu_dp_c_hotplug" = "0x06"
11 # Enable DVI Hotplug with
6ms pulse
12 register
"gpu_dp_b_hotplug" = "0x06"
14 #
1333MHz RAM frequency
15 register
"max_mem_clock_mhz" = "666"
16 register
"spd_addresses" = "{0x50, 0, 0x51, 0}"
19 device ref host_bridge on
end # Host bridge
20 device ref peg10 off
end # PCIe Bridge
for discrete graphics
21 device ref igd on
end # Internal graphics VGA controller
23 chip southbridge
/intel
/bd82x6x # Intel Series
6 Cougar Point PCH
24 register
"sata_port_map" = "0x1"
25 register
"spi_lvscc" = "0x2005"
26 register
"spi_uvscc" = "0x2005"
28 register
"gen1_dec" = "0x00fc0a01" # SuperIO @
0xa00-0xaff
30 register
"usb_port_config" = "{
31 {1, 1, 0}, /* back, towards HDMI plugs */
32 {1, 1, 0}, /* back, towards power plug */
33 {1, 1, 1}, /* half-width miniPCIe */
34 {1, 1, 1}, /* full-width miniPCIe */
35 {1, 1, 2}, /* front-panel header */
36 {1, 1, 2}, /* front-panel header */
37 {1, 1, 3}, /* front connector */
38 {0, 1, 3}, /* not available x7 */
47 device ref xhci off
end # USB xHCI
48 device ref mei1 on
end # Management Engine Interface
1
49 device ref mei2 off
end # Management Engine Interface
2
50 device ref me_ide_r off
end # Management Engine IDE
-R
51 device ref me_kt off
end # Management Engine KT
52 device ref gbe on
end # Intel Gigabit Ethernet
53 device ref ehci2 off
end # USB2 EHCI #
2
54 device ref hda on
end # HD Audio controller
55 device ref pcie_rp1 on
end # PCIe Port #
1 (unused
)
56 device ref pcie_rp2 on
end # PCIe Port #
2 (full
-length mPCIe
/mSATA
)
57 device ref pcie_rp3 on
end # PCIe Port #
3 (half
-length mPCIe
)
58 device ref pcie_rp4 off
end # PCIe Port #
4
59 device ref pcie_rp5 off
end # PCIe Port #
5
60 device ref pcie_rp6 off
end # PCIe Port #
6
61 device ref pcie_rp7 off
end # PCIe Port #
7
62 device ref pcie_rp8 off
end # PCIe Port #
8
63 device ref ehci1 on
end # USB2 EHCI #
1
64 device ref pci_bridge off
end # PCI bridge
65 device ref lpc on # LPC bridge
66 chip superio
/nuvoton
/nct6776
67 device pnp
4e
.0 off
end # Floppy
68 device pnp
4e
.1 off
end # Parallel port
69 device pnp
4e
.2 on # COM1
73 device pnp
4e
.3 off
end # COM2
, IR
74 device pnp
4e
.5 off
end # Keyboard
75 device pnp
4e
.6 off
end # CIR
76 device pnp
4e
.7 on
end # GPIO6
77 device pnp
4e
.107 on
end # GPIO7
78 device pnp
4e
.207 off
end # GPIO8
79 device pnp
4e
.307 off
end # GPIO9
80 device pnp
4e
.8 off
end # WDT
81 device pnp
4e
.108 on
end # GPIO0
82 device pnp
4e
.208 off
end # GPIOA
83 device pnp
4e
.308 on # GPIOBASE
86 device pnp
4e
.109 off
end # GPIO1
87 device pnp
4e
.209 on
end # GPIO2
88 device pnp
4e
.309 off
end # GPIO3
89 device pnp
4e
.409 off
end # GPIO4
90 device pnp
4e
.509 off
end # GPIO5
91 device pnp
4e
.609 off
end # GPIO6
92 device pnp
4e
.709 off
end # GPIO7
93 device pnp
4e.a on
end # ACPI
94 device pnp
4e.b on # HWM
, front panel LED
98 device pnp
4e.d off
end # VID
99 device pnp
4e.e off
end # CIR WAKE
-UP
100 device pnp
4e.f off
end # GPIO
101 device pnp
4e
.14 off
end # SVID
102 device pnp
4e
.16 off
end # Deep sleep
103 device pnp
4e
.17 off
end # GPIOA
106 device ref sata1 on
end # SATA Controller
1
107 device ref smbus on
end # SMBus
108 device ref sata2 off
end # SATA Controller
2
109 device ref thermal off
end # Thermal