src/mainboard/intel/harcuvar/devicetree.cb

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/denverton_ns
   4
   5         # configure pirq routing
   6         register "pirqa_routing" = "11"
   7         register "pirqb_routing" = "10"
   8         register "pirqc_routing" = "06"
   9         register "pirqd_routing" = "07"
  10         register "pirqe_routing" = "12"
  11         register "pirqf_routing" = "14"
  12         register "pirqg_routing" = "15"
  13         register "pirqh_routing" = "15"
  14         # configure device interrupt routing
  15         register "ir00_routing" = "0x3217" # IR00, Dev31
  16         register "ir01_routing" = "0x3210" # IR01, Dev22
  17         register "ir02_routing" = "0x3211" # IR02, Dev23
  18         register "ir03_routing" = "0x3217" # IR03, Dev5
  19         register "ir04_routing" = "0x3212" # IR04, Dev6
  20         register "ir05_routing" = "0x3210" # IR05, Dev24
  21         register "ir06_routing" = "0x3214" # IR06, Dev19
  22         register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12
  23         register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17
  24         register "ir09_routing" = "0x3213" # IR09, Dev21
  25         register "ir10_routing" = "0x3210" # IR10, Dev26/18
  26         register "ir11_routing" = "0x3215" # IR11, Dev20
  27         register "ir12_routing" = "0x3210" # IR12, Dev27
  28         # configure interrupt polarity control
  29         register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
  30         register "ipc1" = "0x00000000" # IPC1
  31         register "ipc2" = "0x00000000" # IPC2
  32         register "ipc3" = "0x00000000" # IPC3
  33
  34         device cpu_cluster 0 on end
  35
  36         device domain 0 on
  37                 device pci 00.0 on end # Host Bridge
  38                 device pci 04.0 on end # RAS
  39                 device pci 05.0 on end # RCEC(Root Complex Event Collector)
  40                 device pci 06.0 on end # Virtual root port 2 (QAT)
  41                 device pci 09.0 on end # PCI Express Port 0, cluster #0, x8
  42                 device pci 0e.0 on end # PCI Express Port 4, cluster #1, x4
  43                 device pci 10.0 on end # PCI Express Port 6, cluster #1, x4
  44                 device pci 12.0 on end # SMBus Controller 1
  45                 device pci 14.0 on end # SATA Controller 1
  46                 device pci 15.0 on end # XHCI USB Controller
  47                 device pci 16.0 on end # Virtual root port 0 (10GBE0)
  48                 device pci 17.0 on end # Virtual root port 1 (10GBE1)
  49                 device pci 18.0 on end # CSME HECI 1
  50                 device pci 1a.0 on end # UART 0
  51                 device pci 1a.1 on end # UART 1
  52                 device pci 1a.2 on end # UART 2
  53                 device pci 1c.0 on end # eMMC
  54                 device pci 1f.0 on end # LPC bridge
  55                 device pci 1f.2 on end # PMC/ACPI
  56                 device pci 1f.4 on end # SMBus Controller 0
  57                 device pci 1f.5 on end # SPI Controller
  58         end
  59 end