mb/ocp/tiogapass: Fix GPIOs
[coreboot2.git] / src / mainboard / intel / kunimitsu / cmos.layout
blobcff042a15c87d93452f7296e796f82d0814d8dfe
1 ## SPDX-License-Identifier: GPL-2.0-only
3 # -----------------------------------------------------------------
4 entries
6 #start-bit length  config config-ID     name
8 # -----------------------------------------------------------------
9 0       120     r       0       reserved_memory
11 # -----------------------------------------------------------------
12 # RTC_BOOT_BYTE (coreboot hardcoded)
13 384     1       e       4       boot_option
14 388     4       h       0       reboot_counter
16 # -----------------------------------------------------------------
17 # coreboot config options: console
18 395     4       e       6       debug_level
20 # coreboot config options: southbridge
21 408     1       e       1       nmi
22 409     2       e       7       power_on_after_fail
24 # coreboot config options: bootloader
25 #Used by ChromeOS:
26 416     128     r       0       vbnv
28 # coreboot config options: check sums
29 984     16      h       0       check_sum
31 # -----------------------------------------------------------------
33 enumerations
35 #ID     value   text
36 1       0       Disable
37 1       1       Enable
38 4       0       Fallback
39 4       1       Normal
40 6       0       Emergency
41 6       1       Alert
42 6       2       Critical
43 6       3       Error
44 6       4       Warning
45 6       5       Notice
46 6       6       Info
47 6       7       Debug
48 6       8       Spew
49 7       0       Disable
50 7       1       Enable
51 7       2       Keep
52 # -----------------------------------------------------------------
53 checksums
55 checksum 392 415 984