mb/ocp/tiogapass: Fix GPIOs
[coreboot2.git] / src / mainboard / lenovo / m920q / cmos.layout
blob4dea5d246971d216fb0dcbbb79b738b657baf0c5
1 ## SPDX-License-Identifier: GPL-2.0-only
3 # -----------------------------------------------------------------
4 entries
6 #start-bit length  config config-ID     name
8 # -----------------------------------------------------------------
9 0       120     r       0       reserved_memory
11 # -----------------------------------------------------------------
12 # RTC_BOOT_BYTE (coreboot hardcoded)
13 384     1       e       4       boot_option
14 388     4       h       0       reboot_counter
16 # -----------------------------------------------------------------
17 # coreboot config options: console
18 395     4       e       6       debug_level
20 # coreboot config options: cpu
21 400     1       e       2       hyper_threading
23 # coreboot config options: southbridge
24 409     2       e       7       power_on_after_fail
26 # coreboot config options: bootloader
27 #Used by ChromeOS:
28 416     128     r       0       vbnv
30 # coreboot config options: check sums
31 984     16      h       0       check_sum
33 # -----------------------------------------------------------------
35 enumerations
37 #ID     value   text
38 1       0       Disable
39 1       1       Enable
40 2       0       Disable
41 2       1       Enable
42 4       0       Fallback
43 4       1       Normal
44 6       0       Emergency
45 6       1       Alert
46 6       2       Critical
47 6       3       Error
48 6       4       Warning
49 6       5       Notice
50 6       6       Info
51 6       7       Debug
52 6       8       Spew
53 7       0       Disable
54 7       1       Enable
55 7       2       Keep
56 # -----------------------------------------------------------------
57 checksums
59 checksum 392 415 984