mb/ocp/tiogapass: Fix GPIOs
[coreboot2.git] / src / mainboard / protectli / vault_cml / mainboard.c
blob1e06fc5feeefbdb7ef5ebe2a8611074adc452ee5
2 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 #include <console/console.h>
5 #include <cpu/x86/name.h>
6 #include <device/device.h>
7 #include <device/mmio.h>
8 #include <intelblocks/cse.h>
9 #include <pc80/i8254.h>
10 #include <soc/intel/common/reset.h>
11 #include <soc/ramstage.h>
12 #include <fmap.h>
13 #include <smbios.h>
14 #include <string.h>
16 static bool need_global_reset = false;
18 /* Flash Master 1 : HOST/BIOS */
19 #define FLMSTR1 0x80
21 #define FLASH_SIGNATURE_OFFSET 0x10
22 #define FLMSTR_WR_SHIFT_V2 20
23 #define FLASH_SIGNATURE_VAL 0x0FF0A55A
25 #define SI_DESC_SIZE (4 * KiB)
26 #define SI_DESC_REGION "SI_DESC"
28 const char *smbios_mainboard_product_name(void)
30 char processor_name[49];
32 fill_processor_name(processor_name);
34 if (strstr(processor_name, "i3-10110U") != NULL)
35 return "VP4630";
36 else if (strstr(processor_name, "i5-10210U") != NULL)
37 return "VP4650";
38 else if (strstr(processor_name, "i7-10810U") != NULL)
39 return "VP4670";
40 else
41 return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME;
44 static void mainboard_final(void *unused)
46 if (CONFIG(BEEP_ON_BOOT))
47 beep(1500, 100);
50 /* It checks whether host (Flash Master 1) has write access to the Descriptor Region or not */
51 static bool is_descriptor_writeable(uint8_t *desc)
53 /* Check flash has valid signature */
54 if (read32((void *)(desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) {
55 printk(BIOS_ERR, "Flash Descriptor is not valid\n");
56 printk(BIOS_ERR, "Descriptor needs to be fixed to ensure proper operation\n");
57 return false;
60 /* Check host has write access to the Descriptor Region */
61 if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) {
62 printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n");
63 return false;
66 return true;
69 static void configure_descriptor_for_lpc_tpm(void)
71 uint8_t si_desc_buf[SI_DESC_SIZE];
72 struct region_device desc_rdev;
74 if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) {
75 printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION);
76 return;
79 if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) {
80 printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n");
81 return;
84 if (!is_descriptor_writeable(si_desc_buf))
85 return;
87 /* Disable SPI TPM if necessary */
88 if ((si_desc_buf[0x1f0] & 0xfe) == si_desc_buf[0x1f0]) {
89 printk(BIOS_DEBUG, "Update of Descriptor is not required!\n");
90 return;
93 si_desc_buf[0x1f0] &= 0xfe;
95 if (rdev_eraseat(&desc_rdev, 0, SI_DESC_SIZE) != SI_DESC_SIZE) {
96 printk(BIOS_ERR, "Failed to erase Descriptor Region area\n");
97 return;
100 if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) {
101 printk(BIOS_ERR, "Failed to update Descriptor Region\n");
102 return;
105 printk(BIOS_DEBUG, "Update of Descriptor successful\n");
106 need_global_reset = true;
109 void mainboard_silicon_init_params(FSPS_UPD *supd)
111 /* Call it right before Silicon Init, so that we avoid EOP */
112 configure_descriptor_for_lpc_tpm();
113 cse_enable_ptt(false);
115 * We wait with global reset after descriptor update until PTT state change to avoid
116 * double global reset. In case PTT was already disabled or cse_enable_ptt will fail
117 * for some reason, but descriptor has been updated we need to do global reset here,
118 * otherwise cse_enable_ptt will do the global reset and the branch below won't be
119 * reached.
121 if (need_global_reset)
122 do_global_reset();
125 struct chip_operations mainboard_ops = {
126 .final = mainboard_final,