src/mainboard/system76/rpl/variants/addw3/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <mainboard/gpio.h>
   4 #include <soc/gpio.h>
   5
   6 static const struct pad_config gpio_table[] = {
   7         /* ------- GPIO Group GPD ------- */
   8         PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
   9         PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
  10         PAD_CFG_NF(GPD2, NONE, PWROK, NF1), // LAN_WAKEUP#
  11         PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
  12         PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
  13         PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
  14         PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
  15         PAD_CFG_GPO(GPD7, 0, PWROK), // GPD_7
  16         PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK
  17         PAD_CFG_NF(GPD9, NONE, PWROK, NF1), // SLP_WLAN#
  18         PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
  19         PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
  20         _PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000), // TP_GPD12
  21
  22         /* ------- GPIO Group GPP_A ------- */
  23         PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
  24         PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
  25         PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
  26         PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
  27         PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
  28         PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
  29         PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET#
  30         PAD_CFG_NF(GPP_A7, UP_20K, DEEP, NF1),
  31         PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1),
  32         PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1),
  33         PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0
  34         PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
  35         PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
  36         PAD_CFG_NF(GPP_A13, UP_20K, DEEP, NF1),
  37         PAD_NC(GPP_A14, NONE),
  38
  39         /* ------- GPIO Group GPP_B ------- */
  40         _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000), // TPM_PIRQ#
  41         PAD_NC(GPP_B1, NONE), // 50k pull-upp to 3.3VA
  42         PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE#
  43         PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN
  44         PAD_NC(GPP_B4, NONE),
  45         PAD_NC(GPP_B5, NONE), // Unpopulated pull-up and pull-down
  46         PAD_NC(GPP_B6, NONE),
  47         PAD_NC(GPP_B7, NONE),
  48         PAD_NC(GPP_B8, NONE),
  49         PAD_NC(GPP_B9, NONE),
  50         PAD_NC(GPP_B10, NONE),
  51         PAD_NC(GPP_B11, NONE), // Unpopulated jumper resistor to LAN_DISABLE#
  52         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
  53         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
  54         PAD_CFG_GPO(GPP_B14, 0, DEEP), // GPP_B14_SPKR
  55         PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW_PCH
  56         PAD_NC(GPP_B16, NONE),
  57         PAD_NC(GPP_B17, NONE),
  58         PAD_CFG_NF(GPP_B18, NONE, RSMRST, NF1), // PCH_PMCALERT#
  59         PAD_CFG_GPO(GPP_B19, 1, DEEP), // PCH_WLAN_EN
  60         PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
  61         _PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000), // GPP_B21_TBT_WAKE#
  62         PAD_CFG_GPO(GPP_B22, 1, DEEP), // LAN_PLT_RST#
  63         PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23
  64
  65         /* ------- GPIO Group GPP_C ------- */
  66         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
  67         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
  68         PAD_CFG_GPO(GPP_C2, 0, DEEP), // GPP_C2
  69         PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // I2C2_SDA
  70         PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // I2C2_SCL
  71         PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C5
  72         PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), // I2C3_SDA
  73         PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), // I2C3_SCL
  74         PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
  75         PAD_NC(GPP_C9, NONE),
  76         PAD_CFG_GPO(GPP_C10, 1, DEEP), // M2_SSD1_PWR_EN
  77         PAD_CFG_GPO(GPP_C11, 1, DEEP), // M2_SSD2_PWR_EN
  78         PAD_NC(GPP_C12, NONE),
  79         PAD_NC(GPP_C13, NONE),
  80         PAD_NC(GPP_C14, NONE),
  81         PAD_NC(GPP_C15, NONE),
  82         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C0_SDA_TP
  83         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C0_SCL_TP
  84         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA
  85         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL
  86         // GPP_C20 (UART2_RXD) configured in bootblock
  87         // GPP_C21 (UART2_TXD) configured in bootblock
  88         PAD_NC(GPP_C22, NONE),
  89         PAD_NC(GPP_C23, NONE),
  90
  91         /* ------- GPIO Group GPP_D ------- */
  92         PAD_NC(GPP_D0, NONE),
  93         PAD_NC(GPP_D1, NONE),
  94         PAD_NC(GPP_D2, NONE),
  95         PAD_NC(GPP_D3, NONE), // GFX_DETECT_STRAP
  96         PAD_NC(GPP_D4, NONE), // SML1_CLK
  97         PAD_CFG_GPO(GPP_D5, 1, DEEP), // CNVI_RF_RST#
  98         // GPP_D6 (XTAL_CLKREQ) configured by FSP
  99         PAD_NC(GPP_D7, NONE), // BT_PCMIN
 100         PAD_NC(GPP_D8, NONE), // BT_PCMCLK
 101         PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1), // SML0_CLK
 102         PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1), // SML0_DATA
 103         PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
 104         PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
 105         PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
 106         PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
 107         PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1), // SML1_DATA
 108         PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
 109         PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
 110         PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
 111         PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
 112         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 113         PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 114         PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
 115         PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 116
 117         /* ------- GPIO Group GPP_E ------- */
 118         PAD_NC(GPP_E0, NONE),
 119         PAD_NC(GPP_E1, NONE),
 120         PAD_NC(GPP_E2, NONE), // SWI#
 121         _PAD_CFG_STRUCT(GPP_E3, 0x42840101, 0x0000), // SMI#
 122         PAD_NC(GPP_E4, NONE),
 123         PAD_NC(GPP_E5, NONE),
 124         PAD_NC(GPP_E6, NONE),
 125         PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN#
 126         PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
 127         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC#0
 128         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), // USB_OC#1
 129         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), // USB_OC#2
 130         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), // USB_OC#3
 131         PAD_NC(GPP_E13, NONE),
 132         PAD_NC(GPP_E14, NONE),
 133         PAD_CFG_GPO(GPP_E15, 0, DEEP), // ROM_I2C_EN
 134         PAD_NC(GPP_E16, NONE),
 135         PAD_CFG_GPI(GPP_E17, DN_20K, DEEP), // SB_KBCRST#
 136         PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON
 137         PAD_NC(GPP_E19, NONE),
 138         PAD_NC(GPP_E20, NONE),
 139         PAD_NC(GPP_E21, NONE),
 140
 141         /* ------- GPIO Group GPP_F ------- */
 142         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2), // SATAGP3
 143         PAD_NC(GPP_F1, NONE),
 144         PAD_CFG_GPO(GPP_F2, 1, PLTRST), // GPP_F2_TBT_RST#
 145         PAD_CFG_GPO(GPP_F3, 1, PLTRST), // M2_SSD2_RST#
 146         PAD_CFG_GPO(GPP_F4, 1, PLTRST), // M2_SSD1_RST#
 147         PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SATA_DEVSLP3
 148         PAD_NC(GPP_F6, NONE),
 149         PAD_CFG_GPI(GPP_F7, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
 150         PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GC6_FB_EN_PCH
 151         // GPP_F9 (DGPU_PWR_EN) configured in bootblock
 152         PAD_NC(GPP_F10, NONE), // GPP_F10
 153         PAD_NC(GPP_F11, NONE),
 154         PAD_NC(GPP_F12, NONE),
 155         PAD_NC(GPP_F13, NONE),
 156         PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), // Unpopulated jumper resistor to DGPU_PWR_EN
 157         PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC#
 158         PAD_NC(GPP_F16, NONE), // Test point T95
 159         PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
 160         PAD_CFG_GPO(GPP_F18, 0, PLTRST), // CCD_FW_WP#
 161         PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
 162         PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
 163         PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
 164         PAD_NC(GPP_F22, NONE),
 165         PAD_NC(GPP_F23, NONE),
 166
 167         /* ------- GPIO Group GPP_G ------- */
 168         PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
 169         PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
 170         PAD_CFG_NF(GPP_G2, DN_20K, DEEP, NF1), // Unpopulated 20k pull-down
 171         PAD_CFG_GPI(GPP_G3, NONE, DEEP), // BOARD_ID3
 172         PAD_CFG_GPI(GPP_G4, NONE, DEEP), // BOARD_ID4
 173         PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), // SLP_DRAM#
 174         PAD_CFG_GPI(GPP_G6, NONE, DEEP), // BOARD_ID5
 175         PAD_CFG_GPI(GPP_G7, NONE, DEEP), // MUX_CTRL_BIOS
 176
 177         /* ------- GPIO Group GPP_H ------- */
 178         PAD_NC(GPP_H0, NONE), // GPP_H0
 179         PAD_CFG_GPI(GPP_H1, NONE, DEEP), // WLAN_WAKE#
 180         PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // SSD2_CLKREQ#
 181         PAD_NC(GPP_H3, NONE),
 182         // GPP_H4 (SSD1_CLKREQ#) configured by FSP
 183         // GPP_H5 (WLAN_CLKREQ#) configured by FSP
 184         // GPP_H6 (CARD_CLKREQ#) configured by FSP
 185         // GPP_H7 (LAN_CLKREQ#) configured by FSP
 186         // GPP_H8 (PEG_CLKREQ#) configured by FSP
 187         // GPP_H9 (TBT_CLKREQ#) configured by FSP
 188         PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1), // GPP_H10_SML2CLK
 189         PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1), // GPP_H11_SML2DATA
 190         PAD_CFG_GPO(GPP_H12, 0, DEEP), // GPP_H12
 191         PAD_CFG_NF(GPP_H13, NONE, PLTRST, NF1), // GPP_H13_SML3CLK
 192         PAD_CFG_NF(GPP_H14, NONE, PLTRST, NF1), // GPP_H14_SML3DATA
 193         PAD_CFG_NF(GPP_H15, NONE, PLTRST, NF1), // GPP_H_15_SML3ALERT#
 194         PAD_CFG_NF(GPP_H16, NONE, PLTRST, NF1), // GPP_H16_SML4CLK
 195         PAD_CFG_GPO(GPP_H17, 1, PLTRST), // M2_WLAN_RST#
 196         PAD_CFG_GPO(GPP_H18, 0, DEEP), // GPP_H18
 197         PAD_NC(GPP_H19, NONE),
 198         PAD_NC(GPP_H20, NONE),
 199         PAD_CFG_GPO(GPP_H21, 0, DEEP), // TBT_MRESET_PCH
 200         PAD_CFG_GPO(GPP_H22, 0, DEEP), // CARD_RTD3_RST#
 201         PAD_NC(GPP_H23, NONE),
 202
 203         /* ------- GPIO Group GPP_I ------- */
 204         PAD_CFG_GPI(GPP_I0, NONE, DEEP), // IN2_HPD
 205         PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // DP_B_HPD
 206         _PAD_CFG_STRUCT(GPP_I2, 0x86800100, 0x0000), // GPU_DP_A_HPD
 207         PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // DP_D_HPD
 208         _PAD_CFG_STRUCT(GPP_I4, 0x86800100, 0x0000), // HDMI_HPD
 209         PAD_CFG_GPO(GPP_I5, 1, PLTRST), // GPIO_TBT_RESET
 210         PAD_CFG_GPO(GPP_I6, 0, DEEP),
 211         PAD_NC(GPP_I7, NONE),
 212         PAD_CFG_GPO(GPP_I8, 0, DEEP),
 213         PAD_NC(GPP_I9, NONE),
 214         PAD_NC(GPP_I10, NONE),
 215         PAD_CFG_NF(GPP_I11, NONE, PLTRST, NF1), // USB_OC#4
 216         PAD_CFG_NF(GPP_I12, NONE, PLTRST, NF1), // USB_OC#5
 217         PAD_CFG_NF(GPP_I13, NONE, PLTRST, NF1), // EDP_MUX_I2C5_SDA
 218         PAD_CFG_NF(GPP_I14, NONE, PLTRST, NF1), // EDP_MUX_I2C5_SCL
 219         PAD_NC(GPP_I15, NONE),
 220         PAD_NC(GPP_I16, NONE),
 221         PAD_NC(GPP_I17, NONE),
 222         PAD_CFG_GPO(GPP_I18, 0, DEEP), // GPP_I18
 223         PAD_NC(GPP_I19, NONE),
 224         PAD_NC(GPP_I20, NONE),
 225         PAD_NC(GPP_I21, NONE),
 226         PAD_CFG_GPO(GPP_I22, 0, DEEP), // GPP_I22
 227
 228         /* ------- GPIO Group GPP_J ------- */
 229         PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
 230         PAD_CFG_NF(GPP_J1, NONE, PLTRST, NF1), // CPU_C10_GATE#_EC
 231         PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT
 232         PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
 233         PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT
 234         PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
 235         PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
 236         PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
 237         PAD_NC(GPP_J8, NONE), // GPP_J8
 238         PAD_NC(GPP_J9, NONE), // Test point T93
 239         PAD_CFG_NF(GPP_J10, DN_20K, DEEP, NF1),
 240         PAD_CFG_NF(GPP_J11, DN_20K, DEEP, NF1),
 241
 242         /* ------- GPIO Group GPP_K ------- */
 243         _PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000), // TBCIO_PLUG_EVENT#
 244         PAD_NC(GPP_K1, NONE),
 245         PAD_NC(GPP_K2, NONE),
 246         PAD_CFG_GPO(GPP_K3, 1, PLTRST), // TBT_RTD3_PWR_EN_R
 247         PAD_CFG_GPO(GPP_K4, 0, RSMRST), // TBT_FORCE_PWR_R
 248         PAD_NC(GPP_K5, NONE),
 249         PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2), // Not in schematic
 250         PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2), // Not in schematic
 251         PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0
 252         PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1
 253         PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2), // Not in schematic
 254         PAD_NC(GPP_K11, NONE),
 255
 256         /* ------- GPIO Group GPP_R ------- */
 257         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
 258         PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
 259         PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
 260         PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
 261         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
 262         PAD_NC(GPP_R5, NONE),
 263         PAD_NC(GPP_R6, NONE),
 264         PAD_NC(GPP_R7, NONE),
 265         PAD_CFG_GPI(GPP_R8, NONE, PLTRST), // DGPU_PWRGD_R
 266         PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // PCH_EDP_HPD
 267         PAD_NC(GPP_R10, NONE),
 268         PAD_NC(GPP_R11, NONE),
 269         PAD_NC(GPP_R12, NONE),
 270         PAD_NC(GPP_R13, NONE),
 271         PAD_NC(GPP_R14, NONE),
 272         PAD_NC(GPP_R15, NONE),
 273         // GPP_R16 (DGPU_RST#_PCH) configured in bootblock
 274         PAD_NC(GPP_R17, NONE),
 275         PAD_NC(GPP_R18, NONE),
 276         PAD_NC(GPP_R19, NONE), // SCI#
 277         PAD_NC(GPP_R20, NONE),
 278         PAD_CFG_GPO(GPP_R21, 0, DEEP),
 279
 280         /* ------- GPIO Group GPP_S ------- */
 281         PAD_NC(GPP_S0, NONE), // Test point T89
 282         PAD_NC(GPP_S1, NONE),
 283         PAD_NC(GPP_S2, NONE), // GPP_S2
 284         PAD_NC(GPP_S3, NONE),
 285         PAD_NC(GPP_S4, NONE),
 286         PAD_NC(GPP_S5, NONE),
 287         PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), // Unpopulated 33 ohm resistor to PCH_DMIC_CLK
 288         PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), // Unpopulated 33 ohm resistor to PCH_DMIC_DATA
 289 };
 290
 291 void mainboard_configure_gpios(void)
 292 {
 293         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 294 }