mb/ocp/tiogapass: Fix GPIOs
[coreboot2.git] / src / mainboard / system76 / rpl / variants / gaze18 / overridetree.cb
blob636d57cadde532e80e125fa2a17ac84777c5d98e
1 # SPDX-License-Identifier: GPL-2.0-only
3 chip soc/intel/alderlake
4 device domain 0 on
5 subsystemid 0x1558 0x5630 inherit
7 device ref xhci on
8 register "usb2_ports" = "{
9 [2] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 (USB 3.1 Gen2) */
10 [4] = USB2_PORT_MID(OC_SKIP), /* Type-A (USB 3.1 Gen2) */
11 [5] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC2 (USB 3.1 Gen2) */
12 [6] = USB2_PORT_MID(OC_SKIP), /* Finger */
13 [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
14 [8] = USB2_PORT_MID(OC_SKIP), /* Type-A */
15 [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
17 register "usb3_ports" = "{
18 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A (USB 3.1 Gen2) */
19 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC2 */
20 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 */
21 [3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 */
23 end
25 device ref i2c0 on
26 # Touchpad I2C bus
27 register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
28 chip drivers/i2c/hid
29 register "generic.hid" = ""ELAN0412""
30 register "generic.desc" = ""ELAN Touchpad""
31 register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
32 register "generic.detect" = "1"
33 register "hid_desc_reg_offset" = "0x01"
34 device i2c 15 on end
35 end
36 chip drivers/i2c/hid
37 register "generic.hid" = ""FTCS1000""
38 register "generic.desc" = ""FocalTech Touchpad""
39 register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
40 register "generic.detect" = "1"
41 register "hid_desc_reg_offset" = "0x01"
42 device i2c 38 on end
43 end
44 end
46 device ref pcie5_0 on
47 # CPU PCIe RP#2 x8, Clock 3 (GPU)
48 register "cpu_pcie_rp[CPU_RP(2)]" = "{
49 .clk_src = 3,
50 .clk_req = 3,
51 .flags = PCIE_RP_LTR | PCIE_RP_AER,
53 end
54 device ref pcie4_0 on
55 # CPU RP#1 x4, Clock 0 (SSD0)
56 register "cpu_pcie_rp[CPU_RP(1)]" = "{
57 .clk_src = 0,
58 .clk_req = 0,
59 .flags = PCIE_RP_LTR | PCIE_RP_AER,
61 end
62 device ref pcie_rp5 on
63 # PCH RP#5 x4, Clock 1 (SSD1)
64 register "pch_pcie_rp[PCH_RP(5)]" = "{
65 .clk_src = 1,
66 .clk_req = 1,
67 .flags = PCIE_RP_LTR | PCIE_RP_AER,
68 .pcie_rp_detect_timeout_ms = 50,
70 end
71 device ref pcie_rp9 on
72 # PCH RP#9 x1, Clock 6 (GLAN)
73 register "pch_pcie_rp[PCH_RP(9)]" = "{
74 .clk_src = 6,
75 .clk_req = 6,
76 .flags = PCIE_RP_LTR | PCIE_RP_AER,
78 device pci 00.0 on end
79 end
80 device ref pcie_rp10 on
81 # PCH RP#10 x1, Clock 2 (WLAN)
82 register "pch_pcie_rp[PCH_RP(10)]" = "{
83 .clk_src = 2,
84 .clk_req = 2,
85 .flags = PCIE_RP_LTR | PCIE_RP_AER,
87 end
88 device ref pcie_rp11 on
89 # PCH RP#11 x1, Clock 5 (CARD)
90 register "pch_pcie_rp[PCH_RP(11)]" = "{
91 .clk_src = 5,
92 .clk_req = 5,
93 .flags = PCIE_RP_LTR | PCIE_RP_AER,
95 end
96 end
97 end