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soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git]
/
util
/
exynos
/
description.md
blob
c039c913f3f5d40da3d0ca2b85fa8ec62cec4f73
1
Computes and fills Exynos ROM checksum (for BL1 or BL2). `Python3`
