soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / util / exynos / fixed_cksum.py
blob0ae7e4f6f8c9cea982927f43937447c8448ac1be
1 #!/usr/bin/env python3
3 # SPDX-License-Identifier: BSD-3-Clause
5 """
6 This utility computes and fills Exynos ROM checksum (for BL1 or BL2).
7 (Algorithm from U-Boot: tools/mkexynosspl.c)
9 Input: IN OUT DATA_SIZE
11 Output:
13 IN padded out to DATA_SIZE, checksum at the end, written to OUT.
14 """
16 import struct
17 import sys
19 def main(argv):
20 if len(argv) != 4:
21 exit('usage: %s IN OUT DATA_SIZE' % argv[0])
23 in_name, out_name = argv[1:3]
24 size = int(argv[3], 0)
25 checksum_format = "<I"
26 with open(in_name, "rb") as in_file, open(out_name, "wb") as out_file:
27 data = in_file.read()
28 checksum_size = struct.calcsize(checksum_format)
29 data_size = size - checksum_size
30 assert len(data) <= data_size
31 checksum = struct.pack(checksum_format, sum(data))
32 out_file.write(data + bytearray(data_size - len(data)) + checksum)
35 if __name__ == '__main__':
36 main(sys.argv)