soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / util / exynos / variable_cksum.py
blob4321f8e53c173dd059eb947841dbfafe01c554bf
1 #!/usr/bin/env python3
3 # SPDX-License-Identifier: BSD-3-Clause
5 """
6 This utility computes and fills Exynos ROM checksum (for BL1 or BL2).
7 (Algorithm from U-Boot: tools/mkexynosspl.c)
9 Input: IN OUT
11 Output:
13 Checksum header added to IN and written to OUT.
14 Header: uint32_t size, checksum, reserved[2].
15 """
17 import struct
18 import sys
20 def main(argv):
21 if len(argv) != 3:
22 exit('usage: %s IN OUT' % argv[0])
24 in_name, out_name = argv[1:3]
25 header_format = "<IIII"
26 with open(in_name, "rb") as in_file, open(out_name, "wb") as out_file:
27 data = in_file.read()
28 header = struct.pack(header_format,
29 struct.calcsize(header_format) + len(data),
30 sum(data),
31 0, 0)
32 out_file.write(header + data)
35 if __name__ == '__main__':
36 main(sys.argv)