util/superiotool/superiotool.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef SUPERIOTOOL_H
   4 #define SUPERIOTOOL_H
   5
   6 #include <stdio.h>
   7 #include <stdlib.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <getopt.h>
  11 #include <commonlib/bsd/helpers.h>
  12 #if defined(__linux__)
  13 #include <sys/io.h>
  14 #endif
  15 #if (defined(__MACH__) && defined(__APPLE__))
  16 /* DirectHW is available here: https://www.coreboot.org/DirectHW */
  17 #include <DirectHW/DirectHW.h>
  18 #endif
  19
  20 #ifdef PCI_SUPPORT
  21 # ifdef __NetBSD__
  22 #include <pciutils/pci.h>
  23 # else
  24 #include <pci/pci.h>
  25 # endif
  26 #endif
  27
  28 #include <sys/types.h>
  29 #include <stdint.h>
  30
  31 #if defined(__FreeBSD__)
  32 #include <sys/types.h>
  33 #include <machine/cpufunc.h>
  34 #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0)
  35 #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0)
  36 #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0)
  37 #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); })
  38 #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); })
  39 #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); })
  40 #else
  41 #define OUTB outb
  42 #define OUTW outw
  43 #define OUTL outl
  44 #define INB  inb
  45 #define INW  inw
  46 #define INL  inl
  47 #endif
  48
  49 #if defined(__NetBSD__) && (defined(__i386__) || defined(__x86_64__))
  50 #include <sys/types.h>
  51 #include <machine/sysarch.h>
  52 #if defined(__i386__)
  53 #define iopl i386_iopl
  54 #elif defined(__x86_64__)
  55 #define iopl x86_64_iopl
  56 #endif
  57
  58 static __inline__ void
  59 outb(uint8_t value, uint16_t port)
  60 {
  61         __asm__ __volatile__ ("outb %b0,%w1": :"a" (value), "Nd" (port));
  62 }
  63
  64 static __inline__ void
  65 outw(uint16_t value, uint16_t port)
  66 {
  67         __asm__ __volatile__ ("outw %w0,%w1": :"a" (value), "Nd" (port));
  68 }
  69
  70 static __inline__ void
  71 outl(uint32_t value, uint16_t port)
  72 {
  73         __asm__ __volatile__ ("outl %0,%w1": :"a" (value), "Nd" (port));
  74 }
  75
  76 static __inline__ uint8_t inb(uint16_t port)
  77 {
  78         uint8_t value;
  79         __asm__ __volatile__ ("inb %w1,%0":"=a" (value):"Nd" (port));
  80         return value;
  81 }
  82
  83 static __inline__ uint16_t inw(uint16_t port)
  84 {
  85         uint16_t value;
  86         __asm__ __volatile__ ("inw %w1,%0":"=a" (value):"Nd" (port));
  87         return value;
  88 }
  89
  90 static __inline__ uint32_t inl(uint16_t port)
  91 {
  92         uint32_t value;
  93         __asm__ __volatile__ ("inl %1,%0":"=a" (value):"Nd" (port));
  94         return value;
  95 }
  96 #endif
  97
  98 #define USAGE "Usage: superiotool [-d] [-e] [-a] [-l] [-V] [-v] [-h]\n\n\
  99   -d | --dump            Dump Super I/O register contents\n\
 100   -e | --extra-dump      Dump secondary registers too (e.g. EC registers)\n\
 101   -a | --alternate-dump  Use alternative dump format, more suitable for diff\n\
 102   -l | --list-supported  Show the list of supported Super I/O chips\n\
 103   -V | --verbose         Verbose mode\n\
 104   -v | --version         Show the superiotool version\n\
 105   -h | --help            Show a short help text\n\n"
 106
 107 #define USAGE_INFO "\
 108 Per default (no options) superiotool will just probe for a Super I/O\n\
 109 and print its vendor, name, ID, revision, and config port.\n"
 110
 111 #define NOTFOUND "  Failed. Returned data: "
 112
 113 #define EOT             -1              /* End Of Table */
 114 #define NOLDN           -2              /* NO LDN needed */
 115 #define NANA            -3              /* Not Available:
 116                                            Used for registers having externally controlled
 117                                            values that can change during runtime like
 118                                            GPIO input value registers. */
 119 #define RSVD            -4              /* Reserved */
 120 #define MISC            -5              /* Needs special comment in output:
 121                                            Used for registers depending on external pin straps
 122                                            configuring static, but board-specific settings like
 123                                            SIO base address or AMD/Intel power seqencing type. */
 124 #define MAXLDN          0x14            /* Biggest LDN */
 125 #define LDNSIZE         (MAXLDN + 3)    /* Biggest LDN + 0 + NOLDN + EOT */
 126 #define MAXNUMIDX       170             /* Maximum number of indices */
 127 #define IDXSIZE         (MAXNUMIDX + 1)
 128 #define MAXNUMPORTS     (6 + 1)         /* Maximum number of Super I/O ports */
 129
 130 /* Select registers for various components. */
 131 #define LDN_SEL         0x07            /* LDN select register */
 132 #define WINBOND_HWM_SEL 0x4e            /* Hardware monitor bank select */
 133
 134 /* Command line parameters. */
 135 extern int dump, verbose, extra_dump;
 136
 137 extern int chip_found;
 138
 139 /* Extra selector structure (see fintek.c) */
 140 struct extra_selector {
 141         const char *name;
 142         uint8_t idx;
 143         uint8_t mask;
 144         uint8_t val;
 145 };
 146
 147 struct superio_registers {
 148         int32_t superio_id;             /* Signed, as we need EOT. */
 149         const char *name;               /* Super I/O name */
 150         struct {
 151                 int8_t ldn;
 152                 const char *name;       /* LDN name */
 153                 int16_t idx[IDXSIZE];
 154                 int16_t def[IDXSIZE];
 155                 struct extra_selector esel;
 156         } ldn[LDNSIZE];
 157 };
 158
 159 /* pci.c */
 160 #ifdef PCI_SUPPORT
 161 extern struct pci_access *pacc;
 162 struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
 163 #endif
 164
 165 /* superiotool.c */
 166 uint8_t regval(uint16_t port, uint8_t reg);
 167 void regwrite(uint16_t port, uint8_t reg, uint8_t val);
 168 void enter_conf_mode_winbond_fintek_ite_8787(uint16_t port);
 169 void exit_conf_mode_winbond_fintek_ite_8787(uint16_t port);
 170 void enter_conf_mode_fintek_7777(uint16_t port);
 171 void exit_conf_mode_fintek_7777(uint16_t port);
 172 int superio_unknown(const struct superio_registers reg_table[], uint16_t id);
 173 const char *get_superio_name(const struct superio_registers reg_table[],
 174                              uint16_t id);
 175 void dump_superio(const char *name, const struct superio_registers reg_table[],
 176                   uint16_t port, uint16_t id, uint8_t ldn_sel);
 177 void dump_io(uint16_t iobase, uint16_t length);
 178 void dump_data(uint16_t iobase, int bank);
 179 void probing_for(const char *vendor, const char *info, uint16_t port);
 180 void print_vendor_chips(const char *vendor,
 181                         const struct superio_registers reg_table[]);
 182
 183 /* ali.c */
 184 void probe_idregs_ali(uint16_t port);
 185 void print_ali_chips(void);
 186
 187 /* aspeed.c */
 188 void probe_idregs_aspeed(uint16_t port);
 189 void print_aspeed_chips(void);
 190
 191 /* amd.c */
 192 void probe_idregs_amd(uint16_t port);
 193 void print_amd_chips(void);
 194
 195 /* serverengines.c */
 196 void probe_idregs_serverengines(uint16_t port);
 197 void print_serverengines_chips(void);
 198
 199 /* exar.c */
 200 void probe_idregs_exar(uint16_t port);
 201 void print_exar_chips(void);
 202
 203 /* fintek.c */
 204 void probe_idregs_fintek(uint16_t port);
 205 void probe_idregs_fintek_alternative(uint16_t port);
 206 void print_fintek_chips(void);
 207
 208 /* infineon.c */
 209 void probe_idregs_infineon(uint16_t port);
 210 void print_infineon_chips(void);
 211
 212 /* ite.c */
 213 void probe_idregs_ite(uint16_t port);
 214 void print_ite_chips(void);
 215
 216 /* nsc.c */
 217 void probe_idregs_nsc(uint16_t port);
 218 void print_nsc_chips(void);
 219
 220 /* nuvoton.c */
 221 void probe_idregs_nuvoton(uint16_t port);
 222 void print_nuvoton_chips(void);
 223
 224 /* smsc.c */
 225 void probe_idregs_smsc(uint16_t port);
 226 void print_smsc_chips(void);
 227
 228 /* winbond.c */
 229 void probe_idregs_winbond(uint16_t port);
 230 void print_winbond_chips(void);
 231
 232 /* via.c */
 233 #ifdef PCI_SUPPORT
 234 void probe_idregs_via(uint16_t port);
 235 void print_via_chips(void);
 236 #endif
 237
 238 /** Table of which config ports to probe for each Super I/O family. */
 239 static const struct {
 240         void (*probe_idregs) (uint16_t port);
 241         int ports[MAXNUMPORTS]; /* Signed, as we need EOT. */
 242 } superio_ports_table[] = {
 243         {probe_idregs_ali,      {0x3f0, 0x370, EOT}},
 244         {probe_idregs_aspeed,   {0x2e, 0x4e, EOT}},
 245         {probe_idregs_exar,     {0x2e, 0x4e, EOT}},
 246         {probe_idregs_fintek,   {0x2e, 0x4e, EOT}},
 247         {probe_idregs_fintek_alternative,       {0x2e, 0x4e, EOT}},
 248         /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */
 249         {probe_idregs_ite,      {0x20e, 0x25e, 0x2e, 0x4e, 0x370, 0x6e, EOT}},
 250         {probe_idregs_nsc,      {0x2e, 0x4e, 0x15c, 0x164e, EOT}},
 251         /* I/O pairs on Nuvoton EC chips can be configured by firmware in
 252          * addition to the following hardware strapping options. */
 253         {probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}},
 254         {probe_idregs_smsc,     {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}},
 255         {probe_idregs_winbond,  {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}},
 256 #ifdef PCI_SUPPORT
 257         {probe_idregs_via,      {0x2e, 0x4e, 0x3f0, EOT}},
 258         /* in fact read the BASE from HW */
 259         {probe_idregs_amd,      {0xaa, EOT}},
 260 #endif
 261         {probe_idregs_serverengines,    {0x2e, EOT}},
 262         {probe_idregs_infineon, {0x2e, 0x4e, EOT}},
 263 };
 264
 265 /** Table of functions to print out supported Super I/O chips. */
 266 static const struct {
 267         void (*print_list) (void);
 268 } vendor_print_functions[] = {
 269         {print_ali_chips},
 270         {print_exar_chips},
 271         {print_fintek_chips},
 272         {print_ite_chips},
 273         {print_nsc_chips},
 274         {print_nuvoton_chips},
 275         {print_smsc_chips},
 276         {print_winbond_chips},
 277 #ifdef PCI_SUPPORT
 278         {print_via_chips},
 279         {print_amd_chips},
 280         {print_aspeed_chips},
 281 #endif
 282         {print_serverengines_chips},
 283         {print_infineon_chips},
 284 };
 285
 286 #endif