1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
7 /* Pad configuration in ramstage for glassway */
8 static const struct pad_config override_gpio_table
[] = {
9 /* A8 : WWAN_RF_DISABLE_ODL */
10 PAD_CFG_GPO(GPP_A8
, 1, DEEP
),
11 /* A20 : DDSP_HPD2 ==> NC */
12 PAD_NC_LOCK(GPP_A20
, NONE
, LOCK_CONFIG
),
13 /* D3 : ISH_GP3 ==> NC */
14 PAD_NC_LOCK(GPP_D3
, NONE
, LOCK_CONFIG
),
16 PAD_CFG_GPO(GPP_D6
, 1, DEEP
),
17 /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
18 PAD_CFG_NF(GPP_D7
, NONE
, DEEP
, NF1
),
19 /* D15 : ISH_UART0_RTS# ==> NC */
20 PAD_NC_LOCK(GPP_D15
, NONE
, LOCK_CONFIG
),
21 /* D16 : ISH_UART0_CTS# ==> NC */
22 PAD_NC_LOCK(GPP_D16
, NONE
, LOCK_CONFIG
),
23 /* D17 : PCIE SLOT1 WAKE N */
24 PAD_NC_LOCK(GPP_D17
, NONE
, LOCK_CONFIG
),
26 PAD_CFG_GPI(GPP_E4
, NONE
, DEEP
),
28 PAD_CFG_GPI(GPP_E5
, NONE
, DEEP
),
29 /* E20 : DDP2_CTRLCLK ==> NC */
30 PAD_NC_LOCK(GPP_E20
, NONE
, LOCK_CONFIG
),
31 /* E21 : DDP2_CTRLDATA ==> NC */
32 PAD_NC_LOCK(GPP_E21
, NONE
, LOCK_CONFIG
),
33 /* F12 : WWAN_RST_L */
34 PAD_CFG_GPO_LOCK(GPP_F12
, 1, LOCK_CONFIG
),
35 /* H19 : SOC_I2C_SUB_INT_ODL */
36 PAD_CFG_GPI_APIC(GPP_H19
, NONE
, PLTRST
, LEVEL
, NONE
),
37 /* H22 : IMGCLKOUT3 ==> NC */
38 PAD_NC_LOCK(GPP_H22
, NONE
, LOCK_CONFIG
),
39 /* H23 : WWAN_SAR_DETECT_ODL */
40 PAD_CFG_GPO(GPP_H23
, 1, DEEP
),
41 /* R4 : I2S2_SCLK ==> DMIC_UCAM_CLK_R */
42 PAD_CFG_NF(GPP_R4
, NONE
, DEEP
, NF3
),
43 /* R5 : I2S2_SFRM ==> DMIC_UCAM_DATA_R */
44 PAD_CFG_NF(GPP_R5
, NONE
, DEEP
, NF3
),
45 /* R6 : DMIC_CLK_A_1A ==> NC */
46 PAD_NC_LOCK(GPP_R6
, NONE
, LOCK_CONFIG
),
48 /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
50 PAD_CFG_NF(GPP_VGPIO_30
, NONE
, DEEP
, NF3
),
52 PAD_CFG_NF(GPP_VGPIO_31
, NONE
, DEEP
, NF3
),
54 PAD_CFG_NF(GPP_VGPIO_32
, NONE
, DEEP
, NF3
),
56 PAD_CFG_NF(GPP_VGPIO_33
, NONE
, DEEP
, NF3
),
58 PAD_CFG_NF(GPP_VGPIO_34
, NONE
, DEEP
, NF1
),
60 PAD_CFG_NF(GPP_VGPIO_35
, NONE
, DEEP
, NF1
),
62 PAD_CFG_NF(GPP_VGPIO_36
, NONE
, DEEP
, NF1
),
64 PAD_CFG_NF(GPP_VGPIO_37
, NONE
, DEEP
, NF1
),
67 /* Early pad configuration in bootblock for glassway */
68 static const struct pad_config early_gpio_table
[] = {
69 /* F12 : GSXDOUT ==> WWAN_RST_L */
70 PAD_CFG_GPO(GPP_F12
, 0, DEEP
),
71 /* H12 : UART0_RTS# ==> SD_PERST_L */
72 PAD_CFG_GPO(GPP_H12
, 0, DEEP
),
73 /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
74 PAD_CFG_GPI_APIC(GPP_A13
, NONE
, PLTRST
, LEVEL
, INVERT
),
75 /* D6 : SRCCLKREQ1# ==> WWAN_EN */
76 PAD_CFG_GPO(GPP_D6
, 1, DEEP
),
77 /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
78 PAD_CFG_GPI_GPIO_DRIVER(GPP_E12
, NONE
, DEEP
),
79 /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
80 PAD_CFG_GPI(GPP_F18
, NONE
, DEEP
),
81 /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
82 PAD_CFG_NF(GPP_H4
, NONE
, DEEP
, NF1
),
83 /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
84 PAD_CFG_NF(GPP_H5
, NONE
, DEEP
, NF1
),
85 /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
86 PAD_CFG_NF(GPP_H10
, NONE
, DEEP
, NF2
),
87 /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
88 PAD_CFG_NF(GPP_H11
, NONE
, DEEP
, NF2
),
89 /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
90 PAD_CFG_GPO(GPP_H13
, 1, DEEP
),
93 static const struct pad_config romstage_gpio_table
[] = {
94 /* Enable touchscreen, hold in reset */
95 /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
96 PAD_CFG_GPO(GPP_C0
, 1, DEEP
),
97 /* C1 : SMBDATA ==> USI_RST_L */
98 PAD_CFG_GPO(GPP_C1
, 0, DEEP
),
99 /* C6 : SML1CLK ==> TCHSCR_REPORT_EN */
100 PAD_CFG_GPO(GPP_C6
, 0, DEEP
),
101 /* H12 : UART0_RTS# ==> SD_PERST_L */
102 PAD_CFG_GPO(GPP_H12
, 1, DEEP
),
105 const struct pad_config
*variant_gpio_override_table(size_t *num
)
107 *num
= ARRAY_SIZE(override_gpio_table
);
108 return override_gpio_table
;
111 const struct pad_config
*variant_early_gpio_table(size_t *num
)
113 *num
= ARRAY_SIZE(early_gpio_table
);
114 return early_gpio_table
;
118 const struct pad_config
*variant_romstage_gpio_table(size_t *num
)
120 *num
= ARRAY_SIZE(romstage_gpio_table
);
121 return romstage_gpio_table
;