src/mainboard/google/brya/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpigen.h>
   4 #include <baseboard/gpio.h>
   5 #include <baseboard/variants.h>
   6 #include <device/device.h>
   7 #include <drivers/tpm/cr50.h>
   8 #include <drivers/wwan/fm/chip.h>
   9 #include <ec/ec.h>
  10 #include <fw_config.h>
  11 #include <security/tpm/tss.h>
  12 #include <soc/gpio.h>
  13 #include <soc/ramstage.h>
  14 #include <stdio.h>
  15
  16 WEAK_DEV_PTR(rp6_wwan);
  17 WEAK_DEV_PTR(dgpu);
  18
  19 static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
  20 {
  21         struct smbios_type11 *t;
  22         char buffer[64];
  23
  24         t = (struct smbios_type11 *)arg;
  25
  26         snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name);
  27         t->count = smbios_add_string(t->eos, buffer);
  28 }
  29
  30 static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t)
  31 {
  32         fw_config_for_each_found(add_fw_config_oem_string, t);
  33 }
  34
  35 void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config)
  36 {
  37         tpm_result_t rc;
  38
  39         rc = tlcl_lib_init();
  40         if (rc != TPM_SUCCESS) {
  41                 printk(BIOS_ERR, "tlcl_lib_init() failed: %#x\n", rc);
  42                 return;
  43         }
  44
  45         if (cr50_is_long_interrupt_pulse_enabled()) {
  46                 printk(BIOS_INFO, "Enabling GPIO PM b/c CR50 has long IRQ pulse support\n");
  47                 config->gpio_override_pm = 0;
  48         } else {
  49                 printk(BIOS_INFO, "Disabling GPIO PM b/c CR50 does not have long IRQ pulse "
  50                        "support\n");
  51                 config->gpio_override_pm = 1;
  52                 config->gpio_pm[COMM_0] = 0;
  53                 config->gpio_pm[COMM_1] = 0;
  54                 config->gpio_pm[COMM_2] = 0;
  55                 config->gpio_pm[COMM_3] = 0;
  56                 config->gpio_pm[COMM_4] = 0;
  57                 config->gpio_pm[COMM_5] = 0;
  58         }
  59
  60         variant_update_soc_chip_config(config);
  61 }
  62
  63 void __weak variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
  64 {
  65         /* default implementation does nothing */
  66 }
  67
  68 void __weak variant_init(void)
  69 {
  70         /* default implementation does nothing */
  71 }
  72
  73 void __weak fw_config_gpio_padbased_override(struct pad_config *padbased_table)
  74 {
  75         /* default implementation does nothing */
  76 }
  77
  78 void __weak variant_configure_pads(void)
  79 {
  80         const struct pad_config *base_pads;
  81         const struct pad_config *override_pads;
  82         size_t base_num, override_num;
  83
  84         base_pads = variant_gpio_table(&base_num);
  85         override_pads = variant_gpio_override_table(&override_num);
  86         gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
  87 }
  88
  89 static void mainboard_init(void *chip_info)
  90 {
  91         variant_configure_pads();
  92         variant_init();
  93         variant_devtree_update();
  94 }
  95
  96 void __weak variant_devtree_update(void)
  97 {
  98         /* Override dev tree settings per board */
  99 }
 100
 101 static void mainboard_dev_init(struct device *dev)
 102 {
 103         mainboard_ec_init();
 104 }
 105
 106 static void mainboard_generate_wwan_shutdown(const struct device *dev)
 107 {
 108         const struct drivers_wwan_fm_config *config = config_of(dev);
 109         const struct device *parent = dev->upstream->dev;
 110
 111         if (!config)
 112                 return;
 113         if (config->rtd3dev) {
 114                 acpigen_write_store();
 115                 acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA"));
 116                 acpigen_emit_byte(LOCAL0_OP);
 117                 acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP);
 118                 {
 119                         acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS"));
 120                         acpigen_emit_byte(ARG0_OP);
 121                 }
 122                 acpigen_write_if_end();
 123         }
 124 }
 125
 126 static void mainboard_generate_dgpu_shutdown(const struct device *dev)
 127 {
 128         /* Call `_OFF` from the Power Resource associated with the dGPU's PEG port. */
 129         const struct device *parent = dev->upstream->dev;
 130
 131         if (parent)
 132                 acpigen_emit_namestring(acpi_device_path_join(parent, "PGPR._OFF"));
 133 }
 134
 135 static void mainboard_generate_mpts(void)
 136 {
 137         const struct device *wwan = DEV_PTR(rp6_wwan);
 138         const struct device *dgpu = DEV_PTR(dgpu);
 139
 140         /*
 141          * If HAVE_WWAN_POWER_SEQUENCE is selected, MPTS will be added to the
 142          * DSDT via wwan_power.asl. We can't add MPTS to the SSDT as well,
 143          * since the duplicate definition will result in a kernel error.
 144          *
 145          * This special case can be removed in the future if the power-off
 146          * sequences for all WWAN devices used on brya are moved to the SSDT.
 147          */
 148         if (CONFIG(HAVE_WWAN_POWER_SEQUENCE)) {
 149                 if (wwan || dgpu)
 150                         printk(BIOS_ERR, "Skip adding duplicate MPTS entry to SSDT\n");
 151                 return;
 152         }
 153
 154         acpigen_write_scope("\\_SB");
 155         acpigen_write_method_serialized("MPTS", 1);
 156         if (wwan)
 157                 mainboard_generate_wwan_shutdown(wwan);
 158         if (dgpu)
 159                 mainboard_generate_dgpu_shutdown(dgpu);
 160
 161         acpigen_write_method_end(); /* Method */
 162         acpigen_write_scope_end(); /* Scope */
 163 }
 164
 165 static void mainboard_generate_s0ix_hook(void)
 166 {
 167         acpigen_write_if_lequal_op_int(ARG0_OP, 1);
 168         {
 169                 if (CONFIG(HAVE_SLP_S0_GATE))
 170                         acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE);
 171                 variant_generate_s0ix_hook(S0IX_ENTRY);
 172         }
 173         acpigen_write_else();
 174         {
 175                 if (CONFIG(HAVE_SLP_S0_GATE))
 176                         acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE);
 177                 variant_generate_s0ix_hook(S0IX_EXIT);
 178         }
 179         acpigen_write_if_end();
 180 }
 181
 182 static void mainboard_fill_ssdt(const struct device *dev)
 183 {
 184         mainboard_generate_mpts();
 185
 186         /* for variant to fill additional SSDT */
 187         variant_fill_ssdt(dev);
 188
 189         acpigen_write_scope("\\_SB");
 190         acpigen_write_method_serialized("MS0X", 1);
 191         mainboard_generate_s0ix_hook();
 192         acpigen_write_method_end(); /* Method */
 193         acpigen_write_scope_end(); /* Scope */
 194
 195 }
 196
 197 void __weak variant_fill_ssdt(const struct device *dev)
 198 {
 199         /* Add board-specific SSDT entries */
 200 }
 201
 202 void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
 203 {
 204         /* Add board-specific MS0X entries */
 205         /*
 206            if (s0ix_entry == S0IX_ENTRY) {
 207                 implement variant operations here
 208            }
 209            if (s0ix_entry == S0IX_EXIT) {
 210                 implement variant operations here
 211            }
 212          */
 213 }
 214
 215 static void mainboard_enable(struct device *dev)
 216 {
 217         dev->ops->init = mainboard_dev_init;
 218         dev->ops->get_smbios_strings = mainboard_smbios_strings;
 219         dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 220 }
 221
 222
 223 void __weak variant_finalize(void)
 224 {
 225 }
 226
 227 static void mainboard_final(void *chip_info)
 228 {
 229         variant_finalize();
 230 }
 231
 232 struct chip_operations mainboard_ops = {
 233         .init = mainboard_init,
 234         .enable_dev = mainboard_enable,
 235         .final = mainboard_final,
 236 };