?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / google / brya / variants / anraggar / overridetree.cb
blob9646f29a60804d72716cc9a4db1a3d5fbfca5e95
1 fw_config
2 field WIFI 10 11
3 option UNKNOWN 0
4 option WIFI_6 1
5 option WIFI_6E 2
6 end
7 field CAMERA 12 13
8 option UF_720P_WF 0
9 option UF_1080P 1
10 option UF_720P 2
11 option UF_1080P_WF 3
12 end
13 end
14
15 chip soc/intel/alderlake
16 register "sagv" = "SaGv_Enabled"
17
18 # EMMC Tx CMD Delay
19 # Refer to EDS-Vol2-42.3.7.
20 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
21 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
22 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
23
24 # EMMC TX DATA Delay 1
25 # Refer to EDS-Vol2-42.3.8.
26 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
27 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
28 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
29
30 # EMMC TX DATA Delay 2
31 # Refer to EDS-Vol2-42.3.9.
32 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
33 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
34 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
35 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
36 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
37
38 # EMMC RX CMD/DATA Delay 1
39 # Refer to EDS-Vol2-42.3.10.
40 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
41 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
42 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
43 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
44 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
45
46 # EMMC RX CMD/DATA Delay 2
47 # Refer to EDS-Vol2-42.3.12.
48 # [17:16] stands for Rx Clock before Output Buffer,
49 # 00: Rx clock after output buffer,
50 # 01: Rx clock before output buffer,
51 # 10: Automatic selection based on working mode.
52 # 11: Reserved
53 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
54 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
55 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10051"
56
57 # EMMC Rx Strobe Delay
58 # Refer to EDS-Vol2-42.3.11.
59 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
60 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
61 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
62
63 # SOC Aux orientation override:
64 # This is a bitfield that corresponds to up to 4 TCSS ports.
65 # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
66 # TcssAuxOri = 0100b
67 # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
68 # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
69 # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
70 # motherboard to USBC connector
71 register "tcss_aux_ori" = "4"
72
73 register "typec_aux_bias_pads[0]" = "{
74 .pad_auxp_dc = GPP_E22,
75 .pad_auxn_dc = GPP_E23
76 }"
77
78 # FIVR configurations for anraggar are disabled since the board doesn't have V1p05 and Vnn
79 # bypass rails implemented.
80 register "ext_fivr_settings" = "{
81 .configure_ext_fivr = 0,
82 }"
83
84 # Enable the Cnvi BT Audio Offload
85 register "cnvi_bt_audio_offload" = "1"
86
87 # Intel Common SoC Config
88 #+-------------+------------------------------+
89 #| Field | Value |
90 #+-------------+------------------------------+
91 #| I2C0 | TPM. Early init is |
92 #| | required to set up a BAR |
93 #| | for TPM communication |
94 #| I2C1 | Touchscreen |
95 #| I2C2 | Sub-board(PSensor)/WCAM |
96 #| I2C3 | Audio |
97 #| I2C5 | Trackpad |
98 #+-------------+------------------------------+
99 register "common_soc_config" = "{
100 .i2c[0] = {
101 .early_init = 1,
102 .speed = I2C_SPEED_FAST_PLUS,
103 .speed_config[0] = {
104 .speed = I2C_SPEED_FAST_PLUS,
105 .scl_lcnt = 55,
106 .scl_hcnt = 30,
107 .sda_hold = 7,
108 }
109 },
110 .i2c[1] = {
111 .speed = I2C_SPEED_FAST,
112 .speed_config[0] = {
113 .speed = I2C_SPEED_FAST,
114 .scl_lcnt = 160,
115 .scl_hcnt = 79,
116 .sda_hold = 7,
117 }
118 },
119 .i2c[2] = {
120 .speed = I2C_SPEED_FAST,
121 .speed_config[0] = {
122 .speed = I2C_SPEED_FAST,
123 .scl_lcnt = 157,
124 .scl_hcnt = 79,
125 .sda_hold = 7,
126 }
127 },
128 .i2c[3] = {
129 .speed = I2C_SPEED_FAST,
130 .speed_config[0] = {
131 .speed = I2C_SPEED_FAST,
132 .scl_lcnt = 157,
133 .scl_hcnt = 79,
134 .sda_hold = 7,
135 }
136 },
137 .i2c[5] = {
138 .speed = I2C_SPEED_FAST,
139 .speed_config[0] = {
140 .speed = I2C_SPEED_FAST,
141 .scl_lcnt = 152,
142 .scl_hcnt = 79,
143 .sda_hold = 7,
144 }
145 },
146 }"
147
148 device domain 0 on
149 device ref dtt on
150 chip drivers/intel/dptf
151 ## sensor information
152 register "options.tsr[0].desc" = ""CPU_VR""
153 register "options.tsr[1].desc" = ""CPU""
154 register "options.tsr[2].desc" = ""Ambient""
155 register "options.tsr[3].desc" = ""Charger""
156
157 # TODO: below values are initial reference values only
158 ## Passive Policy
159 register "policies.passive" = "{
160 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
161 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
162 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
163 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
164 [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 75, 5000),
165 }"
166
167 ## Critical Policy
168 register "policies.critical" = "{
169 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
170 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN),
171 }"
172
173 register "controls.power_limits" = "{
174 .pl1 = {
175 .min_power = 6000,
176 .max_power = 15000,
177 .time_window_min = 28 * MSECS_PER_SEC,
178 .time_window_max = 32 * MSECS_PER_SEC,
179 .granularity = 200
180 },
181 .pl2 = {
182 .min_power = 25000,
183 .max_power = 25000,
184 .time_window_min = 28 * MSECS_PER_SEC,
185 .time_window_max = 32 * MSECS_PER_SEC,
186 .granularity = 1000
187 }
188 }"
189
190 ## Charger Performance Control (Control, mA)
191 register "controls.charger_perf" = "{
192 [0] = { 255, 3000 },
193 [1] = { 24, 1500 },
194 [2] = { 16, 1000 },
195 [3] = { 8, 500 }
196 }"
197
198 device generic 0 on end
199 end
200 end
201 device ref igpu on
202 chip drivers/gfx/generic
203 register "device_count" = "4"
204 # DDIA for eDP
205 register "device[0].name" = ""LCD""
206 # Internal panel on the first port of the graphics chip
207 register "device[0].addr" = "0x80010400"
208 # DDIB for HDMI
209 # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
210 register "device[1].name" = ""DD01""
211 # TCP0 (DP-1) for port C0
212 register "device[2].name" = ""DD02""
213 register "device[2].use_pld" = "true"
214 register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
215 # TCP1 (DP-2) for port C1
216 register "device[3].name" = ""DD03""
217 register "device[3].use_pld" = "true"
218 register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
219 device generic 0 on end
220 end
221 end
222 device ref ipu on
223 chip drivers/intel/mipi_camera
224 register "acpi_uid" = "0x50000"
225 register "acpi_name" = ""IPU0""
226 register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
227
228 register "cio2_num_ports" = "1"
229 register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
230 register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
231 register "cio2_prt[0]" = "1"
232 device generic 0 on
233 probe CAMERA UF_720P_WF
234 probe CAMERA UF_1080P_WF
235 end
236 end
237 end
238 device ref i2c1 on
239 chip drivers/i2c/hid
240 register "generic.hid" = ""ILTK0001""
241 register "generic.desc" = ""ILITEK Touchscreen""
242 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
243 register "generic.detect" = "1"
244 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
245 register "generic.reset_delay_ms" = "200"
246 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)"
247 register "generic.enable_delay_ms" = "12"
248 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
249 register "generic.stop_off_delay_ms" = "200"
250 register "generic.has_power_resource" = "1"
251 register "hid_desc_reg_offset" = "0x01"
252 device i2c 41 on end
253 end
254 chip drivers/generic/gpio_keys
255 register "name" = ""PENH""
256 register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
257 register "key.wake_gpe" = "GPE0_DW2_15"
258 register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
259 register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
260 register "key.dev_name" = ""EJCT""
261 register "key.linux_code" = "SW_PEN_INSERTED"
262 register "key.linux_input_type" = "EV_SW"
263 register "key.label" = ""pen_eject""
264 device generic 0 on end
265 end
266 end
267 device ref i2c2 on
268 chip drivers/intel/mipi_camera
269 register "acpi_hid" = ""OVTIDB10""
270 register "acpi_uid" = "0"
271 register "acpi_name" = ""CAM0""
272 register "chip_name" = ""Ov 13b10 Camera""
273 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
274
275 register "ssdb.lanes_used" = "4"
276 register "ssdb.vcm_type" = "0x0C"
277 register "vcm_name" = ""VCM0""
278 register "num_freq_entries" = "1"
279 register "link_freq[0]" = "560 * MHz"
280 register "remote_name" = ""IPU0""
281
282 register "has_power_resource" = "1"
283 #Controls
284 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
285 register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
286
287 register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X
288 register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X
289 register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L
290
291 #_ON
292 register "on_seq.ops_cnt" = "5"
293 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
294 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
295 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
296 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
297 register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
298
299 #_OFF
300 register "off_seq.ops_cnt" = "4"
301 register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
302 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
303 register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
304 register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
305
306 device i2c 36 on
307 probe CAMERA UF_720P_WF
308 probe CAMERA UF_1080P_WF
309 end
310 end
311 chip drivers/intel/mipi_camera
312 register "acpi_uid" = "2"
313 register "acpi_name" = ""VCM0""
314 register "chip_name" = ""DW9714 VCM ""
315 register "device_type" = "INTEL_ACPI_CAMERA_VCM"
316
317 register "vcm_compat" = ""dongwoon,dw9714""
318
319 register "has_power_resource" = "1"
320 #Controls
321 register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_AFVDD
322
323 #_ON
324 register "on_seq.ops_cnt" = "1"
325 register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
326
327 #_OFF
328 register "off_seq.ops_cnt" = "1"
329 register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
330
331 device i2c 0C on
332 probe CAMERA UF_720P_WF
333 probe CAMERA UF_1080P_WF
334 end
335 end
336 chip drivers/intel/mipi_camera
337 register "acpi_uid" = "1"
338 register "acpi_name" = ""NVM0""
339 register "chip_name" = ""GT24P64E""
340 register "device_type" = "INTEL_ACPI_CAMERA_NVM"
341
342 register "nvm_size" = "0x2000"
343 register "nvm_pagesize" = "1"
344 register "nvm_readonly" = "1"
345 register "nvm_width" = "0x10"
346 register "nvm_compat" = ""atmel,24c64""
347
348 device i2c 50 on
349 probe CAMERA UF_720P_WF
350 probe CAMERA UF_1080P_WF
351 end
352 end
353 end
354 device ref i2c3 on
355 chip drivers/i2c/generic
356 register "hid" = ""10EC5650""
357 register "name" = ""RT58""
358 register "desc" = ""Realtek RT5650""
359 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
360 register "property_count" = "1"
361 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
362 register "property_list[0].name" = ""realtek,jd-mode""
363 register "property_list[0].integer" = "2"
364 device i2c 1a on end
365 end
366 end
367 device ref i2c5 on
368 chip drivers/i2c/hid
369 register "generic.hid" = ""PNP0C50""
370 register "generic.desc" = ""PRIMAX Touchpad""
371 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
372 register "generic.wake" = "GPE0_DW2_14"
373 register "generic.detect" = "1"
374 register "hid_desc_reg_offset" = "0x01"
375 device i2c 15 on end
376 end
377 end
378 device ref cnvi_wifi on
379 chip drivers/wifi/generic
380 register "wake" = "GPE0_PME_B0"
381 register "enable_cnvi_ddr_rfim" = "true"
382 register "add_acpi_dma_property" = "true"
383 device generic 0 on end
384 end
385 end
386 device ref pcie_rp4 on
387 # PCIe 4 WLAN
388 register "pch_pcie_rp[PCH_RP(4)]" = "{
389 .clk_src = 2,
390 .clk_req = 2,
391 .flags = PCIE_RP_LTR | PCIE_RP_AER,
392 }"
393 chip drivers/wifi/generic
394 register "wake" = "GPE0_DW1_03"
395 register "add_acpi_dma_property" = "true"
396 device pci 00.0 on end
397 end
398 end
399 device ref pch_espi on
400 chip ec/google/chromeec
401 use conn0 as mux_conn[0]
402 use conn1 as mux_conn[1]
403 device pnp 0c09.0 on end
404 end
405 end
406 device ref pmc hidden
407 chip drivers/intel/pmc_mux
408 device generic 0 on
409 chip drivers/intel/pmc_mux/conn
410 use usb2_port1 as usb2_port
411 use tcss_usb3_port2 as usb3_port
412 device generic 0 alias conn0 on end
413 end
414 chip drivers/intel/pmc_mux/conn
415 use usb2_port2 as usb2_port
416 use tcss_usb3_port1 as usb3_port
417 device generic 1 alias conn1 on end
418 end
419 end
420 end
421 end
422 device ref tcss_xhci on
423 chip drivers/usb/acpi
424 device ref tcss_root_hub on
425 chip drivers/usb/acpi
426 register "desc" = ""USB3 Type-C Port C0 (MLB)""
427 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
428 register "use_custom_pld" = "true"
429 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
430 device ref tcss_usb3_port2 on end
431 end
432 chip drivers/usb/acpi
433 register "desc" = ""USB3 Type-C Port C1 (DB)""
434 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
435 register "use_custom_pld" = "true"
436 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
437 device ref tcss_usb3_port1 on end
438 end
439 end
440 end
441 end
442 device ref xhci on
443 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
444 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
445 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch)
446 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch)
447 register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch)
448 register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
449 register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
450 register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for CNVi WLAN
451
452 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB))
453 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
454 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE)
455 chip drivers/usb/acpi
456 device ref xhci_root_hub on
457 chip drivers/usb/acpi
458 register "desc" = ""USB2 Type-C Port C0 (MLB)""
459 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
460 register "use_custom_pld" = "true"
461 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
462 device ref usb2_port1 on end
463 end
464 chip drivers/usb/acpi
465 register "desc" = ""USB2 Type-C Port C1 (DB)""
466 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
467 register "use_custom_pld" = "true"
468 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
469 device ref usb2_port2 on end
470 end
471 chip drivers/usb/acpi
472 register "desc" = ""USB2 Type-A Port A0 (MLB)""
473 register "type" = "UPC_TYPE_A"
474 register "use_custom_pld" = "true"
475 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
476 device ref usb2_port3 on end
477 end
478 chip drivers/usb/acpi
479 register "desc" = ""USB2 Type-A Port A1 (DB)""
480 register "type" = "UPC_TYPE_A"
481 register "use_custom_pld" = "true"
482 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
483 device ref usb2_port4 on end
484 end
485 chip drivers/usb/acpi
486 register "desc" = ""USB2 LTE""
487 register "type" = "UPC_TYPE_INTERNAL"
488 device ref usb2_port5 on end
489 end
490 chip drivers/usb/acpi
491 register "desc" = ""USB2 UFC""
492 register "type" = "UPC_TYPE_INTERNAL"
493 device ref usb2_port6 on end
494 end
495 chip drivers/usb/acpi
496 register "desc" = ""PCIe Bluetooth""
497 register "type" = "UPC_TYPE_INTERNAL"
498 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
499 device ref usb2_port8 on end
500 end
501 chip drivers/usb/acpi
502 register "desc" = ""CNVi Bluetooth""
503 register "type" = "UPC_TYPE_INTERNAL"
504 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
505 device ref usb2_port10 on end
506 end
507 chip drivers/usb/acpi
508 register "desc" = ""USB3 Type-A Port A0 (MLB)""
509 register "type" = "UPC_TYPE_USB3_A"
510 register "use_custom_pld" = "true"
511 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
512 device ref usb3_port1 on end
513 end
514 chip drivers/usb/acpi
515 register "desc" = ""USB3 Type-A Port A1 (DB)""
516 register "type" = "UPC_TYPE_USB3_A"
517 register "use_custom_pld" = "true"
518 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
519 device ref usb3_port2 on end
520 end
521 chip drivers/usb/acpi
522 register "desc" = ""USB3 WWAN""
523 register "type" = "UPC_TYPE_INTERNAL"
524 device ref usb3_port3 on end
525 end
526 chip drivers/usb/acpi
527 register "desc" = ""USB3 WLAN""
528 register "type" = "UPC_TYPE_INTERNAL"
529 device ref usb3_port4 on end
530 end
531 end
532 end
533 end
534 device ref pcie_rp7 off end # SDCard
535 device ref hda on
536 chip drivers/sof
537 register "spkr_tplg" = "rt5650_sp"
538 register "jack_tplg" = "rt5650_hp"
539 register "mic_tplg" = "_2ch_pdm0"
540 device generic 0 on end
541 end
542 end
543 end
544 end
coreboot repo mirror