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cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / google / brya / variants / gothrax / overridetree.cb
blobb36ff07453bc03369cc6ace361e85a139ec50411
1 fw_config
2 field DB_USB 0 1
3 option DB_NONE 0
4 option DB_C_A 1
5 option DB_C_A_LTE 2
6 option DB_A 3
7 end
8 field THERMAL_SOLUTION 2
9 option THERMAL_SOLUTION_PASSIVE 0
10 option THERMAL_SOLUTION_ACTIVE 1
11 end
12 field WLAN 3 4
13 option WLAN_MT7921_AZUREWAVE 0
14 option WLAN_AX211_Intel 1
15 end
16 field AUDIO 5 6
17 option AUDIO_ALC1019_ALC5682IVS 0
18 end
19 field STYLUS 7
20 option STYLUS_ABSENT 0
21 option STYLUS_PRESENT 1
22 end
23 field WFC 8
24 option WFC_PRESENT 0
25 option WFC_ABSENT 1
26 end
27 end
28
29 chip soc/intel/alderlake
30 register "sagv" = "SaGv_Enabled"
31
32 # EMMC Tx CMD Delay
33 # Refer to EDS-Vol2-42.3.7.
34 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
35 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
36 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
37
38 # EMMC TX DATA Delay 1
39 # Refer to EDS-Vol2-42.3.8.
40 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
41 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
42 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
43
44 # EMMC TX DATA Delay 2
45 # Refer to EDS-Vol2-42.3.9.
46 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
47 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
48 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
49 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
50 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
51
52 # EMMC RX CMD/DATA Delay 1
53 # Refer to EDS-Vol2-42.3.10.
54 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
55 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
56 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
57 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
58 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
59
60 # EMMC RX CMD/DATA Delay 2
61 # Refer to EDS-Vol2-42.3.12.
62 # [17:16] stands for Rx Clock before Output Buffer,
63 # 00: Rx clock after output buffer,
64 # 01: Rx clock before output buffer,
65 # 10: Automatic selection based on working mode.
66 # 11: Reserved
67 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
68 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
69 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10005"
70
71 # EMMC Rx Strobe Delay
72 # Refer to EDS-Vol2-42.3.11.
73 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
74 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
75 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
76
77 # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
78 # Bit 2 - C1 has a redriver which does SBU muxing.
79 # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
80 register "tcss_aux_ori" = "5"
81
82 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
83 register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
84
85 # Configure external V1P05/Vnn/VnnSx Rails
86 register "ext_fivr_settings" = "{
87 .configure_ext_fivr = 1,
88 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
89 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
90 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
91 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
92 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
93 .v1p05_voltage_mv = 1050,
94 .vnn_voltage_mv = 780,
95 .vnn_sx_voltage_mv = 1050,
96 .v1p05_icc_max_ma = 500,
97 .vnn_icc_max_ma = 500,
98 }"
99
100 # Intel Common SoC Config
101 #+-------------------+---------------------------+
102 #| Field | Value |
103 #+-------------------+---------------------------+
104 #| I2C0 | TPM. Early init is |
105 #| | required to set up a BAR |
106 #| | for TPM communication |
107 #| I2C1 | Touchscreen |
108 #| I2C2 | Sub-board(PSensor)/WCAM |
109 #| I2C3 | Audio |
110 #| I2C5 | Trackpad |
111 #+-------------------+---------------------------+
112 register "common_soc_config" = "{
113 .i2c[0] = {
114 .early_init = 1,
115 .speed = I2C_SPEED_FAST_PLUS,
116 .speed_config[0] = {
117 .speed = I2C_SPEED_FAST_PLUS,
118 .scl_lcnt = 55,
119 .scl_hcnt = 30,
120 .sda_hold = 7,
121 }
122 },
123 .i2c[1] = {
124 .speed = I2C_SPEED_FAST,
125 .speed_config[0] = {
126 .speed = I2C_SPEED_FAST,
127 .scl_lcnt = 160,
128 .scl_hcnt = 79,
129 .sda_hold = 7,
130 }
131 },
132 .i2c[2] = {
133 .speed = I2C_SPEED_FAST,
134 .speed_config[0] = {
135 .speed = I2C_SPEED_FAST,
136 .scl_lcnt = 157,
137 .scl_hcnt = 79,
138 .sda_hold = 7,
139 }
140 },
141 .i2c[3] = {
142 .speed = I2C_SPEED_FAST,
143 .speed_config[0] = {
144 .speed = I2C_SPEED_FAST,
145 .scl_lcnt = 157,
146 .scl_hcnt = 79,
147 .sda_hold = 7,
148 }
149 },
150 .i2c[5] = {
151 .speed = I2C_SPEED_FAST,
152 .speed_config[0] = {
153 .speed = I2C_SPEED_FAST,
154 .scl_lcnt = 152,
155 .scl_hcnt = 79,
156 .sda_hold = 7,
157 }
158 },
159 }"
160
161 device domain 0 on
162 device ref dtt on
163 chip drivers/intel/dptf
164 ## sensor information
165 register "options.tsr[0].desc" = ""Memory""
166 register "options.tsr[1].desc" = ""Charger""
167 register "options.tsr[2].desc" = ""Ambient""
168
169 # TODO: below values are initial reference values only
170 ## Passive Policy
171 register "policies.passive" = "{
172 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
173 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
174 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
175 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
176 }"
177
178 ## Critical Policy
179 register "policies.critical" = "{
180 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
181 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
182 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
183 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
184 }"
185
186 register "controls.power_limits" = "{
187 .pl1 = {
188 .min_power = 3000,
189 .max_power = 6000,
190 .time_window_min = 28 * MSECS_PER_SEC,
191 .time_window_max = 32 * MSECS_PER_SEC,
192 .granularity = 200
193 },
194 .pl2 = {
195 .min_power = 25000,
196 .max_power = 25000,
197 .time_window_min = 28 * MSECS_PER_SEC,
198 .time_window_max = 32 * MSECS_PER_SEC,
199 .granularity = 1000
200 }
201 }"
202
203 ## Charger Performance Control (Control, mA)
204 register "controls.charger_perf" = "{
205 [0] = { 255, 1700 },
206 [1] = { 24, 1500 },
207 [2] = { 16, 1000 },
208 [3] = { 8, 500 }
209 }"
210
211 device generic 0 on end
212 end
213 end
214 device ref i2c1 on
215 chip drivers/i2c/hid
216 register "generic.hid" = ""ELAN7B13""
217 register "generic.desc" = ""ELAN Touchscreen""
218 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
219 register "generic.detect" = "1"
220 register "generic.reset_gpio" =
221 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
222 register "generic.reset_delay_ms" = "300"
223 register "generic.reset_off_delay_ms" = "2"
224 register "generic.enable_gpio" =
225 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
226 register "generic.enable_delay_ms" = "6"
227 register "generic.has_power_resource" = "1"
228 register "hid_desc_reg_offset" = "0x01"
229 device i2c 0x10 on end
230 end
231 end
232 device ref i2c2 on
233 chip drivers/i2c/sx9324
234 register "desc" = ""SAR2 Proximity Sensor""
235 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
236 register "speed" = "I2C_SPEED_FAST"
237 register "uid" = "1"
238 register "reg_gnrl_ctrl0" = "0x16"
239 register "reg_gnrl_ctrl1" = "0x21"
240 register "reg_afe_ctrl0" = "0x20"
241 register "reg_afe_ctrl1" = "0x10"
242 register "reg_afe_ctrl2" = "0x00"
243 register "reg_afe_ctrl3" = "0x01"
244 register "reg_afe_ctrl4" = "0x46"
245 register "reg_afe_ctrl5" = "0x00"
246 register "reg_afe_ctrl6" = "0x00"
247 register "reg_afe_ctrl7" = "0x07"
248 register "reg_afe_ctrl8" = "0x12"
249 register "reg_afe_ctrl9" = "0x0f"
250 register "reg_prox_ctrl0" = "0x12"
251 register "reg_prox_ctrl1" = "0x12"
252 register "reg_prox_ctrl2" = "0x90"
253 register "reg_prox_ctrl3" = "0x60"
254 register "reg_prox_ctrl4" = "0x0c"
255 register "reg_prox_ctrl5" = "0x12"
256 register "reg_prox_ctrl6" = "0x3c"
257 register "reg_prox_ctrl7" = "0x58"
258 register "reg_adv_ctrl0" = "0x00"
259 register "reg_adv_ctrl1" = "0x00"
260 register "reg_adv_ctrl2" = "0x00"
261 register "reg_adv_ctrl3" = "0x00"
262 register "reg_adv_ctrl4" = "0x00"
263 register "reg_adv_ctrl5" = "0x05"
264 register "reg_adv_ctrl6" = "0x00"
265 register "reg_adv_ctrl7" = "0x00"
266 register "reg_adv_ctrl8" = "0x00"
267 register "reg_adv_ctrl9" = "0x00"
268 register "reg_adv_ctrl10" = "0x5c"
269 register "reg_adv_ctrl11" = "0x52"
270 register "reg_adv_ctrl12" = "0xb5"
271 register "reg_adv_ctrl13" = "0x00"
272 register "reg_adv_ctrl14" = "0x80"
273 register "reg_adv_ctrl15" = "0x0c"
274 register "reg_adv_ctrl16" = "0x38"
275 register "reg_adv_ctrl17" = "0x56"
276 register "reg_adv_ctrl18" = "0x33"
277 register "reg_adv_ctrl19" = "0xf0"
278 register "reg_adv_ctrl20" = "0xf0"
279
280 register "ph0_pin" = "{1, 3, 3}"
281 register "ph1_pin" = "{3, 2, 1}"
282 register "ph2_pin" = "{3, 3, 1}"
283 register "ph3_pin" = "{1, 3, 3}"
284 register "ph01_resolution" = "512"
285 register "ph23_resolution" = "1024"
286 register "startup_sensor" = "1"
287 register "ph01_proxraw_strength" = "2"
288 register "ph23_proxraw_strength" = "2"
289 register "avg_pos_strength" = "256"
290 register "cs_idle_sleep" = ""gnd""
291 register "int_comp_resistor" = ""lowest""
292 register "input_precharge_resistor_ohms" = "4000"
293 register "input_analog_gain" = "3"
294 device i2c 28 on
295 probe DB_USB DB_C_A_LTE
296 end
297 end
298 end
299 device ref i2c3 on
300 chip drivers/i2c/generic
301 register "hid" = ""RTL5682""
302 register "name" = ""RT58""
303 register "desc" = ""Headset Codec""
304 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
305 # Set the jd_src to RT5668_JD1 for jack detection
306 register "property_count" = "1"
307 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
308 register "property_list[0].name" = ""realtek,jd-src""
309 register "property_list[0].integer" = "1"
310 device i2c 1a on end
311 end
312 chip drivers/generic/alc1015
313 register "hid" = ""RTL1019""
314 register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
315 device generic 0 on end
316 end
317 end
318
319 device ref i2c5 on
320 chip drivers/i2c/hid
321 register "generic.hid" = ""PNP0C50""
322 register "generic.desc" = ""PIXART Touchpad""
323 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
324 register "generic.wake" = "GPE0_DW2_14"
325 register "generic.detect" = "1"
326 register "hid_desc_reg_offset" = "0x01"
327 device i2c 15 on end
328 end
329 end
330 device ref pcie_rp4 on
331 # PCIe 4 WLAN
332 register "pch_pcie_rp[PCH_RP(4)]" = "{
333 .clk_src = 2,
334 .clk_req = 2,
335 .flags = PCIE_RP_LTR | PCIE_RP_AER,
336 }"
337 chip drivers/wifi/generic
338 register "wake" = "GPE0_DW1_03"
339 register "add_acpi_dma_property" = "true"
340 device pci 00.0 on end
341 end
342 end
343 device ref pcie_rp7 on
344 # Enable SD Card PCIe 7 using clk 3
345 register "pch_pcie_rp[PCH_RP(7)]" = "{
346 .clk_src = 3,
347 .clk_req = 3,
348 .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
349 }"
350 chip soc/intel/common/block/pcie/rtd3
351 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
352 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
353 register "srcclk_pin" = "3"
354 device generic 0 on end
355 end
356 end
357 device ref pch_espi on
358 chip ec/google/chromeec
359 use conn0 as mux_conn[0]
360 use conn1 as mux_conn[1]
361 device pnp 0c09.0 on end
362 end
363 end
364 device ref pmc hidden
365 chip drivers/intel/pmc_mux
366 device generic 0 on
367 chip drivers/intel/pmc_mux/conn
368 use usb2_port1 as usb2_port
369 use tcss_usb3_port1 as usb3_port
370 device generic 0 alias conn0 on end
371 end
372 chip drivers/intel/pmc_mux/conn
373 use usb2_port2 as usb2_port
374 use tcss_usb3_port2 as usb3_port
375 device generic 1 alias conn1 on end
376 end
377 end
378 end
379 end
380 device ref tcss_xhci on
381 chip drivers/usb/acpi
382 device ref tcss_root_hub on
383 chip drivers/usb/acpi
384 register "desc" = ""USB3 Type-C Port C0 (MLB)""
385 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
386 register "use_custom_pld" = "true"
387 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
388 device ref tcss_usb3_port1 on end
389 end
390 chip drivers/usb/acpi
391 register "desc" = ""USB3 Type-C Port C1 (DB)""
392 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
393 register "use_custom_pld" = "true"
394 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
395 device ref tcss_usb3_port2 on
396 probe DB_USB DB_C_A
397 probe DB_USB DB_C_A_LTE
398 end
399 end
400 end
401 end
402 end
403 device ref xhci on
404 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
405 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
406 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
407 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
408 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1
409
410 chip drivers/usb/acpi
411 device ref xhci_root_hub on
412 chip drivers/usb/acpi
413 register "desc" = ""USB2 Type-C Port C0 (MLB)""
414 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
415 register "use_custom_pld" = "true"
416 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
417 device ref usb2_port1 on end
418 end
419 chip drivers/usb/acpi
420 register "desc" = ""USB2 Type-C Port C1 (DB)""
421 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
422 register "use_custom_pld" = "true"
423 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
424 device ref usb2_port2 on
425 probe DB_USB DB_C_A
426 probe DB_USB DB_C_A_LTE
427 end
428 end
429 chip drivers/usb/acpi
430 register "desc" = ""USB2 Type-A Port A0 (MLB)""
431 register "type" = "UPC_TYPE_A"
432 register "use_custom_pld" = "true"
433 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
434 device ref usb2_port3 on end
435 end
436 chip drivers/usb/acpi
437 register "desc" = ""USB2 Type-A Port A1 (DB)""
438 register "type" = "UPC_TYPE_A"
439 register "use_custom_pld" = "true"
440 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
441 device ref usb2_port4 on end
442 end
443 chip drivers/usb/acpi
444 register "desc" = ""USB2 WWAN""
445 register "type" = "UPC_TYPE_INTERNAL"
446 device ref usb2_port5 on
447 probe DB_USB DB_C_A_LTE
448 end
449 end
450 chip drivers/usb/acpi
451 register "desc" = ""USB2 UFC""
452 register "type" = "UPC_TYPE_INTERNAL"
453 device ref usb2_port6 on end
454 end
455 chip drivers/usb/acpi
456 register "desc" = ""USB2 WFC""
457 register "type" = "UPC_TYPE_INTERNAL"
458 device ref usb2_port7 on
459 probe WFC WFC_PRESENT
460 end
461 end
462 chip drivers/usb/acpi
463 register "desc" = ""USB2 Bluetooth""
464 register "type" = "UPC_TYPE_INTERNAL"
465 register "reset_gpio" =
466 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
467 device ref usb2_port8 on end
468 end
469 chip drivers/usb/acpi
470 register "desc" = ""CNVi Bluetooth""
471 register "type" = "UPC_TYPE_INTERNAL"
472 register "reset_gpio" =
473 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
474 device ref usb2_port10 on end
475 end
476 chip drivers/usb/acpi
477 register "desc" = ""USB3 Type-A Port A0 (MLB)""
478 register "type" = "UPC_TYPE_USB3_A"
479 register "use_custom_pld" = "true"
480 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
481 device ref usb3_port1 on end
482 end
483 chip drivers/usb/acpi
484 register "desc" = ""USB3 Type-A Port A1 (DB)""
485 register "type" = "UPC_TYPE_USB3_A"
486 register "use_custom_pld" = "true"
487 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
488 device ref usb3_port2 on end
489 end
490 chip drivers/usb/acpi
491 register "desc" = ""USB3 WWAN""
492 register "type" = "UPC_TYPE_INTERNAL"
493 device ref usb3_port3 on
494 probe DB_USB DB_C_A_LTE
495 end
496 end
497 end
498 end
499 end
500 device ref hda on
501 chip drivers/sof
502 register "spkr_tplg" = "rt1019"
503 register "jack_tplg" = "rt5682"
504 register "mic_tplg" = "_2ch_pdm0"
505 device generic 0 on end
506 end
507 end
508 end
509 end
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