1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 #include <acpi/acpigen.h>
5 #include <baseboard/variants.h>
7 #include <console/console.h>
9 #include <device/device.h>
10 #include <drivers/tpm/cr50.h>
12 #include <security/tpm/tss.h>
13 #include <soc/soc_chip.h>
17 static void mainboard_update_soc_chip_config(void)
19 struct soc_intel_jasperlake_config
*cfg
= config_of_soc();
23 if (rc
!= TPM_SUCCESS
) {
24 printk(BIOS_ERR
, "tlcl_lib_init() failed: %#x\n", rc
);
28 if (!cr50_is_long_interrupt_pulse_enabled()) {
29 /* Disable GPIO PM to allow for shorter IRQ pulses */
30 printk(BIOS_INFO
, "Override GPIO PM\n");
31 cfg
->gpio_override_pm
= 1;
32 memset(cfg
->gpio_pm
, 0, sizeof(cfg
->gpio_pm
));
36 static bool any_hpd_ready(const gpio_t
*gpios
, size_t num_gpios
)
38 for (size_t i
= 0; i
< num_gpios
; i
++) {
39 if (gpio_get(gpios
[i
]))
46 static void mainboard_wait_for_hpd(void)
48 static const long display_timeout_ms
= 3000;
51 const gpio_t
*hpd_gpios
= variant_hpd_gpios(&num_gpios
);
54 printk(BIOS_WARNING
, "No HPD GPIOs, skip waiting\n");
58 printk(BIOS_INFO
, "Waiting for HPD\n");
60 /* Pins will be configured back by gpio_configure_pads. */
61 for (size_t i
= 0; i
< num_gpios
; i
++) {
62 gpio_input(hpd_gpios
[i
]);
65 stopwatch_init_msecs_expire(&sw
, display_timeout_ms
);
66 while (!any_hpd_ready(hpd_gpios
, num_gpios
)) {
67 if (stopwatch_expired(&sw
)) {
69 "HPD not ready after %ld ms. Abort.\n",
75 printk(BIOS_INFO
, "HPD ready after %lld ms\n",
76 stopwatch_duration_msecs(&sw
));
79 static void mainboard_init(void *chip_info
)
81 const struct pad_config
*base_pads
;
82 const struct pad_config
*override_pads
;
83 size_t base_num
, override_num
;
86 * For chromeboxes, wait for DP HPD to be asserted before
87 * entering FSP-S, otherwise display init may fail.
89 if (!CONFIG(SYSTEM_TYPE_LAPTOP
) && display_init_required())
90 mainboard_wait_for_hpd();
92 base_pads
= baseboard_gpio_table(&base_num
);
93 override_pads
= variant_override_gpio_table(&override_num
);
95 gpio_configure_pads_with_override(base_pads
, base_num
,
96 override_pads
, override_num
);
98 variant_devtree_update();
100 if (CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
))
101 mainboard_update_soc_chip_config();
104 void __weak
variant_devtree_update(void)
106 /* Override dev tree settings per board */
109 static void mainboard_dev_init(struct device
*dev
)
114 static unsigned long mainboard_write_acpi_tables(
115 const struct device
*device
, unsigned long current
, acpi_rsdp_t
*rsdp
)
120 static void mainboard_generate_s0ix_hook(void)
122 acpigen_write_if_lequal_op_int(ARG0_OP
, 1);
123 variant_generate_s0ix_hook(S0IX_ENTRY
);
124 acpigen_write_else();
125 variant_generate_s0ix_hook(S0IX_EXIT
);
126 acpigen_write_if_end();
129 static void mainboard_fill_ssdt(const struct device
*dev
)
132 acpigen_write_scope("\\_SB");
133 acpigen_write_method_serialized("MS0X", 1);
134 mainboard_generate_s0ix_hook();
135 acpigen_write_method_end(); /* Method */
136 acpigen_write_scope_end(); /* Scope */
140 void __weak
variant_generate_s0ix_hook(enum s0ix_entry entry
)
143 /* Add board-specific MS0X entries */
145 if (s0ix_entry == S0IX_ENTRY) {
146 implement variant operations here
148 if (s0ix_entry == S0IX_EXIT) {
149 implement variant operations here
155 static void mainboard_enable(struct device
*dev
)
157 dev
->ops
->init
= mainboard_dev_init
;
158 dev
->ops
->write_acpi_tables
= mainboard_write_acpi_tables
;
159 dev
->ops
->acpi_fill_ssdt
= mainboard_fill_ssdt
;
162 struct chip_operations mainboard_ops
= {
163 .init
= mainboard_init
,
164 .enable_dev
= mainboard_enable
,