src/mainboard/google/dedede/variants/baseboard/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <baseboard/gpio.h>
   5 #include <gpio.h>
   6 #include <soc/meminit.h>
   7 #include <soc/romstage.h>
   8
   9 static const struct mb_cfg baseboard_memcfg_cfg = {
  10
  11         .dq_map[DDR_CH0] = {
  12                 {0xf, 0xf0},
  13                 {0xf, 0xf0},
  14                 {0xff, 0x0},
  15                 {0x0, 0x0},
  16                 {0x0, 0x0},
  17                 {0x0, 0x0}
  18         },
  19         .dq_map[DDR_CH1] = {
  20                 {0xf, 0xf0},
  21                 {0xf, 0xf0},
  22                 {0xff, 0x0},
  23                 {0x0, 0x0},
  24                 {0x00, 0x0},
  25                 {0x00, 0x0}
  26         },
  27
  28         /*
  29          * The dqs_map arrays map the ddr4 pins to the SoC pins
  30          * for both channels.
  31          *
  32          * the index = pin number on SoC
  33          * the value = pin number on LPDDR4 part
  34          */
  35
  36         .dqs_map[DDR_CH0] = {1, 3, 0, 2, 7, 5, 4, 6},
  37         .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 5, 7, 6},
  38
  39         /* Disable Early Command Training */
  40         .ect = 1,
  41
  42         /* User Board Type */
  43         .UserBd = BOARD_TYPE_MOBILE,
  44 };
  45
  46 const struct mb_cfg *__weak variant_memcfg_config(void)
  47 {
  48         return &baseboard_memcfg_cfg;
  49 }
  50
  51 int __weak variant_memory_sku(void)
  52 {
  53         gpio_t spd_gpios[] = {
  54                 GPIO_MEM_CONFIG_0,
  55                 GPIO_MEM_CONFIG_1,
  56                 GPIO_MEM_CONFIG_2,
  57                 GPIO_MEM_CONFIG_3,
  58         };
  59
  60         return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
  61 }
  62
  63 bool __weak variant_mem_is_half_populated(void)
  64 {
  65         return !gpio_get(GPIO_MEM_CH_SEL);
  66 }