src/mainboard/google/fizz/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <baseboard/variants.h>
   5 #include <bootmode.h>
   6 #include <chip.h>
   7 #include <console/console.h>
   8 #include <delay.h>
   9 #include <device/device.h>
  10 #include <ec/ec.h>
  11 #include <ec/google/chromeec/ec.h>
  12 #include <gpio.h>
  13 #include <intelblocks/power_limit.h>
  14 #include <smbios.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/nhlt.h>
  17 #include <string.h>
  18 #include <timer.h>
  19
  20 #include <variant/gpio.h>
  21
  22 #define FIZZ_SKU_ID_I7_U42  0x4
  23 #define FIZZ_SKU_ID_I5_U42  0x5
  24 #define FIZZ_SKU_ID_I3_U42  0x6
  25 #define FIZZ_SKU_ID_I7_U22  0x3
  26 #define FIZZ_SKU_ID_I5_U22  0x2
  27 #define FIZZ_SKU_ID_I3_U22  0x1
  28 #define FIZZ_SKU_ID_CEL_U22 0x0
  29 #define FIZZ_PL2_U42        44
  30 #define FIZZ_PL2_U22        29
  31 #define FIZZ_PSYSPL2_U22    65
  32 #define FIZZ_PSYSPL2_U42    90
  33 #define FIZZ_MAX_TIME_WINDOW 6
  34 #define FIZZ_MIN_DUTYCYCLE   4
  35 /*
  36  * For type-C chargers, set PL2 to 90% of max power to account for
  37  * cable loss and FET Rdson loss in the path from the source.
  38  */
  39 #define SET_PSYSPL2(w)     (9 * (w) / 10)
  40
  41 static uint8_t read_sku_id_from_gpio(void)
  42 {
  43         const gpio_t sku_id_gpios[] = {
  44                 GPIO_SKU_ID0,
  45                 GPIO_SKU_ID1,
  46                 GPIO_SKU_ID2,
  47                 GPIO_SKU_ID3,
  48         };
  49         return gpio_base2_value(sku_id_gpios, ARRAY_SIZE(sku_id_gpios));
  50 }
  51
  52 static uint8_t board_sku_id(void)
  53 {
  54         static int sku_id = -1;
  55
  56         if (sku_id < 0) {
  57                 uint32_t id;
  58                 if (google_chromeec_cbi_get_sku_id(&id))
  59                         /* TODO: Once transition completes, raise error instead
  60                            of returning gpio value which could be unintended. */
  61                         /* Reading from EC may succeed next time but we do not
  62                            want to return different values. So, we cache the
  63                            value read from GPIOs. */
  64                         id = read_sku_id_from_gpio();
  65                 sku_id = id;
  66         }
  67
  68         return sku_id;
  69 }
  70
  71 /*
  72  * mainboard_set_power_limits
  73  *
  74  * Set Pl2 and SysPl2 values based on detected charger.
  75  * If detected barrel jack, use values below based on SKU.
  76  * definitions:
  77  * x = no value entered. Use default value in parenthesis.
  78  *     will set 0 to anything that shouldn't be set.
  79  * n = max value of power adapter.
  80  * +-------------+-----+---------+-----------+-------+
  81  * | sku_id      | PL2 | PsysPL2 |  PsysPL3  |  PL4  |
  82  * +-------------+-----+---------+-----------+-------+
  83  * | i7 U42      |  44 |   81    | x(.85PL4) | x(71) |
  84  * | i5 U42      |  44 |   81    | x(.85PL4) | x(71) |
  85  * | i3 U42      |  44 |   81    | x(.85PL4) | x(71) |
  86  * | i7 U22      |  29 |   58    | x(.85PL4) | x(43) |
  87  * | i5 U22      |  29 |   58    | x(.85PL4) | x(43) |
  88  * | i3 U22      |  29 |   58    | x(.85PL4) | x(43) |
  89  * | celeron U22 |  29 |   58    | x(.85PL4) | x(43) |
  90  * +-------------+-----+---------+-----------+-------+
  91  * For USB C charger:
  92  * +-------------+-----+---------+---------+-------+
  93  * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 |  PL4  |
  94  * +-------------+-----+---------+---------+-------+
  95  * | 60 (U42)    |  44 |   54    |    54   |   54  |
  96  * | 60 (U22)    |  29 |   54    |    54   | x(43) |
  97  * | n  (U42)    |  44 |   .9n   |   .9n   |  .9n  |
  98  * | n  (U22)    |  29 |   .9n   |   .9n   | x(43) |
  99  * +-------------+-----+---------+---------+-------+
 100  */
 101 static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
 102 {
 103         enum usb_chg_type type;
 104         u32 watts;
 105         u16 volts_mv, current_ma;
 106         u32 pl2, psyspl2;
 107         int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
 108         uint8_t sku = board_sku_id();
 109         const uint32_t u42_mask = (1 << FIZZ_SKU_ID_I7_U42) |
 110                                   (1 << FIZZ_SKU_ID_I5_U42) |
 111                                   (1 << FIZZ_SKU_ID_I3_U42);
 112
 113         /* PL2 value is sku-based, no matter what charger we are using */
 114         pl2 = FIZZ_PL2_U22;
 115         if ((1 << sku) & u42_mask)
 116                 pl2 = FIZZ_PL2_U42;
 117         conf->tdp_psyspl3 = conf->tdp_pl4 = 0;
 118
 119         /* If we can't get charger info or not PD charger, assume barrel jack */
 120         if (rv != 0 || type != USB_CHG_TYPE_PD) {
 121                 /* using the barrel jack, get PsysPL2 based on sku id */
 122                 psyspl2 = FIZZ_PSYSPL2_U22;
 123                 /* Running a U42 SKU */
 124                 if ((1 << sku) & u42_mask)
 125                         psyspl2 = FIZZ_PSYSPL2_U42;
 126         } else {
 127                 /* Detected TypeC.  Base on max value of adapter */
 128                 watts = ((u32)volts_mv * current_ma) / 1000000;
 129                 psyspl2 = watts;
 130                 conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
 131                 /* set max possible time window */
 132                 conf->tdp_psyspl3_time = FIZZ_MAX_TIME_WINDOW;
 133                 /* set minimum duty cycle */
 134                 conf->tdp_psyspl3_dutycycle = FIZZ_MIN_DUTYCYCLE;
 135                 if ((1 << sku) & u42_mask)
 136                         conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
 137         }
 138
 139         conf->tdp_pl2_override = pl2;
 140         /* set psyspl2 to 90% of max adapter power */
 141         conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
 142 }
 143
 144 static uint8_t read_oem_id_from_gpio(void)
 145 {
 146         const gpio_t oem_id_gpios[] = {
 147                 GPIO_OEM_ID1,
 148                 GPIO_OEM_ID2,
 149                 GPIO_OEM_ID3,
 150         };
 151         return gpio_base2_value(oem_id_gpios, ARRAY_SIZE(oem_id_gpios));
 152 }
 153
 154 static uint8_t board_oem_id(void)
 155 {
 156         static int oem_id = -1;
 157
 158         if (oem_id < 0) {
 159                 uint32_t id;
 160                 if (google_chromeec_cbi_get_oem_id(&id))
 161                         /* TODO: Once transition completes, raise error instead
 162                            of returning gpio value which could be unintended. */
 163                         /* Reading from EC may succeed next time but we do not
 164                            want to return different values. So, we cache the
 165                            value read from GPIOs. */
 166                         id = read_oem_id_from_gpio();
 167                 oem_id = id;
 168         }
 169
 170         return oem_id;
 171 }
 172
 173 const char *smbios_system_sku(void)
 174 {
 175         static char sku_str[7]; /* sku{0..255} */
 176
 177         snprintf(sku_str, sizeof(sku_str), "sku%d", board_oem_id());
 178
 179         return sku_str;
 180 }
 181
 182 const char *fizz_oem_name[] = {
 183         "Kench",
 184         "Teemo",
 185         "Sion",
 186         "Wukong",
 187         "Wukong",
 188         "Wukong",
 189         "Teemo",
 190         "Karma",
 191         "Jax",
 192         "Endeavour",
 193         "Excelsior"
 194 };
 195
 196 const char *smbios_mainboard_product_name(void)
 197 {
 198         return fizz_oem_name[board_oem_id()];
 199 }
 200
 201 static void mainboard_init(struct device *dev)
 202 {
 203         mainboard_ec_init();
 204 }
 205
 206 static unsigned long mainboard_write_acpi_tables(
 207         const struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
 208 {
 209         const char *oem_id = NULL;
 210         const char *oem_table_id = NULL;
 211         uint32_t oem_revision = 0;
 212         uintptr_t start_addr;
 213         uintptr_t end_addr;
 214         struct nhlt *nhlt;
 215
 216         start_addr = current;
 217
 218         nhlt = nhlt_init();
 219         if (!nhlt)
 220                 return start_addr;
 221
 222         variant_nhlt_init(nhlt);
 223         variant_nhlt_oem_overrides(&oem_id, &oem_table_id, &oem_revision);
 224
 225         end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,
 226                                 oem_id, oem_table_id, oem_revision);
 227
 228         if (end_addr != start_addr)
 229                 acpi_add_table(rsdp, (void *)start_addr);
 230
 231         return end_addr;
 232 }
 233
 234 static void mainboard_enable(struct device *dev)
 235 {
 236         struct soc_power_limits_config *soc_conf;
 237         config_t *conf = config_of_soc();
 238
 239         soc_conf = &conf->power_limits_config;
 240         mainboard_set_power_limits(soc_conf);
 241
 242         dev->ops->init = mainboard_init;
 243         dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 244 }
 245
 246 #define GPIO_HDMI_HPD           GPP_E13
 247 #define GPIO_DP_HPD             GPP_E14
 248
 249 /* TODO: This can be moved to common directory */
 250 static void wait_for_hpd(gpio_t gpio, long timeout)
 251 {
 252         struct stopwatch sw;
 253
 254         printk(BIOS_INFO, "Waiting for HPD\n");
 255         gpio_input(gpio);
 256
 257         stopwatch_init_msecs_expire(&sw, timeout);
 258         while (!gpio_get(gpio)) {
 259                 if (stopwatch_expired(&sw)) {
 260                         printk(BIOS_WARNING,
 261                                "HPD not ready after %ldms. Abort.\n", timeout);
 262                         return;
 263                 }
 264                 mdelay(200);
 265         }
 266         printk(BIOS_INFO, "HPD ready after %lld ms\n",
 267                stopwatch_duration_msecs(&sw));
 268 }
 269
 270 void __weak variant_chip_display_init(void)
 271 {
 272         static const long display_timeout_ms = 3000;
 273
 274         /* This is reconfigured back to whatever FSP-S expects by
 275            gpio_configure_pads. */
 276         gpio_input(GPIO_HDMI_HPD);
 277         if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) {
 278                 /* This has to be done before FSP-S runs. */
 279                 if (google_chromeec_wait_for_displayport(display_timeout_ms))
 280                         wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
 281         }
 282 }
 283
 284 static void mainboard_chip_init(void *chip_info)
 285 {
 286         const struct pad_config *pads;
 287         size_t num;
 288
 289         variant_chip_display_init();
 290
 291         pads = variant_gpio_table(&num);
 292         gpio_configure_pads(pads, num);
 293 }
 294
 295 struct chip_operations mainboard_ops = {
 296         .init = mainboard_chip_init,
 297         .enable_dev = mainboard_enable,
 298 };