src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <types.h>
   6 #include <vendorcode/google/chromeos/chromeos.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config gpio_table[] = {
  10
  11         /* WWAN_WAKE_N */
  12         PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT),
  13
  14         /* DDI1_HPD */
  15         PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  16
  17         /* DDI0_HPD */
  18         PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  19
  20         /* M.2_WWAN_DISABLE_N */
  21         PAD_CFG_GPO(GPP_A19, 1, PLTRST),
  22
  23         /* PMC_CORE_VID0 */
  24         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  25
  26         /* PMC_CORE_VID1 */
  27         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  28
  29         /* PMC_SLP_S0_N */
  30         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  31
  32         /* PMC_PLT_RST_N */
  33         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  34
  35         /* CAM1_RST_N */
  36         PAD_CFG_GPO(GPP_B14, 0, PLTRST),
  37
  38         /* M.2_WLAN_PERST_N */
  39         PAD_CFG_GPO(GPP_B17, 1, PLTRST),
  40
  41         /* GSPI1_CS0_N */
  42         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
  43
  44         /* GSPI1_CLK */
  45         PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
  46
  47         /* GSPI1_MISO */
  48         PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
  49
  50         /* GSPI1_MOSI */
  51         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
  52
  53         /* DDI2_HPD */
  54         PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
  55
  56         /* WWAN_PERST_N */
  57         PAD_CFG_GPO(GPP_C0, 0, PLTRST),
  58
  59         /* M2_WWAN_SSD_SKT2_CFG2 */
  60         PAD_CFG_GPI(GPP_C3, NONE, PLTRST),
  61
  62         /* SLP_LAN_N */
  63         PAD_CFG_GPO(GPP_C7, 0, PLTRST),
  64
  65         /* I2C0_SDA */
  66         PAD_CFG_NF(GPP_C16, UP_2K, DEEP, NF1),
  67
  68         /* I2C0_SCL */
  69         PAD_CFG_NF(GPP_C17, UP_2K, DEEP, NF1),
  70
  71         /* CAM2_RST_N */
  72         PAD_CFG_GPO(GPP_C19, 0, PLTRST),
  73
  74         /* WIFI_RF_KILL_N */
  75         PAD_CFG_GPO(GPP_D0, 1, PLTRST),
  76
  77         /* BT_RF_KILL_N */
  78         PAD_CFG_GPO(GPP_D1, 1, PLTRST),
  79
  80         /* CAM2_PWREN */
  81         PAD_CFG_GPO(GPP_D4, 0, PLTRST),
  82
  83         /* CAM1_PWREN */
  84         PAD_CFG_GPO(GPP_D5, 0, PLTRST),
  85
  86         /*LAN_RST_N*/
  87         PAD_CFG_GPO(GPP_D6, 1, PLTRST),
  88
  89         /* I2C4B_SDA */
  90         PAD_CFG_NF(GPP_D12, NONE, DEEP, NF3),
  91
  92         /* I2C4B_SCL */
  93         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),
  94
  95         /* AVS_I2S_MCLK */
  96         PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
  97
  98         /* CNV_MFUART2_RXD */
  99         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 100
 101         /* CNV_MFUART2_TXD */
 102         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 103
 104         /* CNV_PA_BLANKING */
 105         PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 106
 107         /* I2C5_SDA */
 108         PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),
 109
 110         /* I2C5_SCL */
 111         PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF1),
 112
 113         /* IMGCLKOUT_0 */
 114         PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2),
 115
 116         /* IMGCLKOUT_1 */
 117         PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1),
 118
 119         /* WWAN_FCP_OFF_N */
 120         PAD_CFG_GPO(GPP_E3, 1, PLTRST),
 121
 122         /* DDI0_DDC_SCL */
 123         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 124
 125         /* DDI0_DDC_SDA */
 126         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 127
 128         /* DDI1_DDC_SCL */
 129         PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
 130
 131         /* DDI1_DDC_SDA */
 132         PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
 133
 134         /* DDI2_DDC_SCL */
 135         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 136
 137         /* DDI2_DDC_SDA */
 138         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
 139
 140         /* CNV_BRI_DT */
 141         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 142
 143         /* CNV_BRI_RSP */
 144         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 145
 146         /* CNV_RGI_DT */
 147         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
 148
 149         /* CNV_RGI_RSP */
 150         PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
 151
 152         /* CNV_RF_RESET_B */
 153         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 154
 155         /* EMMC_CMD */
 156         PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
 157
 158         /* EMMC_DATA0 */
 159         PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
 160
 161         /* EMMC_DATA1 */
 162         PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
 163
 164         /* EMMC_DATA2 */
 165         PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
 166
 167         /* EMMC_DATA3 */
 168         PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
 169
 170         /* EMMC_DATA4 */
 171         PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
 172
 173         /* EMMC_DATA5 */
 174         PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
 175
 176         /* EMMC_DATA6 */
 177         PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
 178
 179         /* EMMC_DATA7 */
 180         PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 181
 182         /* EMMC_RCLK */
 183         PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
 184
 185         /* EMMC_CLK */
 186         PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
 187
 188         /* EMMC_RESET_N */
 189         PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
 190
 191         /* SD_SDIO_CMD */
 192         PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 193
 194         /* SD_SDIO_D0 */
 195         PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 196
 197         /* SD_SDIO_D1 */
 198         PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
 199
 200         /* SD_SDIO_D2 */
 201         PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
 202
 203         /* SD_SDIO_D3 */
 204         PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
 205
 206         /* SD_SDIO_CD_N */
 207         PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1),
 208
 209         /* SD_SDIO_CLK */
 210         PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 211
 212         /* SD_SDIO_WP */
 213         PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1),
 214
 215         /* FPS_INT */
 216         PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT),
 217
 218         /* SD_SDIO_PWR_EN_N */
 219         PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
 220
 221         /* MODEM_CLKREQ0 */
 222         PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
 223
 224         /* WWAN EN GPIO */
 225         PAD_CFG_GPO(GPP_H7, 1, PLTRST),
 226
 227         /* CPU_C10_GATE_N */
 228         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
 229
 230         /* M.2_BT_I2S2_SCLK */
 231         PAD_CFG_GPI(GPP_H11, NONE, PLTRST),
 232
 233         /* CNV_RF_RESET_N */
 234         PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2),
 235
 236         /* PCH_INT_ODL */
 237         PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
 238
 239         /* M.2_BT_I2S2_RXD */
 240         PAD_CFG_GPI(GPP_H14, NONE, PLTRST),
 241
 242         /* AVS_I2S1_SCLK */
 243         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 244
 245         /* Audio Jack Detection */
 246         PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, EDGE_BOTH),
 247
 248         /* M2_CNVI_EN_N */
 249         PAD_CFG_GPO(GPP_H19, 0, PLTRST),
 250
 251         /* AVS_I2S0_SCLK */
 252         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
 253
 254         /* AVS_I2S0_SFRM */
 255         PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
 256
 257         /* AVS_I2S0_TXD */
 258         PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
 259
 260         /* AVS_I2S0_RXD */
 261         PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
 262
 263         /* AVS_I2S1_RXD */
 264         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
 265
 266         /* AVS_I2S1_SFRM */
 267         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),
 268
 269         /* AVS_I2S1_TXD */
 270         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1),
 271
 272         /* WWAN RST_N */
 273         PAD_CFG_GPO(GPP_S0, 1, DEEP),
 274
 275         /* DMIC_CLK_1 */
 276         PAD_CFG_NF(GPP_S2, UP_20K, DEEP, NF2),
 277
 278         /* DMIC_DATA_1 */
 279         PAD_CFG_NF(GPP_S3, UP_20K, DEEP, NF2),
 280
 281         /* DMIC_CLK_0 */
 282         PAD_CFG_NF(GPP_S6, UP_20K, DEEP, NF2),
 283
 284         /* DMIC_DATA_0 */
 285         PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2),
 286
 287         /* PMC_BATLOW_N */
 288         PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 289
 290         /* PMC_ACPRESENT */
 291         PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 292
 293         /* LAN_WAKE_N */
 294         PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 295
 296         /* PMC_PWR_BTN_N */
 297         PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
 298
 299         /* PMC_SLP_S3_N */
 300         PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 301
 302         /* PMC_SLP_S4_N */
 303         PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 304
 305         /* PMC_SUSCLK */
 306         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 307
 308         /* virtual GPIO for SD card detect */
 309         PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP),
 310 };
 311
 312 /* Early pad configuration in bootblock */
 313 static const struct pad_config early_gpio_table[] = {
 314 #if CONFIG(BOARD_INTEL_JASPERLAKE_RVP_EXT_EC)
 315         /* UART2 RX */
 316         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 317
 318         /* UART2 TX */
 319         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 320 #endif
 321
 322         /* GSPI1_CS# */
 323         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
 324
 325         /* GSPI1_CLK */
 326         PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
 327
 328         /* GSPI1_MISO */
 329         PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
 330
 331         /* GSPI1_MOSI */
 332         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
 333
 334         /* PCH_INT_ODL */
 335         PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
 336 };
 337
 338 const struct pad_config *variant_gpio_table(size_t *num)
 339 {
 340         *num = ARRAY_SIZE(gpio_table);
 341         return gpio_table;
 342 }
 343
 344 const struct pad_config *variant_early_gpio_table(size_t *num)
 345 {
 346         *num = ARRAY_SIZE(early_gpio_table);
 347         return early_gpio_table;
 348 }
 349
 350 static const struct cros_gpio cros_gpios[] = {
 351         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
 352 };
 353
 354 DECLARE_CROS_GPIOS(cros_gpios);